| commit | c7073853ebcbb8a94af0ef405cb05f94b7fd02e5 | |
| author | Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> | |
| Wed, 29 Nov 2023 14:21:27 +0000 (29 15:21 +0100) | ||
| committer | Antonio Borneo <borneo.antonio@gmail.com> | |
| Sat, 13 Jan 2024 14:47:31 +0000 (13 14:47 +0000) | ||
| tree | 8f9734cf410df9d8adc10851491e2f497218d01a | treesnapshot (tar.gz zip) |
| parent | 995a7af21d6f97f628382e26dc21dc38e4fa846e | commitdiff |
contrib/firmware: Add direction control for 'SCL' i2c signal
We want to keep the tri-state buffers located between the FPGA
and the board, in 'Z' state until we launch an i2c connection.
We launch an i2c start condition, make the SCL
direction 'OUT' to start the i2c protocol and at the end
of the i2c connection at the stop condition, we re-make
the tri-state buffers at 'Z' state.
Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7989
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
We want to keep the tri-state buffers located between the FPGA
and the board, in 'Z' state until we launch an i2c connection.
We launch an i2c start condition, make the SCL
direction 'OUT' to start the i2c protocol and at the end
of the i2c connection at the stop condition, we re-make
the tri-state buffers at 'Z' state.
Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7989
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>