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flash/nor/stm32f1x: fix minor error messages
[openocd.git] / src / flash / nor / stm32f1x.c
bloba0144c260e7a134193fa4cf6f816fb377d7c3033
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 int probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t offset, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = 0;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes */
233 retval = target_read_u32(target, STM32_OB_RDP, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = option_bytes & 0xFF;
238 stm32x_info->option_bytes.user = (option_bytes >> 16) & 0xFF;
239
240 /* read user data option bytes */
241 retval = target_read_u32(target, STM32_OB_DATA0, &option_bytes);
242 if (retval != ERROR_OK)
243 return retval;
244
245 stm32x_info->option_bytes.data = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
246
247 /* read write protection option bytes */
248 retval = target_read_u32(target, STM32_OB_WRP0, &option_bytes);
249 if (retval != ERROR_OK)
250 return retval;
251
252 stm32x_info->option_bytes.protection = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
253
254 retval = target_read_u32(target, STM32_OB_WRP2, &option_bytes);
255 if (retval != ERROR_OK)
256 return retval;
257
258 stm32x_info->option_bytes.protection |= (((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF)) << 16;
259
260 return ERROR_OK;
261 }
262
263 static int stm32x_erase_options(struct flash_bank *bank)
264 {
265 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
266 struct target *target = bank->target;
267
268 /* read current options */
269 stm32x_read_options(bank);
270
271 /* unlock flash registers */
272 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
273 if (retval != ERROR_OK)
274 return retval;
275
276 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
277 if (retval != ERROR_OK)
278 return retval;
279
280 /* unlock option flash registers */
281 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
282 if (retval != ERROR_OK)
283 return retval;
284 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
285 if (retval != ERROR_OK)
286 return retval;
287
288 /* erase option bytes */
289 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
290 if (retval != ERROR_OK)
291 return retval;
292 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
293 if (retval != ERROR_OK)
294 return retval;
295
296 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
297 if (retval != ERROR_OK)
298 return retval;
299
300 /* clear read protection option byte
301 * this will also force a device unlock if set */
302 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
303
304 return ERROR_OK;
305 }
306
307 static int stm32x_write_options(struct flash_bank *bank)
308 {
309 struct stm32x_flash_bank *stm32x_info = NULL;
310 struct target *target = bank->target;
311
312 stm32x_info = bank->driver_priv;
313
314 /* unlock flash registers */
315 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
316 if (retval != ERROR_OK)
317 return retval;
318 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
319 if (retval != ERROR_OK)
320 return retval;
321
322 /* unlock option flash registers */
323 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
324 if (retval != ERROR_OK)
325 return retval;
326 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
327 if (retval != ERROR_OK)
328 return retval;
329
330 /* program option bytes */
331 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
332 if (retval != ERROR_OK)
333 return retval;
334
335 uint8_t opt_bytes[16];
336
337 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
338 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
339 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
340 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
341 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
342 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
343 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
344 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
345
346 uint32_t offset = STM32_OB_RDP - bank->base;
347 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
348 if (retval != ERROR_OK) {
349 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
350 LOG_ERROR("working area required to erase options bytes");
351 return retval;
352 }
353
354 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
355 if (retval != ERROR_OK)
356 return retval;
357
358 return ERROR_OK;
359 }
360
361 static int stm32x_protect_check(struct flash_bank *bank)
362 {
363 struct target *target = bank->target;
364 uint32_t protection;
365
366 int retval = stm32x_check_operation_supported(bank);
367 if (ERROR_OK != retval)
368 return retval;
369
370 /* medium density - each bit refers to a 4 sector protection block
371 * high density - each bit refers to a 2 sector protection block
372 * bit 31 refers to all remaining sectors in a bank */
373 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
374 if (retval != ERROR_OK)
375 return retval;
376
377 for (int i = 0; i < bank->num_prot_blocks; i++)
378 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
379
380 return ERROR_OK;
381 }
382
383 static int stm32x_erase(struct flash_bank *bank, int first, int last)
384 {
385 struct target *target = bank->target;
386 int i;
387
388 if (bank->target->state != TARGET_HALTED) {
389 LOG_ERROR("Target not halted");
390 return ERROR_TARGET_NOT_HALTED;
391 }
392
393 if ((first == 0) && (last == (bank->num_sectors - 1)))
394 return stm32x_mass_erase(bank);
395
396 /* unlock flash registers */
397 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
398 if (retval != ERROR_OK)
399 return retval;
400 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
401 if (retval != ERROR_OK)
402 return retval;
403
404 for (i = first; i <= last; i++) {
405 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
406 if (retval != ERROR_OK)
407 return retval;
408 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
409 bank->base + bank->sectors[i].offset);
410 if (retval != ERROR_OK)
411 return retval;
412 retval = target_write_u32(target,
413 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
414 if (retval != ERROR_OK)
415 return retval;
416
417 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
418 if (retval != ERROR_OK)
419 return retval;
420
421 bank->sectors[i].is_erased = 1;
422 }
423
424 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
425 if (retval != ERROR_OK)
426 return retval;
427
428 return ERROR_OK;
429 }
430
431 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
432 {
433 struct target *target = bank->target;
434 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
435
436 if (target->state != TARGET_HALTED) {
437 LOG_ERROR("Target not halted");
438 return ERROR_TARGET_NOT_HALTED;
439 }
440
441 int retval = stm32x_check_operation_supported(bank);
442 if (retval != ERROR_OK)
443 return retval;
444
445 retval = stm32x_erase_options(bank);
446 if (retval != ERROR_OK) {
447 LOG_ERROR("stm32x failed to erase options");
448 return retval;
449 }
450
451 for (int i = first; i <= last; i++) {
452 if (set)
453 stm32x_info->option_bytes.protection &= ~(1 << i);
454 else
455 stm32x_info->option_bytes.protection |= (1 << i);
456 }
457
458 return stm32x_write_options(bank);
459 }
460
461 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
462 uint32_t offset, uint32_t count)
463 {
464 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
465 struct target *target = bank->target;
466 uint32_t buffer_size = 16384;
467 struct working_area *write_algorithm;
468 struct working_area *source;
469 uint32_t address = bank->base + offset;
470 struct reg_param reg_params[5];
471 struct armv7m_algorithm armv7m_info;
472 int retval = ERROR_OK;
473
474 static const uint8_t stm32x_flash_write_code[] = {
475 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
476 };
477
478 /* flash write code */
479 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
480 &write_algorithm) != ERROR_OK) {
481 LOG_WARNING("no working area available, can't do block memory writes");
482 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
483 }
484
485 retval = target_write_buffer(target, write_algorithm->address,
486 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
487 if (retval != ERROR_OK) {
488 target_free_working_area(target, write_algorithm);
489 return retval;
490 }
491
492 /* memory buffer */
493 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
494 buffer_size /= 2;
495 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
496 if (buffer_size <= 256) {
497 /* we already allocated the writing code, but failed to get a
498 * buffer, free the algorithm */
499 target_free_working_area(target, write_algorithm);
500
501 LOG_WARNING("no large enough working area available, can't do block memory writes");
502 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
503 }
504 }
505
506 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
507 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
508 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
509 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
510 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
511
512 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
513 buf_set_u32(reg_params[1].value, 0, 32, count);
514 buf_set_u32(reg_params[2].value, 0, 32, source->address);
515 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
516 buf_set_u32(reg_params[4].value, 0, 32, address);
517
518 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
519 armv7m_info.core_mode = ARM_MODE_THREAD;
520
521 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
522 0, NULL,
523 5, reg_params,
524 source->address, source->size,
525 write_algorithm->address, 0,
526 &armv7m_info);
527
528 if (retval == ERROR_FLASH_OPERATION_FAILED) {
529 LOG_ERROR("flash write failed at address 0x%"PRIx32,
530 buf_get_u32(reg_params[4].value, 0, 32));
531
532 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
533 LOG_ERROR("flash memory not erased before writing");
534 /* Clear but report errors */
535 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
536 }
537
538 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
539 LOG_ERROR("flash memory write protected");
540 /* Clear but report errors */
541 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
542 }
543 }
544
545 target_free_working_area(target, source);
546 target_free_working_area(target, write_algorithm);
547
548 destroy_reg_param(&reg_params[0]);
549 destroy_reg_param(&reg_params[1]);
550 destroy_reg_param(&reg_params[2]);
551 destroy_reg_param(&reg_params[3]);
552 destroy_reg_param(&reg_params[4]);
553
554 return retval;
555 }
556
557 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
558 uint32_t offset, uint32_t count)
559 {
560 struct target *target = bank->target;
561 uint8_t *new_buffer = NULL;
562
563 if (bank->target->state != TARGET_HALTED) {
564 LOG_ERROR("Target not halted");
565 return ERROR_TARGET_NOT_HALTED;
566 }
567
568 if (offset & 0x1) {
569 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
570 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
571 }
572
573 /* If there's an odd number of bytes, the data has to be padded. Duplicate
574 * the buffer and use the normal code path with a single block write since
575 * it's probably cheaper than to special case the last odd write using
576 * discrete accesses. */
577 if (count & 1) {
578 new_buffer = malloc(count + 1);
579 if (new_buffer == NULL) {
580 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
581 return ERROR_FAIL;
582 }
583 LOG_INFO("odd number of bytes to write, padding with 0xff");
584 buffer = memcpy(new_buffer, buffer, count);
585 new_buffer[count++] = 0xff;
586 }
587
588 uint32_t words_remaining = count / 2;
589 int retval, retval2;
590
591 /* unlock flash registers */
592 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
593 if (retval != ERROR_OK)
594 goto cleanup;
595 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
596 if (retval != ERROR_OK)
597 goto cleanup;
598
599 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
600 if (retval != ERROR_OK)
601 goto cleanup;
602
603 /* try using a block write */
604 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
605
606 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
607 /* if block write failed (no sufficient working area),
608 * we use normal (slow) single halfword accesses */
609 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
610
611 while (words_remaining > 0) {
612 uint16_t value;
613 memcpy(&value, buffer, sizeof(uint16_t));
614
615 retval = target_write_u16(target, bank->base + offset, value);
616 if (retval != ERROR_OK)
617 goto reset_pg_and_lock;
618
619 retval = stm32x_wait_status_busy(bank, 5);
620 if (retval != ERROR_OK)
621 goto reset_pg_and_lock;
622
623 words_remaining--;
624 buffer += 2;
625 offset += 2;
626 }
627 }
628
629 reset_pg_and_lock:
630 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
631 if (retval == ERROR_OK)
632 retval = retval2;
633
634 cleanup:
635 if (new_buffer)
636 free(new_buffer);
637
638 return retval;
639 }
640
641 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
642 {
643 /* This check the device CPUID core register to detect
644 * the M0 from the M3 devices. */
645
646 struct target *target = bank->target;
647 uint32_t cpuid, device_id_register = 0;
648
649 /* Get the CPUID from the ARM Core
650 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
651 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
652 if (retval != ERROR_OK)
653 return retval;
654
655 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
656 /* 0xC20 is M0 devices */
657 device_id_register = 0x40015800;
658 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
659 /* 0xC23 is M3 devices */
660 device_id_register = 0xE0042000;
661 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
662 /* 0xC24 is M4 devices */
663 device_id_register = 0xE0042000;
664 } else {
665 LOG_ERROR("Cannot identify target as a stm32x");
666 return ERROR_FAIL;
667 }
668
669 /* read stm32 device id register */
670 retval = target_read_u32(target, device_id_register, device_id);
671 if (retval != ERROR_OK)
672 return retval;
673
674 return retval;
675 }
676
677 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
678 {
679 struct target *target = bank->target;
680 uint32_t cpuid, flash_size_reg;
681
682 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
683 if (retval != ERROR_OK)
684 return retval;
685
686 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
687 /* 0xC20 is M0 devices */
688 flash_size_reg = 0x1FFFF7CC;
689 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
690 /* 0xC23 is M3 devices */
691 flash_size_reg = 0x1FFFF7E0;
692 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
693 /* 0xC24 is M4 devices */
694 flash_size_reg = 0x1FFFF7CC;
695 } else {
696 LOG_ERROR("Cannot identify target as a stm32x");
697 return ERROR_FAIL;
698 }
699
700 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
701 if (retval != ERROR_OK)
702 return retval;
703
704 return retval;
705 }
706
707 static int stm32x_probe(struct flash_bank *bank)
708 {
709 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
710 uint16_t flash_size_in_kb;
711 uint16_t max_flash_size_in_kb;
712 uint32_t device_id;
713 int page_size;
714 uint32_t base_address = 0x08000000;
715
716 stm32x_info->probed = 0;
717 stm32x_info->register_base = FLASH_REG_BASE_B0;
718 stm32x_info->user_data_offset = 10;
719 stm32x_info->option_offset = 0;
720
721 /* default factory read protection level 0 */
722 stm32x_info->default_rdp = 0xA5;
723
724 /* read stm32 device id register */
725 int retval = stm32x_get_device_id(bank, &device_id);
726 if (retval != ERROR_OK)
727 return retval;
728
729 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
730
731 /* set page size, protection granularity and max flash size depending on family */
732 switch (device_id & 0xfff) {
733 case 0x410: /* medium density */
734 page_size = 1024;
735 stm32x_info->ppage_size = 4;
736 max_flash_size_in_kb = 128;
737 break;
738 case 0x412: /* low density */
739 page_size = 1024;
740 stm32x_info->ppage_size = 4;
741 max_flash_size_in_kb = 32;
742 break;
743 case 0x414: /* high density */
744 page_size = 2048;
745 stm32x_info->ppage_size = 2;
746 max_flash_size_in_kb = 512;
747 break;
748 case 0x418: /* connectivity line density */
749 page_size = 2048;
750 stm32x_info->ppage_size = 2;
751 max_flash_size_in_kb = 256;
752 break;
753 case 0x420: /* value line density */
754 page_size = 1024;
755 stm32x_info->ppage_size = 4;
756 max_flash_size_in_kb = 128;
757 break;
758 case 0x422: /* stm32f302/3xb/c */
759 page_size = 2048;
760 stm32x_info->ppage_size = 2;
761 max_flash_size_in_kb = 256;
762 stm32x_info->user_data_offset = 16;
763 stm32x_info->option_offset = 6;
764 stm32x_info->default_rdp = 0xAA;
765 stm32x_info->can_load_options = true;
766 break;
767 case 0x446: /* stm32f303xD/E */
768 page_size = 2048;
769 stm32x_info->ppage_size = 2;
770 max_flash_size_in_kb = 512;
771 stm32x_info->user_data_offset = 16;
772 stm32x_info->option_offset = 6;
773 stm32x_info->default_rdp = 0xAA;
774 stm32x_info->can_load_options = true;
775 break;
776 case 0x428: /* value line High density */
777 page_size = 2048;
778 stm32x_info->ppage_size = 4;
779 max_flash_size_in_kb = 128;
780 break;
781 case 0x430: /* xl line density (dual flash banks) */
782 page_size = 2048;
783 stm32x_info->ppage_size = 2;
784 max_flash_size_in_kb = 1024;
785 stm32x_info->has_dual_banks = true;
786 break;
787 case 0x432: /* stm32f37x */
788 page_size = 2048;
789 stm32x_info->ppage_size = 2;
790 max_flash_size_in_kb = 256;
791 stm32x_info->user_data_offset = 16;
792 stm32x_info->option_offset = 6;
793 stm32x_info->default_rdp = 0xAA;
794 stm32x_info->can_load_options = true;
795 break;
796 case 0x438: /* stm32f33x */
797 case 0x439: /* stm32f302x6/8 */
798 page_size = 2048;
799 stm32x_info->ppage_size = 2;
800 max_flash_size_in_kb = 64;
801 stm32x_info->user_data_offset = 16;
802 stm32x_info->option_offset = 6;
803 stm32x_info->default_rdp = 0xAA;
804 stm32x_info->can_load_options = true;
805 break;
806 case 0x440: /* stm32f05x */
807 case 0x444: /* stm32f03x */
808 case 0x445: /* stm32f04x */
809 page_size = 1024;
810 stm32x_info->ppage_size = 4;
811 max_flash_size_in_kb = 64;
812 stm32x_info->user_data_offset = 16;
813 stm32x_info->option_offset = 6;
814 stm32x_info->default_rdp = 0xAA;
815 stm32x_info->can_load_options = true;
816 break;
817 case 0x448: /* stm32f07x */
818 case 0x442: /* stm32f09x */
819 page_size = 2048;
820 stm32x_info->ppage_size = 4;
821 max_flash_size_in_kb = 256;
822 stm32x_info->user_data_offset = 16;
823 stm32x_info->option_offset = 6;
824 stm32x_info->default_rdp = 0xAA;
825 stm32x_info->can_load_options = true;
826 break;
827 default:
828 LOG_WARNING("Cannot identify target as a STM32 family.");
829 return ERROR_FAIL;
830 }
831
832 /* get flash size from target. */
833 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
834
835 /* failed reading flash size or flash size invalid (early silicon),
836 * default to max target family */
837 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
838 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
839 max_flash_size_in_kb);
840 flash_size_in_kb = max_flash_size_in_kb;
841 }
842
843 if (stm32x_info->has_dual_banks) {
844 /* split reported size into matching bank */
845 if (bank->base != 0x08080000) {
846 /* bank 0 will be fixed 512k */
847 flash_size_in_kb = 512;
848 } else {
849 flash_size_in_kb -= 512;
850 /* bank1 also uses a register offset */
851 stm32x_info->register_base = FLASH_REG_BASE_B1;
852 base_address = 0x08080000;
853 }
854 }
855
856 /* if the user sets the size manually then ignore the probed value
857 * this allows us to work around devices that have a invalid flash size register value */
858 if (stm32x_info->user_bank_size) {
859 LOG_INFO("ignoring flash probed value, using configured bank size");
860 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
861 }
862
863 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
864
865 /* did we assign flash size? */
866 assert(flash_size_in_kb != 0xffff);
867
868 /* calculate numbers of pages */
869 int num_pages = flash_size_in_kb * 1024 / page_size;
870
871 /* check that calculation result makes sense */
872 assert(num_pages > 0);
873
874 if (bank->sectors) {
875 free(bank->sectors);
876 bank->sectors = NULL;
877 }
878
879 if (bank->prot_blocks) {
880 free(bank->prot_blocks);
881 bank->prot_blocks = NULL;
882 }
883
884 bank->base = base_address;
885 bank->size = (num_pages * page_size);
886
887 bank->num_sectors = num_pages;
888 bank->sectors = alloc_block_array(0, page_size, num_pages);
889 if (!bank->sectors)
890 return ERROR_FAIL;
891
892 /* calculate number of write protection blocks */
893 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
894 if (num_prot_blocks > 32)
895 num_prot_blocks = 32;
896
897 bank->num_prot_blocks = num_prot_blocks;
898 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
899 if (!bank->prot_blocks)
900 return ERROR_FAIL;
901
902 if (num_prot_blocks == 32)
903 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
904
905 stm32x_info->probed = 1;
906
907 return ERROR_OK;
908 }
909
910 static int stm32x_auto_probe(struct flash_bank *bank)
911 {
912 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
913 if (stm32x_info->probed)
914 return ERROR_OK;
915 return stm32x_probe(bank);
916 }
917
918 #if 0
919 COMMAND_HANDLER(stm32x_handle_part_id_command)
920 {
921 return ERROR_OK;
922 }
923 #endif
924
925 static const char *get_stm32f0_revision(uint16_t rev_id)
926 {
927 const char *rev_str = NULL;
928
929 switch (rev_id) {
930 case 0x1000:
931 rev_str = "1.0";
932 break;
933 case 0x2000:
934 rev_str = "2.0";
935 break;
936 }
937 return rev_str;
938 }
939
940 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
941 {
942 uint32_t dbgmcu_idcode;
943
944 /* read stm32 device id register */
945 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
946 if (retval != ERROR_OK)
947 return retval;
948
949 uint16_t device_id = dbgmcu_idcode & 0xfff;
950 uint16_t rev_id = dbgmcu_idcode >> 16;
951 const char *device_str;
952 const char *rev_str = NULL;
953
954 switch (device_id) {
955 case 0x410:
956 device_str = "STM32F10x (Medium Density)";
957
958 switch (rev_id) {
959 case 0x0000:
960 rev_str = "A";
961 break;
962
963 case 0x2000:
964 rev_str = "B";
965 break;
966
967 case 0x2001:
968 rev_str = "Z";
969 break;
970
971 case 0x2003:
972 rev_str = "Y";
973 break;
974 }
975 break;
976
977 case 0x412:
978 device_str = "STM32F10x (Low Density)";
979
980 switch (rev_id) {
981 case 0x1000:
982 rev_str = "A";
983 break;
984 }
985 break;
986
987 case 0x414:
988 device_str = "STM32F10x (High Density)";
989
990 switch (rev_id) {
991 case 0x1000:
992 rev_str = "A";
993 break;
994
995 case 0x1001:
996 rev_str = "Z";
997 break;
998
999 case 0x1003:
1000 rev_str = "Y";
1001 break;
1002 }
1003 break;
1004
1005 case 0x418:
1006 device_str = "STM32F10x (Connectivity)";
1007
1008 switch (rev_id) {
1009 case 0x1000:
1010 rev_str = "A";
1011 break;
1012
1013 case 0x1001:
1014 rev_str = "Z";
1015 break;
1016 }
1017 break;
1018
1019 case 0x420:
1020 device_str = "STM32F100 (Low/Medium Density)";
1021
1022 switch (rev_id) {
1023 case 0x1000:
1024 rev_str = "A";
1025 break;
1026
1027 case 0x1001:
1028 rev_str = "Z";
1029 break;
1030 }
1031 break;
1032
1033 case 0x422:
1034 device_str = "STM32F302xB/C";
1035
1036 switch (rev_id) {
1037 case 0x1000:
1038 rev_str = "A";
1039 break;
1040
1041 case 0x1001:
1042 rev_str = "Z";
1043 break;
1044
1045 case 0x1003:
1046 rev_str = "Y";
1047 break;
1048
1049 case 0x2000:
1050 rev_str = "B";
1051 break;
1052 }
1053 break;
1054
1055 case 0x428:
1056 device_str = "STM32F100 (High Density)";
1057
1058 switch (rev_id) {
1059 case 0x1000:
1060 rev_str = "A";
1061 break;
1062
1063 case 0x1001:
1064 rev_str = "Z";
1065 break;
1066 }
1067 break;
1068
1069 case 0x430:
1070 device_str = "STM32F10x (XL Density)";
1071
1072 switch (rev_id) {
1073 case 0x1000:
1074 rev_str = "A";
1075 break;
1076 }
1077 break;
1078
1079 case 0x432:
1080 device_str = "STM32F37x";
1081
1082 switch (rev_id) {
1083 case 0x1000:
1084 rev_str = "A";
1085 break;
1086
1087 case 0x2000:
1088 rev_str = "B";
1089 break;
1090 }
1091 break;
1092
1093 case 0x438:
1094 device_str = "STM32F33x";
1095
1096 switch (rev_id) {
1097 case 0x1000:
1098 rev_str = "A";
1099 break;
1100 }
1101 break;
1102
1103 case 0x439:
1104 device_str = "STM32F302x6/8";
1105
1106 switch (rev_id) {
1107 case 0x1000:
1108 rev_str = "A";
1109 break;
1110
1111 case 0x1001:
1112 rev_str = "Z";
1113 break;
1114 }
1115 break;
1116
1117 case 0x444:
1118 device_str = "STM32F03x";
1119 rev_str = get_stm32f0_revision(rev_id);
1120 break;
1121
1122 case 0x440:
1123 device_str = "STM32F05x";
1124 rev_str = get_stm32f0_revision(rev_id);
1125 break;
1126
1127 case 0x445:
1128 device_str = "STM32F04x";
1129 rev_str = get_stm32f0_revision(rev_id);
1130 break;
1131
1132 case 0x446:
1133 device_str = "STM32F303xD/E";
1134 switch (rev_id) {
1135 case 0x1000:
1136 rev_str = "A";
1137 break;
1138 }
1139 break;
1140
1141 case 0x448:
1142 device_str = "STM32F07x";
1143 rev_str = get_stm32f0_revision(rev_id);
1144 break;
1145
1146 case 0x442:
1147 device_str = "STM32F09x";
1148 rev_str = get_stm32f0_revision(rev_id);
1149 break;
1150
1151 default:
1152 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1153 return ERROR_FAIL;
1154 }
1155
1156 if (rev_str != NULL)
1157 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1158 else
1159 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1160
1161 return ERROR_OK;
1162 }
1163
1164 COMMAND_HANDLER(stm32x_handle_lock_command)
1165 {
1166 struct target *target = NULL;
1167 struct stm32x_flash_bank *stm32x_info = NULL;
1168
1169 if (CMD_ARGC < 1)
1170 return ERROR_COMMAND_SYNTAX_ERROR;
1171
1172 struct flash_bank *bank;
1173 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1174 if (ERROR_OK != retval)
1175 return retval;
1176
1177 stm32x_info = bank->driver_priv;
1178
1179 target = bank->target;
1180
1181 if (target->state != TARGET_HALTED) {
1182 LOG_ERROR("Target not halted");
1183 return ERROR_TARGET_NOT_HALTED;
1184 }
1185
1186 retval = stm32x_check_operation_supported(bank);
1187 if (ERROR_OK != retval)
1188 return retval;
1189
1190 if (stm32x_erase_options(bank) != ERROR_OK) {
1191 command_print(CMD_CTX, "stm32x failed to erase options");
1192 return ERROR_OK;
1193 }
1194
1195 /* set readout protection */
1196 stm32x_info->option_bytes.rdp = 0;
1197
1198 if (stm32x_write_options(bank) != ERROR_OK) {
1199 command_print(CMD_CTX, "stm32x failed to lock device");
1200 return ERROR_OK;
1201 }
1202
1203 command_print(CMD_CTX, "stm32x locked");
1204
1205 return ERROR_OK;
1206 }
1207
1208 COMMAND_HANDLER(stm32x_handle_unlock_command)
1209 {
1210 struct target *target = NULL;
1211
1212 if (CMD_ARGC < 1)
1213 return ERROR_COMMAND_SYNTAX_ERROR;
1214
1215 struct flash_bank *bank;
1216 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1217 if (ERROR_OK != retval)
1218 return retval;
1219
1220 target = bank->target;
1221
1222 if (target->state != TARGET_HALTED) {
1223 LOG_ERROR("Target not halted");
1224 return ERROR_TARGET_NOT_HALTED;
1225 }
1226
1227 retval = stm32x_check_operation_supported(bank);
1228 if (ERROR_OK != retval)
1229 return retval;
1230
1231 if (stm32x_erase_options(bank) != ERROR_OK) {
1232 command_print(CMD_CTX, "stm32x failed to erase options");
1233 return ERROR_OK;
1234 }
1235
1236 if (stm32x_write_options(bank) != ERROR_OK) {
1237 command_print(CMD_CTX, "stm32x failed to unlock device");
1238 return ERROR_OK;
1239 }
1240
1241 command_print(CMD_CTX, "stm32x unlocked.\n"
1242 "INFO: a reset or power cycle is required "
1243 "for the new settings to take effect.");
1244
1245 return ERROR_OK;
1246 }
1247
1248 COMMAND_HANDLER(stm32x_handle_options_read_command)
1249 {
1250 uint32_t optionbyte, protection;
1251 struct target *target = NULL;
1252 struct stm32x_flash_bank *stm32x_info = NULL;
1253
1254 if (CMD_ARGC < 1)
1255 return ERROR_COMMAND_SYNTAX_ERROR;
1256
1257 struct flash_bank *bank;
1258 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1259 if (ERROR_OK != retval)
1260 return retval;
1261
1262 stm32x_info = bank->driver_priv;
1263
1264 target = bank->target;
1265
1266 if (target->state != TARGET_HALTED) {
1267 LOG_ERROR("Target not halted");
1268 return ERROR_TARGET_NOT_HALTED;
1269 }
1270
1271 retval = stm32x_check_operation_supported(bank);
1272 if (ERROR_OK != retval)
1273 return retval;
1274
1275 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1276 if (retval != ERROR_OK)
1277 return retval;
1278
1279 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1280
1281 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1282 if (retval != ERROR_OK)
1283 return retval;
1284
1285 if (optionbyte & (1 << OPT_ERROR))
1286 command_print(CMD_CTX, "option byte complement error");
1287
1288 command_print(CMD_CTX, "option byte register = 0x%" PRIx32 "", optionbyte);
1289 command_print(CMD_CTX, "write protection register = 0x%" PRIx32 "", protection);
1290
1291 command_print(CMD_CTX, "read protection: %s",
1292 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1293
1294 /* user option bytes are offset depending on variant */
1295 optionbyte >>= stm32x_info->option_offset;
1296
1297 command_print(CMD_CTX, "watchdog: %sware",
1298 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1299
1300 command_print(CMD_CTX, "stop mode: %sreset generated upon entry",
1301 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1302
1303 command_print(CMD_CTX, "standby mode: %sreset generated upon entry",
1304 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1305
1306 if (stm32x_info->has_dual_banks)
1307 command_print(CMD_CTX, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1308
1309 command_print(CMD_CTX, "user data = 0x%02" PRIx16 "", user_data);
1310
1311 return ERROR_OK;
1312 }
1313
1314 COMMAND_HANDLER(stm32x_handle_options_write_command)
1315 {
1316 struct target *target = NULL;
1317 struct stm32x_flash_bank *stm32x_info = NULL;
1318 uint16_t optionbyte;
1319
1320 if (CMD_ARGC < 2)
1321 return ERROR_COMMAND_SYNTAX_ERROR;
1322
1323 struct flash_bank *bank;
1324 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1325 if (ERROR_OK != retval)
1326 return retval;
1327
1328 stm32x_info = bank->driver_priv;
1329
1330 target = bank->target;
1331
1332 if (target->state != TARGET_HALTED) {
1333 LOG_ERROR("Target not halted");
1334 return ERROR_TARGET_NOT_HALTED;
1335 }
1336
1337 retval = stm32x_check_operation_supported(bank);
1338 if (ERROR_OK != retval)
1339 return retval;
1340
1341 retval = stm32x_read_options(bank);
1342 if (ERROR_OK != retval)
1343 return retval;
1344
1345 /* start with current options */
1346 optionbyte = stm32x_info->option_bytes.user;
1347
1348 /* skip over flash bank */
1349 CMD_ARGC--;
1350 CMD_ARGV++;
1351
1352 while (CMD_ARGC) {
1353 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1354 optionbyte |= (1 << 0);
1355 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1356 optionbyte &= ~(1 << 0);
1357 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1358 optionbyte |= (1 << 1);
1359 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1360 optionbyte &= ~(1 << 1);
1361 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1362 optionbyte |= (1 << 2);
1363 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1364 optionbyte &= ~(1 << 2);
1365 else if (stm32x_info->has_dual_banks) {
1366 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1367 optionbyte |= (1 << 3);
1368 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1369 optionbyte &= ~(1 << 3);
1370 else
1371 return ERROR_COMMAND_SYNTAX_ERROR;
1372 } else
1373 return ERROR_COMMAND_SYNTAX_ERROR;
1374 CMD_ARGC--;
1375 CMD_ARGV++;
1376 }
1377
1378 if (stm32x_erase_options(bank) != ERROR_OK) {
1379 command_print(CMD_CTX, "stm32x failed to erase options");
1380 return ERROR_OK;
1381 }
1382
1383 stm32x_info->option_bytes.user = optionbyte;
1384
1385 if (stm32x_write_options(bank) != ERROR_OK) {
1386 command_print(CMD_CTX, "stm32x failed to write options");
1387 return ERROR_OK;
1388 }
1389
1390 command_print(CMD_CTX, "stm32x write options complete.\n"
1391 "INFO: %spower cycle is required "
1392 "for the new settings to take effect.",
1393 stm32x_info->can_load_options
1394 ? "'stm32f1x options_load' command or " : "");
1395
1396 return ERROR_OK;
1397 }
1398
1399 COMMAND_HANDLER(stm32x_handle_options_load_command)
1400 {
1401 if (CMD_ARGC < 1)
1402 return ERROR_COMMAND_SYNTAX_ERROR;
1403
1404 struct flash_bank *bank;
1405 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1406 if (ERROR_OK != retval)
1407 return retval;
1408
1409 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1410
1411 if (!stm32x_info->can_load_options) {
1412 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1413 "required instead.");
1414 return ERROR_FAIL;
1415 }
1416
1417 struct target *target = bank->target;
1418
1419 if (target->state != TARGET_HALTED) {
1420 LOG_ERROR("Target not halted");
1421 return ERROR_TARGET_NOT_HALTED;
1422 }
1423
1424 retval = stm32x_check_operation_supported(bank);
1425 if (ERROR_OK != retval)
1426 return retval;
1427
1428 /* unlock option flash registers */
1429 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1430 if (retval != ERROR_OK)
1431 return retval;
1432 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1433 if (retval != ERROR_OK)
1434 return retval;
1435
1436 /* force re-load of option bytes - generates software reset */
1437 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1438 if (retval != ERROR_OK)
1439 return retval;
1440
1441 return ERROR_OK;
1442 }
1443
1444 static int stm32x_mass_erase(struct flash_bank *bank)
1445 {
1446 struct target *target = bank->target;
1447
1448 if (target->state != TARGET_HALTED) {
1449 LOG_ERROR("Target not halted");
1450 return ERROR_TARGET_NOT_HALTED;
1451 }
1452
1453 /* unlock option flash registers */
1454 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1455 if (retval != ERROR_OK)
1456 return retval;
1457 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1458 if (retval != ERROR_OK)
1459 return retval;
1460
1461 /* mass erase flash memory */
1462 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1463 if (retval != ERROR_OK)
1464 return retval;
1465 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1466 FLASH_MER | FLASH_STRT);
1467 if (retval != ERROR_OK)
1468 return retval;
1469
1470 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1471 if (retval != ERROR_OK)
1472 return retval;
1473
1474 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1475 if (retval != ERROR_OK)
1476 return retval;
1477
1478 return ERROR_OK;
1479 }
1480
1481 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1482 {
1483 int i;
1484
1485 if (CMD_ARGC < 1)
1486 return ERROR_COMMAND_SYNTAX_ERROR;
1487
1488 struct flash_bank *bank;
1489 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1490 if (ERROR_OK != retval)
1491 return retval;
1492
1493 retval = stm32x_mass_erase(bank);
1494 if (retval == ERROR_OK) {
1495 /* set all sectors as erased */
1496 for (i = 0; i < bank->num_sectors; i++)
1497 bank->sectors[i].is_erased = 1;
1498
1499 command_print(CMD_CTX, "stm32x mass erase complete");
1500 } else
1501 command_print(CMD_CTX, "stm32x mass erase failed");
1502
1503 return retval;
1504 }
1505
1506 static const struct command_registration stm32x_exec_command_handlers[] = {
1507 {
1508 .name = "lock",
1509 .handler = stm32x_handle_lock_command,
1510 .mode = COMMAND_EXEC,
1511 .usage = "bank_id",
1512 .help = "Lock entire flash device.",
1513 },
1514 {
1515 .name = "unlock",
1516 .handler = stm32x_handle_unlock_command,
1517 .mode = COMMAND_EXEC,
1518 .usage = "bank_id",
1519 .help = "Unlock entire protected flash device.",
1520 },
1521 {
1522 .name = "mass_erase",
1523 .handler = stm32x_handle_mass_erase_command,
1524 .mode = COMMAND_EXEC,
1525 .usage = "bank_id",
1526 .help = "Erase entire flash device.",
1527 },
1528 {
1529 .name = "options_read",
1530 .handler = stm32x_handle_options_read_command,
1531 .mode = COMMAND_EXEC,
1532 .usage = "bank_id",
1533 .help = "Read and display device option bytes.",
1534 },
1535 {
1536 .name = "options_write",
1537 .handler = stm32x_handle_options_write_command,
1538 .mode = COMMAND_EXEC,
1539 .usage = "bank_id ('SWWDG'|'HWWDG') "
1540 "('RSTSTNDBY'|'NORSTSTNDBY') "
1541 "('RSTSTOP'|'NORSTSTOP')",
1542 .help = "Replace bits in device option bytes.",
1543 },
1544 {
1545 .name = "options_load",
1546 .handler = stm32x_handle_options_load_command,
1547 .mode = COMMAND_EXEC,
1548 .usage = "bank_id",
1549 .help = "Force re-load of device option bytes.",
1550 },
1551 COMMAND_REGISTRATION_DONE
1552 };
1553
1554 static const struct command_registration stm32x_command_handlers[] = {
1555 {
1556 .name = "stm32f1x",
1557 .mode = COMMAND_ANY,
1558 .help = "stm32f1x flash command group",
1559 .usage = "",
1560 .chain = stm32x_exec_command_handlers,
1561 },
1562 COMMAND_REGISTRATION_DONE
1563 };
1564
1565 struct flash_driver stm32f1x_flash = {
1566 .name = "stm32f1x",
1567 .commands = stm32x_command_handlers,
1568 .flash_bank_command = stm32x_flash_bank_command,
1569 .erase = stm32x_erase,
1570 .protect = stm32x_protect,
1571 .write = stm32x_write,
1572 .read = default_flash_read,
1573 .probe = stm32x_probe,
1574 .auto_probe = stm32x_auto_probe,
1575 .erase_check = default_flash_blank_check,
1576 .protect_check = stm32x_protect_check,
1577 .info = get_stm32x_info,
1578 .free_driver_priv = default_flash_free_driver_priv,
1579 };
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