src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <jtag/interface.h>
  25 #include "bitbang.h"
  26
  27 #define TDO_BIT         1
  28 #define TDI_BIT         2
  29 #define TCK_BIT         4
  30 #define TMS_BIT         8
  31 #define TRST_BIT        16
  32 #define SRST_BIT        32
  33 #define VCC_BIT         64
  34
  35 #include <sys/mman.h>
  36
  37 static uint8_t output_value = 0x0;
  38 static int dev_mem_fd;
  39 static void *gpio_controller;
  40 static volatile uint8_t *gpio_data_register;
  41 static volatile uint8_t *gpio_data_direction_register;
  42
  43 /* low level command set
  44  */
  45 static int ep93xx_read(void);
  46 static void ep93xx_write(int tck, int tms, int tdi);
  47 static void ep93xx_reset(int trst, int srst);
  48
  49 static int ep93xx_speed(int speed);
  50 static int ep93xx_register_commands(struct command_context *cmd_ctx);
  51 static int ep93xx_init(void);
  52 static int ep93xx_quit(void);
  53
  54 struct timespec ep93xx_zzzz;
  55
  56 struct jtag_interface ep93xx_interface =
  57 {
  58         .name = "ep93xx",
  59
  60         .supported = DEBUG_CAP_TMS_SEQ,
  61         .execute_queue = bitbang_execute_queue,
  62
  63         .speed = ep93xx_speed,
  64         .register_commands = ep93xx_register_commands,
  65         .init = ep93xx_init,
  66         .quit = ep93xx_quit,
  67 };
  68
  69 static struct bitbang_interface ep93xx_bitbang =
  70 {
  71         .read = ep93xx_read,
  72         .write = ep93xx_write,
  73         .reset = ep93xx_reset,
  74         .blink = 0,
  75 };
  76
  77 static int ep93xx_read(void)
  78 {
  79         return !!(*gpio_data_register & TDO_BIT);
  80 }
  81
  82 static void ep93xx_write(int tck, int tms, int tdi)
  83 {
  84         if (tck)
  85                 output_value |= TCK_BIT;
  86         else
  87                 output_value &= ~TCK_BIT;
  88
  89         if (tms)
  90                 output_value |= TMS_BIT;
  91         else
  92                 output_value &= ~TMS_BIT;
  93
  94         if (tdi)
  95                 output_value |= TDI_BIT;
  96         else
  97                 output_value &= ~TDI_BIT;
  98
  99         *gpio_data_register = output_value;
 100         nanosleep(&ep93xx_zzzz, NULL);
 101 }
 102
 103 /* (1) assert or (0) deassert reset lines */
 104 static void ep93xx_reset(int trst, int srst)
 105 {
 106         if (trst == 0)
 107                 output_value |= TRST_BIT;
 108         else if (trst == 1)
 109                 output_value &= ~TRST_BIT;
 110
 111         if (srst == 0)
 112                 output_value |= SRST_BIT;
 113         else if (srst == 1)
 114                 output_value &= ~SRST_BIT;
 115
 116         *gpio_data_register = output_value;
 117         nanosleep(&ep93xx_zzzz, NULL);
 118 }
 119
 120 static int ep93xx_speed(int speed)
 121 {
 122
 123         return ERROR_OK;
 124 }
 125
 126 static int ep93xx_register_commands(struct command_context *cmd_ctx)
 127 {
 128
 129         return ERROR_OK;
 130 }
 131
 132 static int set_gonk_mode(void)
 133 {
 134         void *syscon;
 135         uint32_t devicecfg;
 136
 137         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 138                         MAP_SHARED, dev_mem_fd, 0x80930000);
 139         if (syscon == MAP_FAILED) {
 140                 perror("mmap");
 141                 return ERROR_JTAG_INIT_FAILED;
 142         }
 143
 144         devicecfg = *((volatile int *)(syscon + 0x80));
 145         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 146         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 147
 148         munmap(syscon, 4096);
 149
 150         return ERROR_OK;
 151 }
 152
 153 static int ep93xx_init(void)
 154 {
 155         int ret;
 156
 157         bitbang_interface = &ep93xx_bitbang;
 158
 159         ep93xx_zzzz.tv_sec = 0;
 160         ep93xx_zzzz.tv_nsec = 10000000;
 161
 162         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 163         if (dev_mem_fd < 0) {
 164                 perror("open");
 165                 return ERROR_JTAG_INIT_FAILED;
 166         }
 167
 168         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 169                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 170         if (gpio_controller == MAP_FAILED) {
 171                 perror("mmap");
 172                 close(dev_mem_fd);
 173                 return ERROR_JTAG_INIT_FAILED;
 174         }
 175
 176         ret = set_gonk_mode();
 177         if (ret != ERROR_OK) {
 178                 munmap(gpio_controller, 4096);
 179                 close(dev_mem_fd);
 180                 return ret;
 181         }
 182
 183 #if 0
 184         /* Use GPIO port A.  */
 185         gpio_data_register = gpio_controller + 0x00;
 186         gpio_data_direction_register = gpio_controller + 0x10;
 187
 188
 189         /* Use GPIO port B.  */
 190         gpio_data_register = gpio_controller + 0x04;
 191         gpio_data_direction_register = gpio_controller + 0x14;
 192
 193         /* Use GPIO port C.  */
 194         gpio_data_register = gpio_controller + 0x08;
 195         gpio_data_direction_register = gpio_controller + 0x18;
 196
 197         /* Use GPIO port D.  */
 198         gpio_data_register = gpio_controller + 0x0c;
 199         gpio_data_direction_register = gpio_controller + 0x1c;
 200 #endif
 201
 202         /* Use GPIO port C.  */
 203         gpio_data_register = gpio_controller + 0x08;
 204         gpio_data_direction_register = gpio_controller + 0x18;
 205
 206         LOG_INFO("gpio_data_register      = %p\n", gpio_data_register);
 207         LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
 208         /*
 209          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 210          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 211          * TMS/TRST/SRST high.
 212          */
 213         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 214         *gpio_data_register = output_value;
 215         nanosleep(&ep93xx_zzzz, NULL);
 216
 217         /*
 218          * Configure the direction register.  1 = output, 0 = input.
 219          */
 220         *gpio_data_direction_register =
 221                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 222
 223         nanosleep(&ep93xx_zzzz, NULL);
 224         return ERROR_OK;
 225 }
 226
 227 static int ep93xx_quit(void)
 228 {
 229
 230         return ERROR_OK;
 231 }