1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
11 * Copyright (C) 2009-2010 by David Brownell
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 ***************************************************************************/
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
44 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
45 #define JTAG_DP_ABORT 0x8
46 #define JTAG_DP_DPACC 0xA
47 #define JTAG_DP_APACC 0xB
48 #define JTAG_DP_IDCODE 0xE
50 /* three-bit ACK values for DPACC and APACC reads */
51 #define JTAG_ACK_OK_FAULT 0x2
52 #define JTAG_ACK_WAIT 0x1
54 /***************************************************************************
56 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
58 ***************************************************************************/
61 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
62 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
63 * discusses operations which access these registers.
65 * Note that only one scan is performed. If RnW is set, a separate scan
66 * will be needed to collect the data which was read; the "invalue" collects
67 * the posted result of a preceding operation, not the current one.
70 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
71 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
72 * SELECT register has more addressing bits.
73 * @param RnW false iff outvalue will be written to the DP or AP
74 * @param outvalue points to a 32-bit (little-endian) integer
75 * @param invalue NULL, or points to a 32-bit (little-endian) integer
76 * @param ack points to where the three bit JTAG_ACK_* code will be stored
79 /* FIXME don't export ... this is a temporary workaround for the
80 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
82 int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
83 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
84 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
86 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
87 struct scan_field fields
[2];
90 arm_jtag_set_instr(jtag_info
, instr
, NULL
, TAP_IDLE
);
92 /* Scan out a read or write operation using some DP or AP register.
93 * For APACC access with any sticky error flag set, this is discarded.
95 fields
[0].num_bits
= 3;
96 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
97 fields
[0].out_value
= &out_addr_buf
;
98 fields
[0].in_value
= ack
;
100 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
101 * complete; data we write is discarded, data we read is unpredictable.
102 * When overrun detect is active, STICKYORUN is set.
105 fields
[1].num_bits
= 32;
106 fields
[1].out_value
= outvalue
;
107 fields
[1].in_value
= invalue
;
109 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_IDLE
);
111 /* Add specified number of tck clocks after starting memory bus
112 * access, giving the hardware time to complete the access.
113 * They provide more time for the (MEM) AP to complete the read ...
114 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
116 if ((instr
== JTAG_DP_APACC
)
117 && ((reg_addr
== AP_REG_DRW
)
118 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
119 && (dap
->memaccess_tck
!= 0))
120 jtag_add_runtest(dap
->memaccess_tck
,
123 return jtag_get_error();
127 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
128 * This is exactly like adi_jtag_dp_scan(), except that endianness
129 * conversions are performed (so the types of invalue and outvalue
130 * must be different).
132 static int adi_jtag_dp_scan_u32(struct adiv5_dap
*dap
,
133 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
134 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
136 uint8_t out_value_buf
[4];
139 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
141 retval
= adi_jtag_dp_scan(dap
, instr
, reg_addr
, RnW
,
142 out_value_buf
, (uint8_t *)invalue
, ack
);
143 if (retval
!= ERROR_OK
)
147 jtag_add_callback(arm_le_to_h_u32
,
148 (jtag_callback_data_t
) invalue
);
154 * Utility to write AP registers.
156 static inline int adi_jtag_ap_write_check(struct adiv5_dap
*dap
,
157 uint8_t reg_addr
, uint8_t *outvalue
)
159 return adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg_addr
, DPAP_WRITE
,
160 outvalue
, NULL
, NULL
);
163 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap
*dap
,
164 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
165 uint32_t outvalue
, uint32_t *invalue
)
169 /* Issue the read or write */
170 retval
= adi_jtag_dp_scan_u32(dap
, instr
, reg_addr
,
171 RnW
, outvalue
, NULL
, NULL
);
172 if (retval
!= ERROR_OK
)
175 /* For reads, collect posted value; RDBUFF has no other effect.
176 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
178 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
179 retval
= adi_jtag_dp_scan_u32(dap
, JTAG_DP_DPACC
,
180 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &dap
->ack
);
184 static int jtagdp_transaction_endcheck(struct adiv5_dap
*dap
)
189 /* too expensive to call keep_alive() here */
192 /* Danger!!!! BROKEN!!!! */
193 adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
194 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
195 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
196 R956 introduced the check on return value here and now Michael Schwingen reports
197 that this code no longer works....
199 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
201 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
203 LOG_ERROR("BUG: Why does this fail the first time????");
205 /* Why??? second time it works??? */
208 /* Post CTRL/STAT read; discard any previous posted read value
209 * but collect its ACK status.
211 adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
212 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
213 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
216 dap
->ack
= dap
->ack
& 0x7;
218 /* common code path avoids calling timeval_ms() */
219 if (dap
->ack
!= JTAG_ACK_OK_FAULT
)
221 long long then
= timeval_ms();
223 while (dap
->ack
!= JTAG_ACK_OK_FAULT
)
225 if (dap
->ack
== JTAG_ACK_WAIT
)
227 if ((timeval_ms()-then
) > 1000)
229 /* NOTE: this would be a good spot
230 * to use JTAG_DP_ABORT.
232 LOG_WARNING("Timeout (1000ms) waiting "
234 "in JTAG-DP transaction");
235 return ERROR_JTAG_DEVICE_ERROR
;
240 LOG_WARNING("Invalid ACK %#x "
241 "in JTAG-DP transaction",
243 return ERROR_JTAG_DEVICE_ERROR
;
246 adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
247 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
248 if ((retval
= dap_run(dap
)) != ERROR_OK
)
250 dap
->ack
= dap
->ack
& 0x7;
254 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
256 /* Check for STICKYERR and STICKYORUN */
257 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
259 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
260 /* Check power to debug regions */
261 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
262 ahbap_debugport_init(dap
);
265 uint32_t mem_ap_csw
, mem_ap_tar
;
267 /* Maybe print information about last intended
268 * MEM-AP access; but not if autoincrementing.
269 * *Real* CSW and TAR values are always shown.
271 if (dap
->ap_tar_value
!= (uint32_t) -1)
272 LOG_DEBUG("MEM-AP Cached values: "
274 ", ap_csw 0x%" PRIx32
275 ", ap_tar 0x%" PRIx32
,
280 if (ctrlstat
& SSTICKYORUN
)
281 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
282 "memaccess, or reduce jtag speed");
284 if (ctrlstat
& SSTICKYERR
)
285 LOG_ERROR("JTAG-DP STICKY ERROR");
287 /* Clear Sticky Error Bits */
288 adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
289 DP_CTRL_STAT
, DPAP_WRITE
,
290 dap
->dp_ctrl_stat
| SSTICKYORUN
292 adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
293 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
294 if ((retval
= dap_run(dap
)) != ERROR_OK
)
297 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
299 retval
= dap_queue_ap_read(dap
,
300 AP_REG_CSW
, &mem_ap_csw
);
301 if (retval
!= ERROR_OK
)
304 retval
= dap_queue_ap_read(dap
,
305 AP_REG_TAR
, &mem_ap_tar
);
306 if (retval
!= ERROR_OK
)
309 if ((retval
= dap_run(dap
)) != ERROR_OK
)
311 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
312 PRIx32
, mem_ap_csw
, mem_ap_tar
);
315 if ((retval
= dap_run(dap
)) != ERROR_OK
)
317 return ERROR_JTAG_DEVICE_ERROR
;
323 /*--------------------------------------------------------------------------*/
325 static int jtag_idcode_q_read(struct adiv5_dap
*dap
,
326 uint8_t *ack
, uint32_t *data
)
328 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
330 struct scan_field fields
[1];
332 /* This is a standard JTAG operation -- no DAP tweakage */
333 retval
= arm_jtag_set_instr(jtag_info
, JTAG_DP_IDCODE
, NULL
, TAP_IDLE
);
334 if (retval
!= ERROR_OK
)
337 fields
[0].num_bits
= 32;
338 fields
[0].out_value
= NULL
;
339 fields
[0].in_value
= (void *) data
;
341 jtag_add_dr_scan(jtag_info
->tap
, 1, fields
, TAP_IDLE
);
342 retval
= jtag_get_error();
343 if (retval
!= ERROR_OK
)
346 jtag_add_callback(arm_le_to_h_u32
,
347 (jtag_callback_data_t
) data
);
352 static int jtag_dp_q_read(struct adiv5_dap
*dap
, unsigned reg
,
355 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
356 reg
, DPAP_READ
, 0, data
);
359 static int jtag_dp_q_write(struct adiv5_dap
*dap
, unsigned reg
,
362 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
363 reg
, DPAP_WRITE
, data
, NULL
);
366 /** Select the AP register bank matching bits 7:4 of reg. */
367 static int jtag_ap_q_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
369 uint32_t select_ap_bank
= reg
& 0x000000F0;
371 if (select_ap_bank
== dap
->ap_bank_value
)
373 dap
->ap_bank_value
= select_ap_bank
;
375 select_ap_bank
|= dap
->apsel
;
377 return jtag_dp_q_write(dap
, DP_SELECT
, select_ap_bank
);
380 static int jtag_ap_q_read(struct adiv5_dap
*dap
, unsigned reg
,
383 int retval
= jtag_ap_q_bankselect(dap
, reg
);
385 if (retval
!= ERROR_OK
)
388 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_APACC
, reg
,
392 static int jtag_ap_q_write(struct adiv5_dap
*dap
, unsigned reg
,
395 uint8_t out_value_buf
[4];
397 int retval
= jtag_ap_q_bankselect(dap
, reg
);
398 if (retval
!= ERROR_OK
)
401 buf_set_u32(out_value_buf
, 0, 32, data
);
403 return adi_jtag_ap_write_check(dap
, reg
, out_value_buf
);
406 static int jtag_ap_q_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
408 /* for JTAG, this is the only valid ABORT register operation */
409 return adi_jtag_dp_scan_u32(dap
, JTAG_DP_ABORT
,
410 0, DPAP_WRITE
, 1, NULL
, ack
);
413 static int jtag_dp_run(struct adiv5_dap
*dap
)
415 return jtagdp_transaction_endcheck(dap
);
418 /* FIXME don't export ... just initialize as
421 const struct dap_ops jtag_dp_ops
= {
422 .queue_idcode_read
= jtag_idcode_q_read
,
423 .queue_dp_read
= jtag_dp_q_read
,
424 .queue_dp_write
= jtag_dp_q_write
,
425 .queue_ap_read
= jtag_ap_q_read
,
426 .queue_ap_write
= jtag_ap_q_write
,
427 .queue_ap_abort
= jtag_ap_q_abort
,
432 static const uint8_t swd2jtag_bitseq
[] = {
433 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
434 * putting both JTAG and SWD logic into reset state.
436 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
437 /* Switching equence disables SWD and enables JTAG
438 * NOTE: bits in the DP's IDCODE can expose the need for
439 * the old/deprecated sequence (0xae 0xde).
442 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
443 * putting both JTAG and SWD logic into reset state.
444 * NOTE: some docs say "at least 5".
446 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
449 /** Put the debug link into JTAG mode, if the target supports it.
450 * The link's initial mode may be either SWD or JTAG.
452 * @param target Enters JTAG mode (if possible).
454 * Note that targets implemented with SW-DP do not support JTAG, and
455 * that some targets which could otherwise support it may have been
456 * configured to disable JTAG signaling
458 * @return ERROR_OK or else a fault code.
460 int dap_to_jtag(struct target
*target
)
464 LOG_DEBUG("Enter JTAG mode");
466 /* REVISIT it's nasty to need to make calls to a "jtag"
467 * subsystem if the link isn't in JTAG mode...
470 retval
= jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq
),
471 swd2jtag_bitseq
, TAP_RESET
);
472 if (retval
== ERROR_OK
)
473 retval
= jtag_execute_queue();
475 /* REVISIT set up the DAP's ops vector for JTAG mode. */