1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Texas Instruments DaVinci family: TMS320DM365
6 if { [info exists CHIPNAME] } {
7 set _CHIPNAME $CHIPNAME
12 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
13 # after JTAG reset until ICEpick is used to route them in.
16 # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
17 # needing any ICEpick interaction.
20 source [find target/icepick.cfg]
22 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
23 if { [info exists ETB_TAPID] } {
24 set _ETB_TAPID $ETB_TAPID
26 set _ETB_TAPID 0x2b900f0f
28 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
29 jtag configure $_CHIPNAME.etb -event tap-enable \
30 "icepick_c_tapenable $_CHIPNAME.jrc 1"
32 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
33 if { [info exists CPU_TAPID] } {
34 set _CPU_TAPID $CPU_TAPID
36 set _CPU_TAPID 0x0792602f
38 jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
39 jtag configure $_CHIPNAME.arm -event tap-enable \
40 "icepick_c_tapenable $_CHIPNAME.jrc 0"
42 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
43 if { [info exists JRC_TAPID] } {
44 set _JRC_TAPID $JRC_TAPID
46 set _JRC_TAPID 0x0b83e02f
48 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
50 jtag configure $_CHIPNAME.jrc -event setup \
51 "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
55 # various symbol definitions, to avoid hard-wiring addresses
56 # and enable some sharing of DaVinci-family utility code
58 set dm365 [ dict create ]
60 # Physical addresses for controllers and memory
61 # (Some of these are valid for many DaVinci family chips)
62 dict set dm365 sram0 0x00010000
63 dict set dm365 sram1 0x00014000
64 dict set dm365 sysbase 0x01c40000
65 dict set dm365 pllc1 0x01c40800
66 dict set dm365 pllc2 0x01c40c00
67 dict set dm365 psc 0x01c41000
68 dict set dm365 gpio 0x01c67000
69 dict set dm365 a_emif 0x01d10000
70 dict set dm365 a_emif_cs0 0x02000000
71 dict set dm365 a_emif_cs1 0x04000000
72 dict set dm365 ddr_emif 0x20000000
73 dict set dm365 ddr 0x80000000
75 source [find target/davinci.cfg]
78 # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
79 # and the ETB memory (4K) are other options, while trace is unused.
80 set _TARGETNAME $_CHIPNAME.arm
82 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
84 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
85 # and that the work area is used only with a kernel mmu context ...
86 $_TARGETNAME configure \
87 -work-area-virt [expr {0xfffe0000 + 0x4000}] \
88 -work-area-phys [dict get $dm365 sram1] \
89 -work-area-size 0x4000 \
92 # be absolutely certain the JTAG clock will work with the worst-case
93 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
94 # on the PLL and starts using it. OK to speed up after clock setup.
96 $_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
98 arm7_9 fast_memory_access enable
99 arm7_9 dcc_downloads enable
102 etm config $_TARGETNAME 16 normal full etb
103 etb config $_TARGETNAME $_CHIPNAME.etb