1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Texas Instruments CC26x0 - ARM Cortex-M3
9 source [find target/icepick.cfg]
10 source [find target/ti-cjtag.cfg]
12 if { [info exists CHIPNAME] } {
13 set _CHIPNAME $CHIPNAME
21 if { [info exists DAP_TAPID] } {
22 set _DAP_TAPID $DAP_TAPID
24 set _DAP_TAPID 0x4BA00477
26 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
27 jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
30 # ICEpick-C (JTAG route controller)
32 if { [info exists JRC_TAPID] } {
33 set _JRC_TAPID $JRC_TAPID
35 set _JRC_TAPID 0x0B99A02F
37 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
38 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
39 # A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG
40 jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
42 set _TARGETNAME $_CHIPNAME.cpu
43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
44 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
46 if { [info exists WORKAREASIZE] } {
47 set _WORKAREASIZE $WORKAREASIZE
49 set _WORKAREASIZE 0x4000
52 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
54 set _FLASHNAME $_CHIPNAME.flash
55 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
57 cortex_m reset_config vectreset