1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
4 # The chips are very similar; the SAMV series just has
5 # more peripherals and seems like the "flagship" of the
6 # family. This script will work for all of them.
8 source [find target/swj-dp.tcl]
10 if { [info exists CHIPNAME] } {
11 set _CHIPNAME $CHIPNAME
16 if { [info exists ENDIAN] } {
22 # Work-area is a space in RAM used for flash programming
24 if { [info exists WORKAREASIZE] } {
25 set _WORKAREASIZE $WORKAREASIZE
27 set _WORKAREASIZE 0x4000
30 if { [info exists CPUTAPID] } {
31 set _CPUTAPID $CPUTAPID
33 set _CPUTAPID 0x0bd11477
36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
39 set _TARGETNAME $_CHIPNAME.cpu
40 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
42 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
47 # if srst is not fitted use SYSRESETREQ to
48 # perform a soft reset
49 cortex_m reset_config sysresetreq
51 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
52 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
53 # makes the data access cacheable. This allows reading and writing data in the
54 # CPU cache from the debugger, which is far more useful than going straight to
55 # RAM when operating on typical variables, and is generally no worse when
56 # operating on special memory locations.
57 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
60 set _FLASHNAME $_CHIPNAME.flash
61 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME