1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_NDS32_EDM_H
20 #define OPENOCD_TARGET_NDS32_EDM_H
24 * This is the interface to the Embedded Debug Module for Andes cores.
27 /* EDM misc registers */
28 enum nds_edm_misc_reg
{
29 NDS_EDM_MISC_DIMIR
= 0x0,
31 NDS_EDM_MISC_EDM_CMDR
,
34 NDS_EDM_MISC_EDM_PROBE
,
35 NDS_EDM_MISC_GEN_PORT0
,
36 NDS_EDM_MISC_GEN_PORT1
,
39 /* EDM system registers */
40 enum nds_edm_system_reg
{
41 NDS_EDM_SR_BPC0
= 0x00,
49 NDS_EDM_SR_BPA0
= 0x08,
57 NDS_EDM_SR_BPAM0
= 0x10,
65 NDS_EDM_SR_BPV0
= 0x18,
73 NDS_EDM_SR_BPCID0
= 0x20,
81 NDS_EDM_SR_EDM_CFG
= 0x28,
82 NDS_EDM_SR_EDMSW
= 0x30,
83 NDS_EDM_SR_EDM_CTL
= 0x38,
84 NDS_EDM_SR_EDM_DTR
= 0x40,
85 NDS_EDM_SR_BPMTV
= 0x48,
86 NDS_EDM_SR_DIMBR
= 0x50,
87 NDS_EDM_SR_TECR0
= 0x70,
88 NDS_EDM_SR_TECR1
= 0x71,
91 enum nds_memory_access
{
92 NDS_MEMORY_ACC_BUS
= 0,
96 enum nds_memory_select
{
97 NDS_MEMORY_SELECT_AUTO
= 0,
98 NDS_MEMORY_SELECT_MEM
= 1,
99 NDS_MEMORY_SELECT_ILM
= 2,
100 NDS_MEMORY_SELECT_DLM
= 3,
103 #define NDS_DBGER_DEX (0x1)
104 #define NDS_DBGER_DPED (0x2)
105 #define NDS_DBGER_CRST (0x4)
106 #define NDS_DBGER_AT_MAX (0x8)
107 #define NDS_DBGER_ILL_SEC_ACC (0x10)
108 #define NDS_DBGER_ALL_SUPRS_EX (0x40000000)
109 #define NDS_DBGER_RESACC (0x80000000)
110 #define NDS_DBGER_CLEAR_ALL (0x1F)
112 #define NDS_EDMSW_WDV (1 << 0)
113 #define NDS_EDMSW_RDV (1 << 1)
115 #endif /* OPENOCD_TARGET_NDS32_EDM_H */