1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
28 ***************************************************************************/
35 #define CORTEX_A_COMMON_MAGIC 0x411fc082
36 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
38 #define CORTEX_A5_PARTNUM 0xc05
39 #define CORTEX_A7_PARTNUM 0xc07
40 #define CORTEX_A8_PARTNUM 0xc08
41 #define CORTEX_A9_PARTNUM 0xc09
42 #define CORTEX_A15_PARTNUM 0xc0f
43 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
44 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
46 #define CPUDBG_CPUID 0xD00
47 #define CPUDBG_CTYPR 0xD04
48 #define CPUDBG_TTYPR 0xD0C
49 #define CPUDBG_LOCKACCESS 0xFB0
50 #define CPUDBG_LOCKSTATUS 0xFB4
51 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
56 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
58 enum cortex_a_isrmasking_mode
{
71 struct cortex_a_common
{
73 struct arm_jtag jtag_info
;
75 /* Context information */
78 /* Saved cp15 registers */
79 uint32_t cp15_control_reg
;
80 /* latest cp15 register value written and cpsr processor mode */
81 uint32_t cp15_control_reg_curr
;
82 enum arm_mode curr_mode
;
85 /* Breakpoint register pairs */
88 int brp_num_available
;
89 struct cortex_a_brp
*brp_list
;
91 /* Use cortex_a_read_regs_through_mem for fast register reads */
99 enum cortex_a_isrmasking_mode isrmasking_mode
;
101 struct armv7a_common armv7a_common
;
105 static inline struct cortex_a_common
*
106 target_to_cortex_a(struct target
*target
)
108 return container_of(target
->arch_info
, struct cortex_a_common
, armv7a_common
.arm
);
111 #endif /* CORTEX_A_H */