1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
40 int cfi_register_commands(struct command_context_s
*cmd_ctx
);
41 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
42 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
43 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
44 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
45 int cfi_probe(struct flash_bank_s
*bank
);
46 int cfi_auto_probe(struct flash_bank_s
*bank
);
47 int cfi_erase_check(struct flash_bank_s
*bank
);
48 int cfi_protect_check(struct flash_bank_s
*bank
);
49 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
51 int cfi_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 #define CFI_MAX_BUS_WIDTH 4
54 #define CFI_MAX_CHIP_WIDTH 4
56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
57 #define CFI_MAX_INTEL_CODESIZE 256
59 flash_driver_t cfi_flash
=
62 .register_commands
= cfi_register_commands
,
63 .flash_bank_command
= cfi_flash_bank_command
,
65 .protect
= cfi_protect
,
68 .auto_probe
= cfi_auto_probe
,
69 .erase_check
= cfi_erase_check
,
70 .protect_check
= cfi_protect_check
,
74 cfi_unlock_addresses_t cfi_unlock_addresses
[] =
76 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
77 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
80 /* CFI fixups foward declarations */
81 void cfi_fixup_non_cfi(flash_bank_t
*flash
, void *param
);
82 void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
83 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
84 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
86 /* fixup after identifying JEDEC manufactuer and ID */
87 cfi_fixup_t cfi_jedec_fixups
[] = {
88 {CFI_MFR_SST
, 0x00D4, cfi_fixup_non_cfi
, NULL
},
89 {CFI_MFR_SST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
90 {CFI_MFR_SST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
91 {CFI_MFR_SST
, 0x00D7, cfi_fixup_non_cfi
, NULL
},
92 {CFI_MFR_SST
, 0x2780, cfi_fixup_non_cfi
, NULL
},
93 {CFI_MFR_ST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
94 {CFI_MFR_ST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
95 {CFI_MFR_AMD
, 0x2223, cfi_fixup_non_cfi
, NULL
},
96 {CFI_MFR_AMD
, 0x22ab, cfi_fixup_non_cfi
, NULL
},
100 /* fixup after reading cmdset 0002 primary query table */
101 cfi_fixup_t cfi_0002_fixups
[] = {
102 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
103 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
104 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
105 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
106 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
107 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
108 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
112 /* fixup after reading cmdset 0001 primary query table */
113 cfi_fixup_t cfi_0001_fixups
[] = {
117 void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
119 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
122 for (f
= fixups
; f
->fixup
; f
++)
124 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
125 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
127 f
->fixup(bank
, f
->param
);
132 inline u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
134 /* while the sector list isn't built, only accesses to sector 0 work */
136 return bank
->base
+ offset
* bank
->bus_width
;
141 ERROR("BUG: sector list not yet built");
144 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
149 void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
153 /* clear whole buffer, to ensure bits that exceed the bus_width
156 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
159 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
161 for (i
= bank
->bus_width
; i
> 0; i
--)
163 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
168 for (i
= 1; i
<= bank
->bus_width
; i
++)
170 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
175 /* read unsigned 8-bit value from the bank
176 * flash banks are expected to be made of similar chips
177 * the query result should be the same for all
179 u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
181 target_t
*target
= bank
->target
;
182 u8 data
[CFI_MAX_BUS_WIDTH
];
184 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
186 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
189 return data
[bank
->bus_width
- 1];
192 /* read unsigned 8-bit value from the bank
193 * in case of a bank made of multiple chips,
194 * the individual values are ORed
196 u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
198 target_t
*target
= bank
->target
;
199 u8 data
[CFI_MAX_BUS_WIDTH
];
202 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
204 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
206 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
214 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
215 value
|= data
[bank
->bus_width
- 1 - i
];
221 u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
223 target_t
*target
= bank
->target
;
224 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
226 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
228 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
229 return data
[0] | data
[bank
->bus_width
] << 8;
231 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
234 u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
236 target_t
*target
= bank
->target
;
237 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
239 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
241 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
242 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
244 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
245 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
248 void cfi_intel_clear_status_register(flash_bank_t
*bank
)
250 target_t
*target
= bank
->target
;
253 if (target
->state
!= TARGET_HALTED
)
255 ERROR("BUG: attempted to clear status register while target wasn't halted");
259 cfi_command(bank
, 0x50, command
);
260 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
263 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
267 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
269 DEBUG("status: 0x%x", status
);
273 /* mask out bit 0 (reserved) */
274 status
= status
& 0xfe;
276 DEBUG("status: 0x%x", status
);
278 if ((status
& 0x80) != 0x80)
280 ERROR("timeout while waiting for WSM to become ready");
282 else if (status
!= 0x80)
284 ERROR("status register: 0x%x", status
);
286 ERROR("Block Lock-Bit Detected, Operation Abort");
288 ERROR("Program suspended");
290 ERROR("Low Programming Voltage Detected, Operation Aborted");
292 ERROR("Program Error / Error in Setting Lock-Bit");
294 ERROR("Error in Block Erasure or Clear Lock-Bits");
296 ERROR("Block Erase Suspended");
298 cfi_intel_clear_status_register(bank
);
304 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
306 u8 status
, oldstatus
;
308 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
311 status
= cfi_get_u8(bank
, 0, 0x0);
312 if ((status
^ oldstatus
) & 0x40) {
314 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
315 status
= cfi_get_u8(bank
, 0, 0x0);
316 if ((status
^ oldstatus
) & 0x40) {
317 ERROR("dq5 timeout, status: 0x%x", status
);
318 return(ERROR_FLASH_OPERATION_FAILED
);
320 DEBUG("status: 0x%x", status
);
325 DEBUG("status: 0x%x", status
);
331 } while (timeout
-- > 0);
333 ERROR("timeout, status: 0x%x", status
);
335 return(ERROR_FLASH_BUSY
);
338 int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
340 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
341 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
342 target_t
*target
= bank
->target
;
345 cfi_info
->pri_ext
= pri_ext
;
347 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
348 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
349 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
351 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
353 cfi_command(bank
, 0xf0, command
);
354 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
355 cfi_command(bank
, 0xff, command
);
356 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
357 return ERROR_FLASH_BANK_INVALID
;
360 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
361 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
363 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
365 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
366 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
367 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
369 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
371 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
372 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
374 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
375 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
376 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
378 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
379 if (pri_ext
->num_protection_fields
!= 1)
381 WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
384 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
385 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
386 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
388 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
393 int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
395 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
396 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
397 target_t
*target
= bank
->target
;
400 cfi_info
->pri_ext
= pri_ext
;
402 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
403 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
404 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
406 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
408 cfi_command(bank
, 0xf0, command
);
409 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
410 return ERROR_FLASH_BANK_INVALID
;
413 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
414 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
416 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
418 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
419 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
420 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
421 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
422 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
423 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
424 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
425 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
426 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
427 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
428 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
430 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
431 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
433 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
434 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
436 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
439 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
440 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
441 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
443 DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
445 /* default values for implementation specific workarounds */
446 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
447 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
448 pri_ext
->_reversed_geometry
= 0;
453 int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
455 cfi_atmel_pri_ext_t atmel_pri_ext
;
456 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
457 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
458 target_t
*target
= bank
->target
;
461 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
462 * but a different primary extended query table.
463 * We read the atmel table, and prepare a valid AMD/Spansion query table.
466 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
468 cfi_info
->pri_ext
= pri_ext
;
470 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
471 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
472 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
474 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
476 cfi_command(bank
, 0xf0, command
);
477 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
478 return ERROR_FLASH_BANK_INVALID
;
481 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
482 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
483 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
485 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
486 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
488 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
490 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
491 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
493 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
494 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
495 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
496 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
498 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
499 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
501 if (atmel_pri_ext
.features
& 0x02)
502 pri_ext
->EraseSuspend
= 2;
504 if (atmel_pri_ext
.bottom_boot
)
505 pri_ext
->TopBottom
= 2;
507 pri_ext
->TopBottom
= 3;
509 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
510 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
515 int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
517 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
519 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
521 return cfi_read_atmel_pri_ext(bank
);
525 return cfi_read_spansion_pri_ext(bank
);
529 int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
532 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
533 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
535 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
539 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
540 pri_ext
->pri
[1], pri_ext
->pri
[2],
541 pri_ext
->major_version
, pri_ext
->minor_version
);
545 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
546 (pri_ext
->SiliconRevision
) >> 2,
547 (pri_ext
->SiliconRevision
) & 0x03);
551 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
552 pri_ext
->EraseSuspend
,
557 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
558 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
559 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
564 int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
567 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
568 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
570 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
574 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
578 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
582 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
583 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
584 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
588 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
593 int cfi_register_commands(struct command_context_s
*cmd_ctx
)
595 /*command_t *cfi_cmd = */
596 register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
598 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
599 "print part id of cfi flash bank <num>");
604 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
606 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
608 cfi_flash_bank_t
*cfi_info
;
613 WARNING("incomplete flash_bank cfi configuration");
614 return ERROR_FLASH_BANK_INVALID
;
617 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
618 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
620 ERROR("chip and bus width have to specified in bytes");
621 return ERROR_FLASH_BANK_INVALID
;
624 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
625 cfi_info
->probed
= 0;
626 bank
->driver_priv
= cfi_info
;
628 cfi_info
->write_algorithm
= NULL
;
629 cfi_info
->erase_check_algorithm
= NULL
;
631 cfi_info
->x16_as_x8
= 0;
632 cfi_info
->jedec_probe
= 0;
633 cfi_info
->not_cfi
= 0;
635 for (i
= 6; i
< argc
; i
++)
637 if (strcmp(args
[i
], "x16_as_x8") == 0)
639 cfi_info
->x16_as_x8
= 1;
641 else if (strcmp(args
[i
], "jedec_probe") == 0)
643 cfi_info
->jedec_probe
= 1;
647 cfi_info
->write_algorithm
= NULL
;
649 /* bank wasn't probed yet */
650 cfi_info
->qry
[0] = -1;
655 int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
657 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
658 target_t
*target
= bank
->target
;
662 cfi_intel_clear_status_register(bank
);
664 for (i
= first
; i
<= last
; i
++)
666 cfi_command(bank
, 0x20, command
);
667 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
669 cfi_command(bank
, 0xd0, command
);
670 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
672 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
673 bank
->sectors
[i
].is_erased
= 1;
676 cfi_command(bank
, 0xff, command
);
677 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
679 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
680 return ERROR_FLASH_OPERATION_FAILED
;
684 cfi_command(bank
, 0xff, command
);
685 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
690 int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
692 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
693 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
694 target_t
*target
= bank
->target
;
698 for (i
= first
; i
<= last
; i
++)
700 cfi_command(bank
, 0xaa, command
);
701 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
703 cfi_command(bank
, 0x55, command
);
704 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
706 cfi_command(bank
, 0x80, command
);
707 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
709 cfi_command(bank
, 0xaa, command
);
710 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
712 cfi_command(bank
, 0x55, command
);
713 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
715 cfi_command(bank
, 0x30, command
);
716 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
718 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
719 bank
->sectors
[i
].is_erased
= 1;
722 cfi_command(bank
, 0xf0, command
);
723 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
725 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
726 return ERROR_FLASH_OPERATION_FAILED
;
730 cfi_command(bank
, 0xf0, command
);
731 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
736 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
738 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
740 if (bank
->target
->state
!= TARGET_HALTED
)
742 return ERROR_TARGET_NOT_HALTED
;
745 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
747 return ERROR_FLASH_SECTOR_INVALID
;
750 if (cfi_info
->qry
[0] != 'Q')
751 return ERROR_FLASH_BANK_NOT_PROBED
;
753 switch(cfi_info
->pri_id
)
757 return cfi_intel_erase(bank
, first
, last
);
760 return cfi_spansion_erase(bank
, first
, last
);
763 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
770 int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
772 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
773 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
774 target_t
*target
= bank
->target
;
779 /* if the device supports neither legacy lock/unlock (bit 3) nor
780 * instant individual block locking (bit 5).
782 if (!(pri_ext
->feature_support
& 0x28))
783 return ERROR_FLASH_OPERATION_FAILED
;
785 cfi_intel_clear_status_register(bank
);
787 for (i
= first
; i
<= last
; i
++)
789 cfi_command(bank
, 0x60, command
);
790 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
791 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
794 cfi_command(bank
, 0x01, command
);
795 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
796 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
797 bank
->sectors
[i
].is_protected
= 1;
801 cfi_command(bank
, 0xd0, command
);
802 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
803 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
804 bank
->sectors
[i
].is_protected
= 0;
807 /* instant individual block locking doesn't require reading of the status register */
808 if (!(pri_ext
->feature_support
& 0x20))
810 /* Clear lock bits operation may take up to 1.4s */
811 cfi_intel_wait_status_busy(bank
, 1400);
816 /* read block lock bit, to verify status */
817 cfi_command(bank
, 0x90, command
);
818 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
819 block_status
= cfi_get_u8(bank
, i
, 0x2);
821 if ((block_status
& 0x1) != set
)
823 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
824 cfi_command(bank
, 0x70, command
);
825 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
826 cfi_intel_wait_status_busy(bank
, 10);
829 return ERROR_FLASH_OPERATION_FAILED
;
839 /* if the device doesn't support individual block lock bits set/clear,
840 * all blocks have been unlocked in parallel, so we set those that should be protected
842 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
844 for (i
= 0; i
< bank
->num_sectors
; i
++)
846 if (bank
->sectors
[i
].is_protected
== 1)
848 cfi_intel_clear_status_register(bank
);
850 cfi_command(bank
, 0x60, command
);
851 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
853 cfi_command(bank
, 0x01, command
);
854 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
856 cfi_intel_wait_status_busy(bank
, 100);
861 cfi_command(bank
, 0xff, command
);
862 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
867 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
869 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
871 if (bank
->target
->state
!= TARGET_HALTED
)
873 return ERROR_TARGET_NOT_HALTED
;
876 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
878 return ERROR_FLASH_SECTOR_INVALID
;
881 if (cfi_info
->qry
[0] != 'Q')
882 return ERROR_FLASH_BANK_NOT_PROBED
;
884 switch(cfi_info
->pri_id
)
888 cfi_intel_protect(bank
, set
, first
, last
);
891 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
898 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
899 static void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
901 //target_t *target = bank->target;
906 // The data to flash must not be changed in endian! We write a bytestrem in
907 // target byte order already. Only the control and status byte lane of the flash
908 // WSM is interpreted by the CPU in different ways, when read a u16 or u32
909 // word (data seems to be in the upper or lower byte lane for u16 accesses).
911 //if (target->endianness == TARGET_LITTLE_ENDIAN)
914 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
915 word
[i
] = word
[i
+ 1];
916 word
[bank
->bus_width
- 1] = byte
;
921 // for (i = bank->bus_width - 1; i > 0; i--)
922 // word[i] = word[i - 1];
927 /* Convert code image to target endian */
928 /* FIXME create general block conversion fcts in target.c?) */ static
929 void cfi_fix_code_endian(target_t
*target
, u32
*dest
, const u32
*src
, u32 count
)
932 for (i
=0; i
< count
; i
++)
934 target_buffer_set_u32(target
, (u8
*)dest
, *src
);
940 int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
942 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
943 target_t
*target
= bank
->target
;
944 reg_param_t reg_params
[7];
945 armv4_5_algorithm_t armv4_5_info
;
946 working_area_t
*source
;
947 u32 buffer_size
= 32768;
948 u8 write_command_buf
[CFI_MAX_BUS_WIDTH
];
949 u8 busy_pattern_buf
[CFI_MAX_BUS_WIDTH
];
950 u8 error_pattern_buf
[CFI_MAX_BUS_WIDTH
];
951 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
953 /* algorithm register usage:
954 * r0: source address (in RAM)
955 * r1: target address (in Flash)
957 * r3: flash write command
958 * r4: status byte (returned to host)
959 * r5: busy test pattern
960 * r6: error test pattern
963 static const u32 word_32_code
[] = {
964 0xe4904004, /* loop: ldr r4, [r0], #4 */
965 0xe5813000, /* str r3, [r1] */
966 0xe5814000, /* str r4, [r1] */
967 0xe5914000, /* busy: ldr r4, [r1] */
968 0xe0047005, /* and r7, r4, r5 */
969 0xe1570005, /* cmp r7, r5 */
970 0x1afffffb, /* bne busy */
971 0xe1140006, /* tst r4, r6 */
972 0x1a000003, /* bne done */
973 0xe2522001, /* subs r2, r2, #1 */
974 0x0a000001, /* beq done */
975 0xe2811004, /* add r1, r1 #4 */
976 0xeafffff2, /* b loop */
977 0xeafffffe /* done: b -2 */
980 static const u32 word_16_code
[] = {
981 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
982 0xe1c130b0, /* strh r3, [r1] */
983 0xe1c140b0, /* strh r4, [r1] */
984 0xe1d140b0, /* busy ldrh r4, [r1] */
985 0xe0047005, /* and r7, r4, r5 */
986 0xe1570005, /* cmp r7, r5 */
987 0x1afffffb, /* bne busy */
988 0xe1140006, /* tst r4, r6 */
989 0x1a000003, /* bne done */
990 0xe2522001, /* subs r2, r2, #1 */
991 0x0a000001, /* beq done */
992 0xe2811002, /* add r1, r1 #2 */
993 0xeafffff2, /* b loop */
994 0xeafffffe /* done: b -2 */
997 static const u32 word_8_code
[] = {
998 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
999 0xe5c13000, /* strb r3, [r1] */
1000 0xe5c14000, /* strb r4, [r1] */
1001 0xe5d14000, /* busy ldrb r4, [r1] */
1002 0xe0047005, /* and r7, r4, r5 */
1003 0xe1570005, /* cmp r7, r5 */
1004 0x1afffffb, /* bne busy */
1005 0xe1140006, /* tst r4, r6 */
1006 0x1a000003, /* bne done */
1007 0xe2522001, /* subs r2, r2, #1 */
1008 0x0a000001, /* beq done */
1009 0xe2811001, /* add r1, r1 #1 */
1010 0xeafffff2, /* b loop */
1011 0xeafffffe /* done: b -2 */
1013 u32 target_code
[CFI_MAX_INTEL_CODESIZE
];
1014 const u32
*target_code_src
;
1015 int target_code_size
;
1016 int retval
= ERROR_OK
;
1019 cfi_intel_clear_status_register(bank
);
1021 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1022 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1023 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1025 /* If we are setting up the write_algorith, we need target_code_src */
1026 /* if not we only need target_code_size. */
1028 /* However, we don't want to create multiple code paths, so we */
1029 /* do the unecessary evaluation of target_code_src, which the */
1030 /* compiler will probably nicely optimize away if not needed */
1032 /* prepare algorithm code for target endian */
1033 switch (bank
->bus_width
)
1036 target_code_src
= word_8_code
;
1037 target_code_size
= sizeof(word_8_code
);
1040 target_code_src
= word_16_code
;
1041 target_code_size
= sizeof(word_16_code
);
1044 target_code_src
= word_32_code
;
1045 target_code_size
= sizeof(word_32_code
);
1048 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1049 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1052 /* flash write code */
1053 if (!cfi_info
->write_algorithm
)
1055 if ( target_code_size
> sizeof(target_code
) )
1057 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1058 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1060 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
);
1062 /* Get memory for block write handler */
1063 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1064 if (retval
!= ERROR_OK
)
1066 WARNING("No working area available, can't do block memory writes");
1067 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1070 /* write algorithm code to working area */
1071 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, (u8
*)target_code
);
1072 if (retval
!= ERROR_OK
)
1074 ERROR("Unable to write block write code to target");
1079 /* Get a workspace buffer for the data to flash starting with 32k size.
1080 Half size until buffer would be smaller 256 Bytem then fail back */
1081 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1082 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1085 if (buffer_size
<= 256)
1087 WARNING("no large enough working area available, can't do block memory writes");
1088 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1093 /* setup algo registers */
1094 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1095 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1096 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1097 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1098 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1099 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1100 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1102 /* prepare command and status register patterns */
1103 cfi_command(bank
, 0x40, write_command_buf
);
1104 cfi_command(bank
, 0x80, busy_pattern_buf
);
1105 cfi_command(bank
, 0x7e, error_pattern_buf
);
1107 switch (bank
->bus_width
)
1110 write_command_val
= write_command_buf
[0];
1111 busy_pattern_val
= busy_pattern_buf
[0];
1112 error_pattern_val
= error_pattern_buf
[0];
1115 write_command_val
= target_buffer_get_u16(target
, write_command_buf
);
1116 busy_pattern_val
= target_buffer_get_u16(target
, busy_pattern_buf
);
1117 error_pattern_val
= target_buffer_get_u16(target
, error_pattern_buf
);
1120 write_command_val
= target_buffer_get_u32(target
, write_command_buf
);
1121 busy_pattern_val
= target_buffer_get_u32(target
, busy_pattern_buf
);
1122 error_pattern_val
= target_buffer_get_u32(target
, error_pattern_buf
);
1125 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1126 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1130 INFO("Using target buffer at 0x%08x and of size 0x%04x", source
->address
, buffer_size
);
1132 /* Programming main loop */
1135 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1138 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1140 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1141 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1142 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1144 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1145 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1146 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1148 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count
, address
);
1150 /* Execute algorithm, assume breakpoint for last instruction */
1151 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
,
1152 cfi_info
->write_algorithm
->address
,
1153 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(u32
),
1154 10000, /* 10s should be enough for max. 32k of data */
1157 /* On failure try a fall back to direct word writes */
1158 if (retval
!= ERROR_OK
)
1160 cfi_intel_clear_status_register(bank
);
1161 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1162 retval
= ERROR_FLASH_OPERATION_FAILED
;
1163 //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1164 // FIXME To allow fall back or recovery, we must save the actual status
1165 // somewhere, so that a higher level code can start recovery.
1169 /* Check return value from algo code */
1170 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1173 /* read status register (outputs debug inforation) */
1174 cfi_intel_wait_status_busy(bank
, 100);
1175 cfi_intel_clear_status_register(bank
);
1176 retval
= ERROR_FLASH_OPERATION_FAILED
;
1180 buffer
+= thisrun_count
;
1181 address
+= thisrun_count
;
1182 count
-= thisrun_count
;
1185 /* free up resources */
1188 target_free_working_area(target
, source
);
1190 if (cfi_info
->write_algorithm
)
1192 target_free_working_area(target
, cfi_info
->write_algorithm
);
1193 cfi_info
->write_algorithm
= NULL
;
1196 destroy_reg_param(®_params
[0]);
1197 destroy_reg_param(®_params
[1]);
1198 destroy_reg_param(®_params
[2]);
1199 destroy_reg_param(®_params
[3]);
1200 destroy_reg_param(®_params
[4]);
1201 destroy_reg_param(®_params
[5]);
1202 destroy_reg_param(®_params
[6]);
1207 int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1209 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1210 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1211 target_t
*target
= bank
->target
;
1212 reg_param_t reg_params
[10];
1213 armv4_5_algorithm_t armv4_5_info
;
1214 working_area_t
*source
;
1215 u32 buffer_size
= 32768;
1216 u8 write_command
[CFI_MAX_BUS_WIDTH
];
1220 int exit_code
= ERROR_OK
;
1222 /* input parameters - */
1223 /* R0 = source address */
1224 /* R1 = destination address */
1225 /* R2 = number of writes */
1226 /* R3 = flash write command */
1227 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1228 /* output parameters - */
1229 /* R5 = 0x80 ok 0x00 bad */
1230 /* temp registers - */
1231 /* R6 = value read from flash to test status */
1232 /* R7 = holding register */
1233 /* unlock registers - */
1234 /* R8 = unlock1_addr */
1235 /* R9 = unlock1_cmd */
1236 /* R10 = unlock2_addr */
1237 /* R11 = unlock2_cmd */
1239 u32 word_32_code
[] = {
1240 /* 00008100 <sp_32_code>: */
1241 0xe4905004, /* ldr r5, [r0], #4 */
1242 0xe5889000, /* str r9, [r8] */
1243 0xe58ab000, /* str r11, [r10] */
1244 0xe5883000, /* str r3, [r8] */
1245 0xe5815000, /* str r5, [r1] */
1246 0xe1a00000, /* nop */
1248 /* 00008110 <sp_32_busy>: */
1249 0xe5916000, /* ldr r6, [r1] */
1250 0xe0257006, /* eor r7, r5, r6 */
1251 0xe0147007, /* ands r7, r4, r7 */
1252 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1253 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1254 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1255 0xe5916000, /* ldr r6, [r1] */
1256 0xe0257006, /* eor r7, r5, r6 */
1257 0xe0147007, /* ands r7, r4, r7 */
1258 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1259 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1260 0x1a000004, /* bne 8154 <sp_32_done> */
1262 /* 00008140 <sp_32_cont>: */
1263 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1264 0x03a05080, /* moveq r5, #128 ; 0x80 */
1265 0x0a000001, /* beq 8154 <sp_32_done> */
1266 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1267 0xeaffffe8, /* b 8100 <sp_32_code> */
1269 /* 00008154 <sp_32_done>: */
1270 0xeafffffe /* b 8154 <sp_32_done> */
1273 u32 word_16_code
[] = {
1274 /* 00008158 <sp_16_code>: */
1275 0xe0d050b2, /* ldrh r5, [r0], #2 */
1276 0xe1c890b0, /* strh r9, [r8] */
1277 0xe1cab0b0, /* strh r11, [r10] */
1278 0xe1c830b0, /* strh r3, [r8] */
1279 0xe1c150b0, /* strh r5, [r1] */
1280 0xe1a00000, /* nop (mov r0,r0) */
1282 /* 00008168 <sp_16_busy>: */
1283 0xe1d160b0, /* ldrh r6, [r1] */
1284 0xe0257006, /* eor r7, r5, r6 */
1285 0xe0147007, /* ands r7, r4, r7 */
1286 0x0a000007, /* beq 8198 <sp_16_cont> */
1287 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1288 0x0afffff9, /* beq 8168 <sp_16_busy> */
1289 0xe1d160b0, /* ldrh r6, [r1] */
1290 0xe0257006, /* eor r7, r5, r6 */
1291 0xe0147007, /* ands r7, r4, r7 */
1292 0x0a000001, /* beq 8198 <sp_16_cont> */
1293 0xe3a05000, /* mov r5, #0 ; 0x0 */
1294 0x1a000004, /* bne 81ac <sp_16_done> */
1296 /* 00008198 <sp_16_cont>: */
1297 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1298 0x03a05080, /* moveq r5, #128 ; 0x80 */
1299 0x0a000001, /* beq 81ac <sp_16_done> */
1300 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1301 0xeaffffe8, /* b 8158 <sp_16_code> */
1303 /* 000081ac <sp_16_done>: */
1304 0xeafffffe /* b 81ac <sp_16_done> */
1307 u32 word_8_code
[] = {
1308 /* 000081b0 <sp_16_code_end>: */
1309 0xe4d05001, /* ldrb r5, [r0], #1 */
1310 0xe5c89000, /* strb r9, [r8] */
1311 0xe5cab000, /* strb r11, [r10] */
1312 0xe5c83000, /* strb r3, [r8] */
1313 0xe5c15000, /* strb r5, [r1] */
1314 0xe1a00000, /* nop (mov r0,r0) */
1316 /* 000081c0 <sp_8_busy>: */
1317 0xe5d16000, /* ldrb r6, [r1] */
1318 0xe0257006, /* eor r7, r5, r6 */
1319 0xe0147007, /* ands r7, r4, r7 */
1320 0x0a000007, /* beq 81f0 <sp_8_cont> */
1321 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1322 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1323 0xe5d16000, /* ldrb r6, [r1] */
1324 0xe0257006, /* eor r7, r5, r6 */
1325 0xe0147007, /* ands r7, r4, r7 */
1326 0x0a000001, /* beq 81f0 <sp_8_cont> */
1327 0xe3a05000, /* mov r5, #0 ; 0x0 */
1328 0x1a000004, /* bne 8204 <sp_8_done> */
1330 /* 000081f0 <sp_8_cont>: */
1331 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1332 0x03a05080, /* moveq r5, #128 ; 0x80 */
1333 0x0a000001, /* beq 8204 <sp_8_done> */
1334 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1335 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1337 /* 00008204 <sp_8_done>: */
1338 0xeafffffe /* b 8204 <sp_8_done> */
1341 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1342 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1343 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1345 /* flash write code */
1346 if (!cfi_info
->write_algorithm
)
1350 /* convert bus-width dependent algorithm code to correct endiannes */
1351 if (bank
->bus_width
== 1)
1353 code_p
= malloc(24 * 4);
1355 for (i
= 0; i
< 24; i
++)
1356 target_buffer_set_u32(target
, code_p
+ (i
*4), word_8_code
[i
]);
1358 else if (bank
->bus_width
== 2)
1360 code_p
= malloc(24 * 4);
1362 for (i
= 0; i
< 24; i
++)
1363 target_buffer_set_u32(target
, code_p
+ (i
*4), word_16_code
[i
]);
1365 else if (bank
->bus_width
== 4)
1367 code_p
= malloc(24 * 4);
1369 for (i
= 0; i
< 24; i
++)
1370 target_buffer_set_u32(target
, code_p
+ (i
*4), word_32_code
[i
]);
1374 return ERROR_FLASH_OPERATION_FAILED
;
1377 /* allocate working area */
1378 retval
=target_alloc_working_area(target
, 24 * 4,
1379 &cfi_info
->write_algorithm
);
1380 if (retval
!= ERROR_OK
)
1385 /* write algorithm code to working area */
1386 target_write_buffer(target
, cfi_info
->write_algorithm
->address
, 24 * 4, code_p
);
1391 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1394 if (buffer_size
<= 256)
1396 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1397 if (cfi_info
->write_algorithm
)
1398 target_free_working_area(target
, cfi_info
->write_algorithm
);
1400 WARNING("not enough working area available, can't do block memory writes");
1401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1405 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1406 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1407 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1408 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1409 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1410 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1411 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1412 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1413 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1414 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1418 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1420 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1422 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1423 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1424 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1425 cfi_command(bank
, 0xA0, write_command
);
1426 buf_set_u32(reg_params
[3].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1427 cfi_command(bank
, 0x80, write_command
);
1428 buf_set_u32(reg_params
[4].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1429 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1430 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaa);
1431 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1432 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55);
1434 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1435 cfi_info
->write_algorithm
->address
,
1436 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1437 10000, &armv4_5_info
);
1439 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1441 if ((retval
!= ERROR_OK
) || status
!= 0x80)
1443 DEBUG("status: 0x%x", status
);
1444 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1448 buffer
+= thisrun_count
;
1449 address
+= thisrun_count
;
1450 count
-= thisrun_count
;
1453 target_free_working_area(target
, source
);
1455 destroy_reg_param(®_params
[0]);
1456 destroy_reg_param(®_params
[1]);
1457 destroy_reg_param(®_params
[2]);
1458 destroy_reg_param(®_params
[3]);
1459 destroy_reg_param(®_params
[4]);
1460 destroy_reg_param(®_params
[5]);
1461 destroy_reg_param(®_params
[6]);
1462 destroy_reg_param(®_params
[7]);
1463 destroy_reg_param(®_params
[8]);
1464 destroy_reg_param(®_params
[9]);
1469 int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1471 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1472 target_t
*target
= bank
->target
;
1475 cfi_intel_clear_status_register(bank
);
1476 cfi_command(bank
, 0x40, command
);
1477 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1479 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1481 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1483 cfi_command(bank
, 0xff, command
);
1484 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1486 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1487 return ERROR_FLASH_OPERATION_FAILED
;
1493 int cfi_intel_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1495 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1496 target_t
*target
= bank
->target
;
1499 /* Calculate buffer size and boundary mask */
1500 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1501 u32 buffermask
= buffersize
-1;
1504 /* Check for valid range */
1505 if (address
& buffermask
)
1507 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1508 return ERROR_FLASH_OPERATION_FAILED
;
1510 switch(bank
->chip_width
)
1512 case 4 : bufferwsize
= buffersize
/ 4; break;
1513 case 2 : bufferwsize
= buffersize
/ 2; break;
1514 case 1 : bufferwsize
= buffersize
; break;
1516 ERROR("Unsupported chip width %d", bank
->chip_width
);
1517 return ERROR_FLASH_OPERATION_FAILED
;
1520 /* Check for valid size */
1521 if (wordcount
> bufferwsize
)
1523 ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1524 return ERROR_FLASH_OPERATION_FAILED
;
1527 /* Write to flash buffer */
1528 cfi_intel_clear_status_register(bank
);
1530 /* Initiate buffer operation _*/
1531 cfi_command(bank
, 0xE8, command
);
1532 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1533 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1535 cfi_command(bank
, 0xff, command
);
1536 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1538 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank
->base
, address
);
1539 return ERROR_FLASH_OPERATION_FAILED
;
1542 /* Write buffer wordcount-1 and data words */
1543 cfi_command(bank
, bufferwsize
-1, command
);
1544 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1546 target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
);
1548 /* Commit write operation */
1549 cfi_command(bank
, 0xd0, command
);
1550 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1551 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1553 cfi_command(bank
, 0xff, command
);
1554 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1556 ERROR("Buffer write at base 0x%x, address %x failed.", bank
->base
, address
);
1557 return ERROR_FLASH_OPERATION_FAILED
;
1563 int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1565 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1566 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1567 target_t
*target
= bank
->target
;
1570 cfi_command(bank
, 0xaa, command
);
1571 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1573 cfi_command(bank
, 0x55, command
);
1574 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
1576 cfi_command(bank
, 0xa0, command
);
1577 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1579 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1581 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1583 cfi_command(bank
, 0xf0, command
);
1584 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1586 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1587 return ERROR_FLASH_OPERATION_FAILED
;
1593 int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1595 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1597 switch(cfi_info
->pri_id
)
1601 return cfi_intel_write_word(bank
, word
, address
);
1604 return cfi_spansion_write_word(bank
, word
, address
);
1607 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1611 return ERROR_FLASH_OPERATION_FAILED
;
1614 int cfi_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1616 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1618 switch(cfi_info
->pri_id
)
1622 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1625 //return cfi_spansion_write_words(bank, word, address);
1626 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info
->pri_id
);
1629 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1633 return ERROR_FLASH_OPERATION_FAILED
;
1636 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1638 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1639 target_t
*target
= bank
->target
;
1640 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1641 u32 write_p
, copy_p
;
1642 int align
; /* number of unaligned bytes */
1643 int blk_count
; /* number of bus_width bytes for block copy */
1644 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1648 if (offset
+ count
> bank
->size
)
1649 return ERROR_FLASH_DST_OUT_OF_BANK
;
1651 if (cfi_info
->qry
[0] != 'Q')
1652 return ERROR_FLASH_BANK_NOT_PROBED
;
1654 /* start at the first byte of the first word (bus_width size) */
1655 write_p
= address
& ~(bank
->bus_width
- 1);
1656 if ((align
= address
- write_p
) != 0)
1658 INFO("Fixup %d unaligned head bytes", align
);
1660 for (i
= 0; i
< bank
->bus_width
; i
++)
1661 current_word
[i
] = 0;
1664 /* copy bytes before the first write address */
1665 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1668 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1669 cfi_add_byte(bank
, current_word
, byte
);
1672 /* add bytes from the buffer */
1673 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1675 cfi_add_byte(bank
, current_word
, *buffer
++);
1680 /* if the buffer is already finished, copy bytes after the last write address */
1681 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1684 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1685 cfi_add_byte(bank
, current_word
, byte
);
1688 retval
= cfi_write_word(bank
, current_word
, write_p
);
1689 if (retval
!= ERROR_OK
)
1694 /* handle blocks of bus_size aligned bytes */
1695 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1696 switch(cfi_info
->pri_id
)
1698 /* try block writes (fails without working area) */
1701 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1704 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1707 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1708 retval
= ERROR_FLASH_OPERATION_FAILED
;
1711 if (retval
== ERROR_OK
)
1713 /* Increment pointers and decrease count on succesful block write */
1714 buffer
+= blk_count
;
1715 write_p
+= blk_count
;
1720 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1722 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1723 u32 buffermask
= buffersize
-1;
1726 switch(bank
->chip_width
)
1728 case 4 : bufferwsize
= buffersize
/ 4; break;
1729 case 2 : bufferwsize
= buffersize
/ 2; break;
1730 case 1 : bufferwsize
= buffersize
; break;
1732 ERROR("Unsupported chip width %d", bank
->chip_width
);
1733 return ERROR_FLASH_OPERATION_FAILED
;
1736 /* fall back to memory writes */
1737 while (count
> bank
->bus_width
)
1739 if ((write_p
& 0xff) == 0)
1741 INFO("Programming at %08x, count %08x bytes remaining", write_p
, count
);
1744 /* NB! this is broken for spansion! */
1745 if ((count
> bufferwsize
) && !(write_p
& buffermask
))
1747 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1748 if (retval
!= ERROR_OK
)
1751 buffer
+= buffersize
;
1752 write_p
+= buffersize
;
1753 count
-= buffersize
;
1758 for (i
= 0; i
< bank
->bus_width
; i
++)
1759 current_word
[i
] = 0;
1761 for (i
= 0; i
< bank
->bus_width
; i
++)
1763 cfi_add_byte(bank
, current_word
, *buffer
++);
1766 retval
= cfi_write_word(bank
, current_word
, write_p
);
1767 if (retval
!= ERROR_OK
)
1770 write_p
+= bank
->bus_width
;
1771 count
-= bank
->bus_width
;
1779 /* return to read array mode, so we can read from flash again for padding */
1780 cfi_command(bank
, 0xf0, current_word
);
1781 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1782 cfi_command(bank
, 0xff, current_word
);
1783 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1785 /* handle unaligned tail bytes */
1788 INFO("Fixup %d unaligned tail bytes", count
);
1791 for (i
= 0; i
< bank
->bus_width
; i
++)
1792 current_word
[i
] = 0;
1794 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
1796 cfi_add_byte(bank
, current_word
, *buffer
++);
1799 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
1802 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1803 cfi_add_byte(bank
, current_word
, byte
);
1805 retval
= cfi_write_word(bank
, current_word
, write_p
);
1806 if (retval
!= ERROR_OK
)
1810 /* return to read array mode */
1811 cfi_command(bank
, 0xf0, current_word
);
1812 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1813 cfi_command(bank
, 0xff, current_word
);
1814 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1819 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
1821 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1822 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1824 pri_ext
->_reversed_geometry
= 1;
1827 void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
1830 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1831 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1833 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
1835 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1837 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
1839 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
1842 swap
= cfi_info
->erase_region_info
[i
];
1843 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
1844 cfi_info
->erase_region_info
[j
] = swap
;
1849 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
1851 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1852 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1853 cfi_unlock_addresses_t
*unlock_addresses
= param
;
1855 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
1856 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
1859 int cfi_probe(struct flash_bank_s
*bank
)
1861 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1862 target_t
*target
= bank
->target
;
1864 int num_sectors
= 0;
1868 u32 unlock1
= 0x555;
1869 u32 unlock2
= 0x2aa;
1871 cfi_info
->probed
= 0;
1873 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1874 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1876 if (cfi_info
->jedec_probe
)
1882 /* switch to read identifier codes mode ("AUTOSELECT") */
1883 cfi_command(bank
, 0xaa, command
);
1884 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1885 cfi_command(bank
, 0x55, command
);
1886 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
);
1887 cfi_command(bank
, 0x90, command
);
1888 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1890 if (bank
->chip_width
== 1)
1892 u8 manufacturer
, device_id
;
1893 target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
);
1894 target_read_u8(target
, bank
->base
+ 0x1, &device_id
);
1895 cfi_info
->manufacturer
= manufacturer
;
1896 cfi_info
->device_id
= device_id
;
1898 else if (bank
->chip_width
== 2)
1900 target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
);
1901 target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
);
1904 /* switch back to read array mode */
1905 cfi_command(bank
, 0xf0, command
);
1906 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1907 cfi_command(bank
, 0xff, command
);
1908 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1910 cfi_fixup(bank
, cfi_jedec_fixups
);
1912 /* query only if this is a CFI compatible flash,
1913 * otherwise the relevant info has already been filled in
1915 if (cfi_info
->not_cfi
== 0)
1917 /* enter CFI query mode
1918 * according to JEDEC Standard No. 68.01,
1919 * a single bus sequence with address = 0x55, data = 0x98 should put
1920 * the device into CFI query mode.
1922 * SST flashes clearly violate this, and we will consider them incompatbile for now
1924 cfi_command(bank
, 0x98, command
);
1925 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
1927 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
1928 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
1929 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
1931 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
1933 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
1935 cfi_command(bank
, 0xf0, command
);
1936 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1937 cfi_command(bank
, 0xff, command
);
1938 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1939 return ERROR_FLASH_BANK_INVALID
;
1942 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
1943 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
1944 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
1945 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
1947 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
1949 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
1950 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
1951 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
1952 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
1953 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
1954 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
1955 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
1956 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
1957 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
1958 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
1959 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
1960 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
1962 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1963 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
1964 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
1965 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
1966 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
1967 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
1968 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
1969 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
1970 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
1971 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
1972 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
1974 cfi_info
->dev_size
= cfi_query_u8(bank
, 0, 0x27);
1975 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
1976 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
1977 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
1979 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
1981 if (((1 << cfi_info
->dev_size
) * bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
1983 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, 1 << cfi_info
->dev_size
);
1986 if (cfi_info
->num_erase_regions
)
1988 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
1989 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
1991 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
1992 DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
1997 cfi_info
->erase_region_info
= NULL
;
2000 /* We need to read the primary algorithm extended query table before calculating
2001 * the sector layout to be able to apply fixups
2003 switch(cfi_info
->pri_id
)
2005 /* Intel command set (standard and extended) */
2008 cfi_read_intel_pri_ext(bank
);
2010 /* AMD/Spansion, Atmel, ... command set */
2012 cfi_read_0002_pri_ext(bank
);
2015 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2019 /* return to read array mode
2020 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2022 cfi_command(bank
, 0xf0, command
);
2023 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2024 cfi_command(bank
, 0xff, command
);
2025 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2028 /* apply fixups depending on the primary command set */
2029 switch(cfi_info
->pri_id
)
2031 /* Intel command set (standard and extended) */
2034 cfi_fixup(bank
, cfi_0001_fixups
);
2036 /* AMD/Spansion, Atmel, ... command set */
2038 cfi_fixup(bank
, cfi_0002_fixups
);
2041 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2045 if (cfi_info
->num_erase_regions
== 0)
2047 /* a device might have only one erase block, spanning the whole device */
2048 bank
->num_sectors
= 1;
2049 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2051 bank
->sectors
[sector
].offset
= 0x0;
2052 bank
->sectors
[sector
].size
= bank
->size
;
2053 bank
->sectors
[sector
].is_erased
= -1;
2054 bank
->sectors
[sector
].is_protected
= -1;
2058 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2060 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2063 bank
->num_sectors
= num_sectors
;
2064 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2066 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2069 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2071 bank
->sectors
[sector
].offset
= offset
;
2072 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2073 offset
+= bank
->sectors
[sector
].size
;
2074 bank
->sectors
[sector
].is_erased
= -1;
2075 bank
->sectors
[sector
].is_protected
= -1;
2081 cfi_info
->probed
= 1;
2086 int cfi_auto_probe(struct flash_bank_s
*bank
)
2088 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2089 if (cfi_info
->probed
)
2091 return cfi_probe(bank
);
2094 int cfi_erase_check(struct flash_bank_s
*bank
)
2096 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2097 target_t
*target
= bank
->target
;
2101 if (!cfi_info
->erase_check_algorithm
)
2103 u32 erase_check_code
[] =
2105 0xe4d03001, /* ldrb r3, [r0], #1 */
2106 0xe0022003, /* and r2, r2, r3 */
2107 0xe2511001, /* subs r1, r1, #1 */
2108 0x1afffffb, /* b -4 */
2109 0xeafffffe /* b 0 */
2112 /* make sure we have a working area */
2113 if (target_alloc_working_area(target
, 20, &cfi_info
->erase_check_algorithm
) != ERROR_OK
)
2115 WARNING("no working area available, falling back to slow memory reads");
2119 u8 erase_check_code_buf
[5 * 4];
2121 for (i
= 0; i
< 5; i
++)
2122 target_buffer_set_u32(target
, erase_check_code_buf
+ (i
*4), erase_check_code
[i
]);
2124 /* write algorithm code to working area */
2125 target
->type
->write_memory(target
, cfi_info
->erase_check_algorithm
->address
, 4, 5, erase_check_code_buf
);
2129 if (!cfi_info
->erase_check_algorithm
)
2131 u32
*buffer
= malloc(4096);
2133 for (i
= 0; i
< bank
->num_sectors
; i
++)
2135 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2136 u32 size
= bank
->sectors
[i
].size
;
2137 u32 check
= 0xffffffffU
;
2142 u32 thisrun_size
= (size
> 4096) ? 4096 : size
;
2145 target
->type
->read_memory(target
, address
, 4, thisrun_size
/ 4, (u8
*)buffer
);
2147 for (j
= 0; j
< thisrun_size
/ 4; j
++)
2150 if (check
!= 0xffffffff)
2156 size
-= thisrun_size
;
2157 address
+= thisrun_size
;
2160 bank
->sectors
[i
].is_erased
= erased
;
2167 for (i
= 0; i
< bank
->num_sectors
; i
++)
2169 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2170 u32 size
= bank
->sectors
[i
].size
;
2172 reg_param_t reg_params
[3];
2173 armv4_5_algorithm_t armv4_5_info
;
2175 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2176 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2177 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2179 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
2180 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2182 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2183 buf_set_u32(reg_params
[1].value
, 0, 32, size
);
2185 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
2186 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
2188 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
, cfi_info
->erase_check_algorithm
->address
, cfi_info
->erase_check_algorithm
->address
+ 0x10, 10000, &armv4_5_info
)) != ERROR_OK
)
2189 return ERROR_FLASH_OPERATION_FAILED
;
2191 if (buf_get_u32(reg_params
[2].value
, 0, 32) == 0xff)
2192 bank
->sectors
[i
].is_erased
= 1;
2194 bank
->sectors
[i
].is_erased
= 0;
2196 destroy_reg_param(®_params
[0]);
2197 destroy_reg_param(®_params
[1]);
2198 destroy_reg_param(®_params
[2]);
2205 int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2207 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2208 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2209 target_t
*target
= bank
->target
;
2210 u8 command
[CFI_MAX_BUS_WIDTH
];
2213 /* check if block lock bits are supported on this device */
2214 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2215 return ERROR_FLASH_OPERATION_FAILED
;
2217 cfi_command(bank
, 0x90, command
);
2218 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
2220 for (i
= 0; i
< bank
->num_sectors
; i
++)
2222 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2224 if (block_status
& 1)
2225 bank
->sectors
[i
].is_protected
= 1;
2227 bank
->sectors
[i
].is_protected
= 0;
2230 cfi_command(bank
, 0xff, command
);
2231 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2236 int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2238 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2239 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2240 target_t
*target
= bank
->target
;
2244 cfi_command(bank
, 0xaa, command
);
2245 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2247 cfi_command(bank
, 0x55, command
);
2248 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
2250 cfi_command(bank
, 0x90, command
);
2251 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2253 for (i
= 0; i
< bank
->num_sectors
; i
++)
2255 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2257 if (block_status
& 1)
2258 bank
->sectors
[i
].is_protected
= 1;
2260 bank
->sectors
[i
].is_protected
= 0;
2263 cfi_command(bank
, 0xf0, command
);
2264 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2269 int cfi_protect_check(struct flash_bank_s
*bank
)
2271 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2273 if (cfi_info
->qry
[0] != 'Q')
2274 return ERROR_FLASH_BANK_NOT_PROBED
;
2276 switch(cfi_info
->pri_id
)
2280 return cfi_intel_protect_check(bank
);
2283 return cfi_spansion_protect_check(bank
);
2286 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2293 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2296 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2298 if (cfi_info
->qry
[0] == (char)-1)
2300 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2304 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2306 buf_size
-= printed
;
2308 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2309 cfi_info
->manufacturer
, cfi_info
->device_id
);
2311 buf_size
-= printed
;
2313 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2315 buf_size
-= printed
;
2317 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2318 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2319 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2320 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2322 buf_size
-= printed
;
2324 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2325 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2327 buf_size
-= printed
;
2329 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2330 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2331 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2332 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2334 buf_size
-= printed
;
2336 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, cfi_info
->max_buf_write_size
);
2338 buf_size
-= printed
;
2340 switch(cfi_info
->pri_id
)
2344 cfi_intel_info(bank
, buf
, buf_size
);
2347 cfi_spansion_info(bank
, buf
, buf_size
);
2350 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);