target/arm_adi_v5: fix sync CSW cache on apreg write
[openocd.git] / src / target / esirisc.h
blobbb50652aa86e08c335e3f9133e970e59619d49c1
1 /***************************************************************************
2 * Copyright (C) 2018 by Square, Inc. *
3 * Steven Stallion <stallion@squareup.com> *
4 * James Zhao <hjz@squareup.com> *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
18 ***************************************************************************/
20 #ifndef OPENOCD_TARGET_ESIRISC_H
21 #define OPENOCD_TARGET_ESIRISC_H
23 #include <target/breakpoints.h>
24 #include <target/register.h>
25 #include <target/target.h>
27 #include "esirisc_jtag.h"
28 #include "esirisc_regs.h"
30 #define MAX_BREAKPOINTS 8
31 #define MAX_WATCHPOINTS 8
33 /* Exception IDs */
34 #define EID_RESET 0x00
35 #define EID_HARDWARE_FAILURE 0x01
36 #define EID_NMI 0x02
37 #define EID_INST_BREAKPOINT 0x03
38 #define EID_DATA_BREAKPOINT 0x04
39 #define EID_UNSUPPORTED 0x05
40 #define EID_PRIVILEGE_VIOLATION 0x06
41 #define EID_INST_BUS_ERROR 0x07
42 #define EID_DATA_BUS_ERROR 0x08
43 #define EID_ALIGNMENT_ERROR 0x09
44 #define EID_ARITHMETIC_ERROR 0x0a
45 #define EID_SYSTEM_CALL 0x0b
46 #define EID_MEMORY_MANAGEMENT 0x0c
47 #define EID_UNRECOVERABLE 0x0d
48 #define EID_INTERRUPTn 0x20
50 /* Exception Entry Points */
51 #define ENTRY_RESET 0x00
52 #define ENTRY_UNRECOVERABLE 0x01
53 #define ENTRY_HARDWARE_FAILURE 0x02
54 #define ENTRY_RUNTIME 0x03
55 #define ENTRY_MEMORY 0x04
56 #define ENTRY_SYSCALL 0x05
57 #define ENTRY_DEBUG 0x06
58 #define ENTRY_NMI 0x07
59 #define ENTRY_INTERRUPTn 0x08
61 /* Hardware Debug Control */
62 #define HWDC_R (1<<4) /* Reset & Hardware Failure */
63 #define HWDC_I (1<<3) /* Interrupts */
64 #define HWDC_S (1<<2) /* System Calls */
65 #define HWDC_E (1<<1) /* Program Errors */
66 #define HWDC_D (1<<0) /* Debug Exceptions */
68 enum esirisc_cache {
69 ESIRISC_CACHE_VON_NEUMANN,
70 ESIRISC_CACHE_HARVARD,
73 struct esirisc_common {
74 struct target *target;
75 struct esirisc_jtag jtag_info;
76 enum esirisc_cache cache_arch;
77 char *gdb_arch;
79 struct reg_cache *reg_cache;
80 struct reg *epc;
81 struct reg *ecas;
82 struct reg *eid;
83 struct reg *ed;
84 uint32_t etc_save;
85 uint32_t hwdc_save;
87 int num_bits;
88 int num_regs;
89 bool has_icache;
90 bool has_dcache;
91 int num_breakpoints;
92 int num_watchpoints;
94 struct breakpoint *breakpoints_p[MAX_BREAKPOINTS];
95 struct watchpoint *watchpoints_p[MAX_WATCHPOINTS];
98 union esirisc_memory {
99 uint32_t word;
100 uint16_t hword;
101 uint8_t byte;
104 struct esirisc_reg {
105 struct esirisc_common *esirisc;
107 uint8_t bank;
108 uint8_t csr;
110 int (*read)(struct reg *reg);
111 int (*write)(struct reg *reg);
114 static inline struct esirisc_common *target_to_esirisc(struct target *target)
116 return (struct esirisc_common *)target->arch_info;
119 static inline char *esirisc_cache_arch(struct esirisc_common *esirisc)
121 return esirisc->cache_arch == ESIRISC_CACHE_HARVARD ? "harvard" : "von_neumann";
124 static inline bool esirisc_has_cache(struct esirisc_common *esirisc)
126 return esirisc->has_icache || esirisc->has_dcache;
129 #endif /* OPENOCD_TARGET_ESIRISC_H */