src/target/arm_disassembler.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
  20 #define OPENOCD_TARGET_ARM_DISASSEMBLER_H
  21
  22 enum arm_instruction_type {
  23         ARM_UNKNOWN_INSTUCTION,
  24
  25         /* Branch instructions */
  26         ARM_B,
  27         ARM_BL,
  28         ARM_BX,
  29         ARM_BLX,
  30
  31         /* Data processing instructions */
  32         ARM_AND,
  33         ARM_EOR,
  34         ARM_SUB,
  35         ARM_RSB,
  36         ARM_ADD,
  37         ARM_ADC,
  38         ARM_SBC,
  39         ARM_RSC,
  40         ARM_TST,
  41         ARM_TEQ,
  42         ARM_CMP,
  43         ARM_CMN,
  44         ARM_ORR,
  45         ARM_MOV,
  46         ARM_BIC,
  47         ARM_MVN,
  48
  49         /* Load/store instructions */
  50         ARM_LDR,
  51         ARM_LDRB,
  52         ARM_LDRT,
  53         ARM_LDRBT,
  54
  55         ARM_LDRH,
  56         ARM_LDRSB,
  57         ARM_LDRSH,
  58
  59         ARM_LDM,
  60
  61         ARM_STR,
  62         ARM_STRB,
  63         ARM_STRT,
  64         ARM_STRBT,
  65
  66         ARM_STRH,
  67
  68         ARM_STM,
  69
  70         /* Status register access instructions */
  71         ARM_MRS,
  72         ARM_MSR,
  73
  74         /* Multiply instructions */
  75         ARM_MUL,
  76         ARM_MLA,
  77         ARM_SMULL,
  78         ARM_SMLAL,
  79         ARM_UMULL,
  80         ARM_UMLAL,
  81
  82         /* Miscellaneous instructions */
  83         ARM_CLZ,
  84
  85         /* Exception return instructions */
  86         ARM_ERET,
  87
  88         /* Exception generating instructions */
  89         ARM_BKPT,
  90         ARM_SWI,
  91         ARM_HVC,
  92         ARM_SMC,
  93
  94         /* Coprocessor instructions */
  95         ARM_CDP,
  96         ARM_LDC,
  97         ARM_STC,
  98         ARM_MCR,
  99         ARM_MRC,
 100
 101         /* Semaphore instructions */
 102         ARM_SWP,
 103         ARM_SWPB,
 104
 105         /* Enhanced DSP extensions */
 106         ARM_MCRR,
 107         ARM_MRRC,
 108         ARM_PLD,
 109         ARM_QADD,
 110         ARM_QDADD,
 111         ARM_QSUB,
 112         ARM_QDSUB,
 113         ARM_SMLAxy,
 114         ARM_SMLALxy,
 115         ARM_SMLAWy,
 116         ARM_SMULxy,
 117         ARM_SMULWy,
 118         ARM_LDRD,
 119         ARM_STRD,
 120
 121         ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 122 };
 123
 124 struct arm_b_bl_bx_blx_instr {
 125         int reg_operand;
 126         uint32_t target_address;
 127 };
 128
 129 union arm_shifter_operand {
 130         struct {
 131                 uint32_t immediate;
 132         } immediate;
 133         struct {
 134                 uint8_t Rm;
 135                 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 136                 uint8_t shift_imm;
 137         } immediate_shift;
 138         struct {
 139                 uint8_t Rm;
 140                 uint8_t shift;
 141                 uint8_t Rs;
 142         } register_shift;
 143 };
 144
 145 struct arm_data_proc_instr {
 146         int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
 147         uint8_t S;
 148         uint8_t Rn;
 149         uint8_t Rd;
 150         union arm_shifter_operand shifter_operand;
 151 };
 152
 153 struct arm_load_store_instr {
 154         uint8_t Rd;
 155         uint8_t Rn;
 156         uint8_t U;
 157         int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 158         int offset_mode; /* 0: immediate, 1: (scaled) register */
 159         union {
 160                 uint32_t offset;
 161                 struct {
 162                         uint8_t Rm;
 163                         uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 164                         uint8_t shift_imm;
 165                 } reg;
 166         } offset;
 167 };
 168
 169 struct arm_load_store_multiple_instr {
 170         uint8_t Rn;
 171         uint32_t register_list;
 172         uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
 173         uint8_t S;
 174         uint8_t W;
 175 };
 176
 177 struct arm_instruction {
 178         enum arm_instruction_type type;
 179         char text[128];
 180         uint32_t opcode;
 181
 182         /* return value ... Thumb-2 sizes vary */
 183         unsigned instruction_size;
 184
 185         union {
 186                 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
 187                 struct arm_data_proc_instr data_proc;
 188                 struct arm_load_store_instr load_store;
 189                 struct arm_load_store_multiple_instr load_store_multiple;
 190         } info;
 191
 192 };
 193
 194 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
 195                 struct arm_instruction *instruction);
 196 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
 197                 struct arm_instruction *instruction);
 198 int thumb2_opcode(struct target *target, uint32_t address,
 199                 struct arm_instruction *instruction);
 200 int arm_access_size(struct arm_instruction *instruction);
 201
 202 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 203
 204 #endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */