From 67b5f0d984bc6a0965e6c3b59d07fd346cbcf122 Mon Sep 17 00:00:00 2001 From: afaerber Date: Sat, 20 Nov 2010 21:14:59 +0000 Subject: [PATCH] ppc: Turn 32-bit ppc64 into a config option, to be deprecated MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Having legacy 64-bit support as an option allows users to disable it and test the 32-bit only version prior to official removal of legacy 64-bit support. Fork single-bitness macros EXCEPTION_{PREAMBLE,EPILOGUE}: Use assembler macros for things that are constant to avoid ; and \, and use preprocessor macros to handle differences. Adopt QEMU coding style for new code. Functional changes for ppc64: * Don't clear MSR in preamble in order to stay in Sixty-Four Bit Mode. * Just save the minimum number of registers since 64-bit code will save the full registers. * Reserve 48 bytes of stack frame space for ppc64, according to 64-bit PowerPC ELF ABI supplement 1.9. * Use rfid via RFI macro. v2: * Remove inaccurate comment on unused stack location. * Add explanatory comments for #else and #endif. Cc: Alexander Graf Signed-off-by: Andreas Färber git-svn-id: svn://openbios.org/openbios/trunk/openbios-devel@962 f158a5a8-5612-0410-a976-696ce0be7e32 --- arch/ppc/qemu/init.c | 4 ++ arch/ppc/qemu/start.S | 90 +++++++++++++++++++++++++++++++++++++++++- config/examples/ppc_config.xml | 1 + 3 files changed, 94 insertions(+), 1 deletion(-) diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index ba215bc..834e65d 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -303,6 +303,7 @@ cpu_g4_init(const struct cpudef *cpu) fword("finish-device"); } +#ifdef CONFIG_PPC_64BITSUPPORT /* In order to get 64 bit aware handlers that rescue all our GPRs from getting truncated to 32 bits, we need to patch the existing handlers so they jump to our 64 bit aware ones. */ @@ -322,6 +323,7 @@ ppc64_patch_handlers(void) asm ( "icbi 0, %0" : : "r"(dsi) ); asm ( "icbi 0, %0" : : "r"(isi) ); } +#endif static void cpu_970_init(const struct cpudef *cpu) @@ -341,10 +343,12 @@ cpu_970_init(const struct cpudef *cpu) fword("finish-device"); +#ifdef CONFIG_PPC_64BITSUPPORT /* The 970 is a PPC64 CPU, so we need to activate * 64bit aware interrupt handlers */ ppc64_patch_handlers(); +#endif /* The 970 also implements the HIOR which we need to set to 0 */ diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index e86bdfd..eef4293 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -14,6 +14,7 @@ * */ +#include "autoconf.h" #include "asm/asmdefs.h" #include "asm/processor.h" @@ -24,6 +25,8 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v +#ifdef CONFIG_PPC_64BITSUPPORT + /* We're trying to use the same code for the ppc32 and ppc64 handlers here. * On ppc32 we only save/restore the registers, C considers volatile. * @@ -176,6 +179,87 @@ #undef stl #undef ll +#else /* !CONFIG_PPC_64BITSUPPORT */ + +#ifdef __powerpc64__ + +#define ULONG_SIZE 8 +#define STACKFRAME_MINSIZE 48 +#define stl std +#define ll ld + +#else + +#define ULONG_SIZE 4 +#define STACKFRAME_MINSIZE 16 +#define stl stw +#define ll lwz + +#endif + +.macro EXCEPTION_PREAMBLE + mtsprg1 r1 /* scratch */ + mfsprg0 r1 /* exception stack in sprg0 */ + addi r1, r1, -(20 * ULONG_SIZE) /* push exception frame */ + + stl r0, ( 0 * ULONG_SIZE)(r1) /* save r0 */ + mfsprg1 r0 + stl r0, ( 1 * ULONG_SIZE)(r1) /* save r1 */ + stl r2, ( 2 * ULONG_SIZE)(r1) /* save r2 */ + stl r3, ( 3 * ULONG_SIZE)(r1) /* save r3 */ + stl r4, ( 4 * ULONG_SIZE)(r1) + stl r5, ( 5 * ULONG_SIZE)(r1) + stl r6, ( 6 * ULONG_SIZE)(r1) + stl r7, ( 7 * ULONG_SIZE)(r1) + stl r8, ( 8 * ULONG_SIZE)(r1) + stl r9, ( 9 * ULONG_SIZE)(r1) + stl r10, (10 * ULONG_SIZE)(r1) + stl r11, (11 * ULONG_SIZE)(r1) + stl r12, (12 * ULONG_SIZE)(r1) + + mflr r0 + stl r0, (13 * ULONG_SIZE)(r1) + mfcr r0 + stl r0, (14 * ULONG_SIZE)(r1) + mfctr r0 + stl r0, (15 * ULONG_SIZE)(r1) + mfxer r0 + stl r0, (16 * ULONG_SIZE)(r1) + + addi r1, r1, -STACKFRAME_MINSIZE /* C ABI saves LR and SP */ +.endm + +.macro EXCEPTION_EPILOGUE + addi r1, r1, STACKFRAME_MINSIZE /* pop ABI frame */ + + ll r0, (13 * ULONG_SIZE)(r1) + mtlr r0 + ll r0, (14 * ULONG_SIZE)(r1) + mtcr r0 + ll r0, (15 * ULONG_SIZE)(r1) + mtctr r0 + ll r0, (16 * ULONG_SIZE)(r1) + mtxer r0 + + ll r0, ( 0 * ULONG_SIZE)(r1) + ll r2, ( 2 * ULONG_SIZE)(r1) + ll r3, ( 3 * ULONG_SIZE)(r1) + ll r4, ( 4 * ULONG_SIZE)(r1) + ll r5, ( 5 * ULONG_SIZE)(r1) + ll r6, ( 6 * ULONG_SIZE)(r1) + ll r7, ( 7 * ULONG_SIZE)(r1) + ll r8, ( 8 * ULONG_SIZE)(r1) + ll r9, ( 9 * ULONG_SIZE)(r1) + ll r10, (10 * ULONG_SIZE)(r1) + ll r11, (11 * ULONG_SIZE)(r1) + ll r12, (12 * ULONG_SIZE)(r1) + + ll r1, ( 1 * ULONG_SIZE)(r1) /* restore stack at last */ + RFI +.endm + +#endif /* !CONFIG_PPC_64BITSUPPORT */ + /************************************************************************/ /* vectors */ /************************************************************************/ @@ -253,6 +337,8 @@ ILLEGAL_VECTOR( 0x1500 ) ILLEGAL_VECTOR( 0x1600 ) ILLEGAL_VECTOR( 0x1700 ) +#ifdef CONFIG_PPC_64BITSUPPORT + VECTOR( 0x2000, "DSI_64" ): EXCEPTION_PREAMBLE_64 LOAD_REG_IMMEDIATE(r3, dsi_exception) @@ -267,6 +353,8 @@ VECTOR( 0x2200, "ISI_64" ): bctrl EXCEPTION_EPILOGUE_64 +#endif + GLOBL(__vectors_end): /************************************************************************/ @@ -275,7 +363,7 @@ GLOBL(__vectors_end): GLOBL(_entry): -#ifndef __powerpc64__ +#ifdef CONFIG_PPC_64BITSUPPORT /* clear MSR, disable MMU */ li r0,0 diff --git a/config/examples/ppc_config.xml b/config/examples/ppc_config.xml index 5f79c21..352cb57 100644 --- a/config/examples/ppc_config.xml +++ b/config/examples/ppc_config.xml @@ -57,6 +57,7 @@