1 ;; GCC machine description for picochip
2 ;; Copyright (C) 2008 Free Software Foundation, Inc.
3 ;; Contributed by Picochip Ltd (http://www.picochip.com)
4 ;; Maintained by Daniel Towner (dant@picochip.com) and Hariharan
5 ;; Sandanagobalane (hariharan@picochip.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not, see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; The following DFA description schedules instructions for speed. In
24 ;; addition to the scheduling of instructions to remove stall cycles
25 ;; (e.g., memory load), the scheduler will also pack multiple
26 ;; instructions into a single cycle, using VLIW.
28 ;; Each instruction comes in forms with and without long
29 ;; constants. The long constant is treated as though it were also an
30 ;; instruction. Thus, an instruction which used slot0, will use slot0
31 ;; plus one of the other slots for the constant. This mechanism
32 ;; ensures that it is impossible for 3 instructions to be issued, if
33 ;; one of them has a long constant. This is necessary, because the
34 ;; encoding of 3 instructions, plus a constant, will overrun the
37 ; Extended ALU - Slot 0
38 (define_insn_reservation "picoAluInsn" 1
39 (and (eq_attr "schedType" "speed")
40 (and (eq_attr "type" "picoAlu") (eq_attr "longConstant" "false")))
42 (define_insn_reservation "picoAluInsnWithConst" 1
43 (and (eq_attr "schedType" "speed")
44 (and (eq_attr "type" "picoAlu") (eq_attr "longConstant" "true")))
45 "(slot0+slot1)|(slot0+slot2)")
47 ; Basic ALU - Slot 0 or 1
48 (define_insn_reservation "basicAluInsn" 1
49 (and (eq_attr "schedType" "speed")
50 (and (eq_attr "type" "basicAlu") (eq_attr "longConstant" "false")))
52 (define_insn_reservation "basicAluInsnWithConst" 1
53 (and (eq_attr "schedType" "speed")
54 (and (eq_attr "type" "basicAlu") (eq_attr "longConstant" "true")))
55 "(slot0+slot1) | (slot1+slot2) | (slot0+slot2)")
57 ; ALU which must not set flags - Slot 1
58 (define_insn_reservation "nonCcAluInsn" 1
59 (and (eq_attr "schedType" "speed")
60 (and (eq_attr "type" "nonCcAlu") (eq_attr "longConstant" "false")))
62 (define_insn_reservation "nonCcAluInsnWithConst" 1
63 (and (eq_attr "schedType" "speed")
64 (and (eq_attr "type" "nonCcAlu") (eq_attr "longConstant" "true")))
65 "(slot1+slot0) | (slot1+slot2)")
68 (define_insn_reservation "memInsn" 2
69 (and (eq_attr "schedType" "speed")
70 (and (eq_attr "type" "mem") (eq_attr "longConstant" "false")))
72 (define_insn_reservation "memInsnWithConst" 2
73 (and (eq_attr "schedType" "speed")
74 (and (eq_attr "type" "mem") (eq_attr "longConstant" "true")))
75 "slot1+(slot0|slot2),nothing")
78 (define_insn_reservation "mulInsn" 1
79 (and (eq_attr "schedType" "speed")
80 (and (eq_attr "type" "mul") (eq_attr "longConstant" "false")))
82 (define_insn_reservation "mulInsnWithConst" 1
83 (and (eq_attr "schedType" "speed")
84 (and (eq_attr "type" "mul") (eq_attr "longConstant" "true")))
85 "(slot2+slot0)|(slot2+slot1)")
88 (define_insn_reservation "macInsn" 1
89 (and (eq_attr "schedType" "speed")
90 (and (eq_attr "type" "mac") (eq_attr "longConstant" "false")))
92 (define_insn_reservation "macInsnWithConst" 1
93 (and (eq_attr "schedType" "speed")
94 (and (eq_attr "type" "mac") (eq_attr "longConstant" "true")))
95 "(slot2+slot0)|(slot2+slot1)")
97 ; Branch - Real branches use slot2, while macro branches use unknown
99 (define_insn_reservation "branchInsn" 1
100 (and (eq_attr "schedType" "speed")
101 (and (eq_attr "type" "realBranch") (eq_attr "longConstant" "false")))
103 (define_insn_reservation "branchInsnWithConst" 1
104 (and (eq_attr "schedType" "speed")
105 (and (eq_attr "type" "realBranch") (eq_attr "longConstant" "true")))
106 "(slot2+slot0)|(slot2+slot1)")
107 (define_insn_reservation "branchInsnMacro" 1
108 (and (eq_attr "schedType" "speed")
109 (eq_attr "type" "realBranch"))
110 "(slot0+slot1+slot2)")
112 ; Call instructions use all slots to prevent inadvertent scheduling
113 ; alongside instructions which set R12.
115 (define_insn_reservation "callInsn" 1
116 (and (eq_attr "schedType" "speed") (eq_attr "type" "call"))
119 ; Communications - Slot 1
120 (define_insn_reservation "commsInsn" 1
121 (and (eq_attr "schedType" "speed") (eq_attr "type" "comms"))