1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
26 (define_enum "processor" [
68 (define_c_enum "unspec" [
69 ;; Unaligned accesses.
75 ;; Floating-point moves.
91 UNSPEC_POTENTIAL_CPRESTORE
96 UNSPEC_SET_GOT_VERSION
97 UNSPEC_UPDATE_GOT_VERSION
105 ;; MIPS16 constant pools.
107 UNSPEC_CONSTTABLE_INT
108 UNSPEC_CONSTTABLE_FLOAT
110 ;; Blockage and synchronisation.
117 ;; Cache manipulation.
119 UNSPEC_R10K_CACHE_BARRIER
121 ;; Interrupt handling.
129 ;; Used in a call expression in place of args_size. It's present for PIC
130 ;; indirect calls where it contains args_size and the function symbol.
135 [(TLS_GET_TP_REGNUM 3)
136 (RETURN_ADDR_REGNUM 31)
137 (CPRESTORE_SLOT_REGNUM 76)
138 (GOT_VERSION_REGNUM 79)
140 ;; PIC long branch sequences are never longer than 100 bytes.
141 (MAX_PIC_BRANCH_LENGTH 100)
145 (include "predicates.md")
146 (include "constraints.md")
148 ;; ....................
152 ;; ....................
154 (define_attr "got" "unset,xgot_high,load"
155 (const_string "unset"))
157 ;; For jal instructions, this attribute is DIRECT when the target address
158 ;; is symbolic and INDIRECT when it is a register.
159 (define_attr "jal" "unset,direct,indirect"
160 (const_string "unset"))
162 ;; This attribute is YES if the instruction is a jal macro (not a
163 ;; real jal instruction).
165 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
166 ;; an instruction to restore $gp. Direct jals are also macros for
167 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
169 (define_attr "jal_macro" "no,yes"
170 (cond [(eq_attr "jal" "direct")
171 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
172 ? JAL_MACRO_YES : JAL_MACRO_NO)")
173 (eq_attr "jal" "indirect")
174 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
175 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
176 (const_string "no")))
178 ;; Classification of moves, extensions and truncations. Most values
179 ;; are as for "type" (see below) but there are also the following
180 ;; move-specific values:
182 ;; constN move an N-constraint integer into a MIPS16 register
183 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
184 ;; to produce a sign-extended DEST, even if SRC is not
185 ;; properly sign-extended
186 ;; ext_ins EXT, DEXT, INS or DINS instruction
187 ;; andi a single ANDI instruction
188 ;; loadpool move a constant into a MIPS16 register by loading it
190 ;; shift_shift a shift left followed by a shift right
191 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
193 ;; This attribute is used to determine the instruction's length and
194 ;; scheduling type. For doubleword moves, the attribute always describes
195 ;; the split instructions; in some cases, it is more appropriate for the
196 ;; scheduling type to be "multi" instead.
197 (define_attr "move_type"
198 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
199 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
200 shift_shift,lui_movf"
201 (const_string "unknown"))
203 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
204 (const_string "unknown"))
206 ;; Main data type used by the insn
207 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
208 (const_string "unknown"))
210 ;; True if the main data type is twice the size of a word.
211 (define_attr "dword_mode" "no,yes"
212 (cond [(and (eq_attr "mode" "DI,DF")
213 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
216 (and (eq_attr "mode" "TI,TF")
217 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
218 (const_string "yes")]
219 (const_string "no")))
221 ;; Classification of each insn.
222 ;; branch conditional branch
223 ;; jump unconditional jump
224 ;; call unconditional call
225 ;; load load instruction(s)
226 ;; fpload floating point load
227 ;; fpidxload floating point indexed load
228 ;; store store instruction(s)
229 ;; fpstore floating point store
230 ;; fpidxstore floating point indexed store
231 ;; prefetch memory prefetch (register + offset)
232 ;; prefetchx memory indexed prefetch (register + register)
233 ;; condmove conditional moves
234 ;; mtc transfer to coprocessor
235 ;; mfc transfer from coprocessor
236 ;; mthilo transfer to hi/lo registers
237 ;; mfhilo transfer from hi/lo registers
238 ;; const load constant
239 ;; arith integer arithmetic instructions
240 ;; logical integer logical instructions
241 ;; shift integer shift instructions
242 ;; slt set less than instructions
243 ;; signext sign extend instructions
244 ;; clz the clz and clo instructions
245 ;; pop the pop instruction
246 ;; trap trap if instructions
247 ;; imul integer multiply 2 operands
248 ;; imul3 integer multiply 3 operands
249 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
250 ;; imadd integer multiply-add
251 ;; idiv integer divide 2 operands
252 ;; idiv3 integer divide 3 operands
253 ;; move integer register move ({,D}ADD{,U} with rt = 0)
254 ;; fmove floating point register move
255 ;; fadd floating point add/subtract
256 ;; fmul floating point multiply
257 ;; fmadd floating point multiply-add
258 ;; fdiv floating point divide
259 ;; frdiv floating point reciprocal divide
260 ;; frdiv1 floating point reciprocal divide step 1
261 ;; frdiv2 floating point reciprocal divide step 2
262 ;; fabs floating point absolute value
263 ;; fneg floating point negation
264 ;; fcmp floating point compare
265 ;; fcvt floating point convert
266 ;; fsqrt floating point square root
267 ;; frsqrt floating point reciprocal square root
268 ;; frsqrt1 floating point reciprocal square root step1
269 ;; frsqrt2 floating point reciprocal square root step2
270 ;; multi multiword sequence (or user asm statements)
272 ;; ghost an instruction that produces no real code
274 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
275 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
276 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
277 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
278 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
279 (cond [(eq_attr "jal" "!unset") (const_string "call")
280 (eq_attr "got" "load") (const_string "load")
282 (eq_attr "alu_type" "add,sub") (const_string "arith")
284 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
286 ;; If a doubleword move uses these expensive instructions,
287 ;; it is usually better to schedule them in the same way
288 ;; as the singleword form, rather than as "multi".
289 (eq_attr "move_type" "load") (const_string "load")
290 (eq_attr "move_type" "fpload") (const_string "fpload")
291 (eq_attr "move_type" "store") (const_string "store")
292 (eq_attr "move_type" "fpstore") (const_string "fpstore")
293 (eq_attr "move_type" "mtc") (const_string "mtc")
294 (eq_attr "move_type" "mfc") (const_string "mfc")
295 (eq_attr "move_type" "mthilo") (const_string "mthilo")
296 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
298 ;; These types of move are always single insns.
299 (eq_attr "move_type" "fmove") (const_string "fmove")
300 (eq_attr "move_type" "loadpool") (const_string "load")
301 (eq_attr "move_type" "signext") (const_string "signext")
302 (eq_attr "move_type" "ext_ins") (const_string "arith")
303 (eq_attr "move_type" "arith") (const_string "arith")
304 (eq_attr "move_type" "logical") (const_string "logical")
305 (eq_attr "move_type" "sll0") (const_string "shift")
306 (eq_attr "move_type" "andi") (const_string "logical")
308 ;; These types of move are always split.
309 (eq_attr "move_type" "constN,shift_shift")
310 (const_string "multi")
312 ;; These types of move are split for doubleword modes only.
313 (and (eq_attr "move_type" "move,const")
314 (eq_attr "dword_mode" "yes"))
315 (const_string "multi")
316 (eq_attr "move_type" "move") (const_string "move")
317 (eq_attr "move_type" "const") (const_string "const")]
318 ;; We classify "lui_movf" as "unknown" rather than "multi"
319 ;; because we don't split it. FIXME: we should split instead.
320 (const_string "unknown")))
322 ;; Mode for conversion types (fcvt)
323 ;; I2S integer to float single (SI/DI to SF)
324 ;; I2D integer to float double (SI/DI to DF)
325 ;; S2I float to integer (SF to SI/DI)
326 ;; D2I float to integer (DF to SI/DI)
327 ;; D2S double to float single
328 ;; S2D float single to double
330 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
331 (const_string "unknown"))
333 ;; Is this an extended instruction in mips16 mode?
334 (define_attr "extended_mips16" "no,yes"
335 (if_then_else (ior (eq_attr "move_type" "sll0")
336 (eq_attr "type" "branch")
337 (eq_attr "jal" "direct"))
339 (const_string "no")))
341 ;; Attributes describing a sync loop. These loops have the form:
343 ;; if (RELEASE_BARRIER == YES) sync
345 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
346 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
347 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
348 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
349 ;; $AT |= $TMP1 | $TMP3
350 ;; if (!commit (*MEM = $AT)) goto 1.
351 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
355 ;; where "$" values are temporaries and where the other values are
356 ;; specified by the attributes below. Values are specified as operand
357 ;; numbers and insns are specified as enums. If no operand number is
358 ;; specified, the following values are used instead:
362 ;; - INCLUSIVE_MASK: -1
363 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
364 ;; - EXCLUSIVE_MASK: 0
366 ;; MEM and INSN1_OP2 are required.
368 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
369 ;; but the gen* programs don't yet support that.
370 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
371 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
372 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
373 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
374 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
375 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
376 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
377 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
378 (const_string "move"))
379 (define_attr "sync_insn2" "nop,and,xor,not"
380 (const_string "nop"))
381 (define_attr "sync_release_barrier" "yes,no"
382 (const_string "yes"))
384 ;; Length of instruction in bytes.
385 (define_attr "length" ""
386 (cond [(and (eq_attr "extended_mips16" "yes")
387 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
390 ;; Direct branch instructions have a range of [-0x20000,0x1fffc],
391 ;; relative to the address of the delay slot. If a branch is
392 ;; outside this range, we have a choice of two sequences.
393 ;; For PIC, an out-of-range branch like:
398 ;; becomes the equivalent of:
407 ;; The non-PIC case is similar except that we use a direct
408 ;; jump instead of an la/jr pair. Since the target of this
409 ;; jump is an absolute 28-bit bit address (the other bits
410 ;; coming from the address of the delay slot) this form cannot
411 ;; cross a 256MB boundary. We could provide the option of
412 ;; using la/jr in this case too, but we do not do so at
415 ;; Note that this value does not account for the delay slot
416 ;; instruction, whose length is added separately. If the RTL
417 ;; pattern has no explicit delay slot, mips_adjust_insn_length
418 ;; will add the length of the implicit nop. The values for
419 ;; forward and backward branches will be different as well.
420 (eq_attr "type" "branch")
421 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
422 (le (minus (pc) (match_dup 0)) (const_int 131068)))
425 ;; The non-PIC case: branch, first delay slot, and J.
426 (ne (symbol_ref "TARGET_ABSOLUTE_JUMPS") (const_int 0))
429 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
430 ;; mips_adjust_insn_length substitutes the correct length.
432 ;; Note that we can't simply use (symbol_ref ...) here
433 ;; because genattrtab needs to know the maximum length
435 (const_int MAX_PIC_BRANCH_LENGTH))
437 ;; "Ghost" instructions occupy no space.
438 (eq_attr "type" "ghost")
441 (eq_attr "got" "load")
442 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
445 (eq_attr "got" "xgot_high")
448 ;; In general, constant-pool loads are extended instructions.
449 (eq_attr "move_type" "loadpool")
452 ;; LUI_MOVFs are decomposed into two separate instructions.
453 (eq_attr "move_type" "lui_movf")
456 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
457 ;; They are extended instructions on MIPS16 targets.
458 (eq_attr "move_type" "shift_shift")
459 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
463 ;; Check for doubleword moves that are decomposed into two
465 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
466 (eq_attr "dword_mode" "yes"))
469 ;; Doubleword CONST{,N} moves are split into two word
471 (and (eq_attr "move_type" "const,constN")
472 (eq_attr "dword_mode" "yes"))
473 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
475 ;; Otherwise, constants, loads and stores are handled by external
477 (eq_attr "move_type" "const,constN")
478 (symbol_ref "mips_const_insns (operands[1]) * 4")
479 (eq_attr "move_type" "load,fpload")
480 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
481 (eq_attr "move_type" "store,fpstore")
482 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
484 ;; In the worst case, a call macro will take 8 instructions:
486 ;; lui $25,%call_hi(FOO)
488 ;; lw $25,%call_lo(FOO)($25)
494 (eq_attr "jal_macro" "yes")
497 ;; Various VR4120 errata require a nop to be inserted after a macc
498 ;; instruction. The assembler does this for us, so account for
499 ;; the worst-case length here.
500 (and (eq_attr "type" "imadd")
501 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
504 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
505 ;; the result of the second one is missed. The assembler should work
506 ;; around this by inserting a nop after the first dmult.
507 (and (eq_attr "type" "imul,imul3")
508 (and (eq_attr "mode" "DI")
509 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
512 (eq_attr "type" "idiv,idiv3")
513 (symbol_ref "mips_idiv_insns () * 4")
515 (not (eq_attr "sync_mem" "none"))
516 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
519 ;; Attribute describing the processor.
520 (define_enum_attr "cpu" "processor"
521 (const (symbol_ref "mips_tune")))
523 ;; The type of hardware hazard associated with this instruction.
524 ;; DELAY means that the next instruction cannot read the result
525 ;; of this one. HILO means that the next two instructions cannot
526 ;; write to HI or LO.
527 (define_attr "hazard" "none,delay,hilo"
528 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
529 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
530 (const_string "delay")
532 (and (eq_attr "type" "mfc,mtc")
533 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
534 (const_string "delay")
536 (and (eq_attr "type" "fcmp")
537 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
538 (const_string "delay")
540 ;; The r4000 multiplication patterns include an mflo instruction.
541 (and (eq_attr "type" "imul")
542 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
543 (const_string "hilo")
545 (and (eq_attr "type" "mfhilo")
546 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
547 (const_string "hilo")]
548 (const_string "none")))
550 ;; Is it a single instruction?
551 (define_attr "single_insn" "no,yes"
552 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
553 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
555 ;; Can the instruction be put into a delay slot?
556 (define_attr "can_delay" "no,yes"
557 (if_then_else (and (eq_attr "type" "!branch,call,jump")
558 (and (eq_attr "hazard" "none")
559 (eq_attr "single_insn" "yes")))
561 (const_string "no")))
563 ;; Attribute defining whether or not we can use the branch-likely
565 (define_attr "branch_likely" "no,yes"
566 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
568 (const_string "no")))
570 ;; True if an instruction might assign to hi or lo when reloaded.
571 ;; This is used by the TUNE_MACC_CHAINS code.
572 (define_attr "may_clobber_hilo" "no,yes"
573 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
575 (const_string "no")))
577 ;; Describe a user's asm statement.
578 (define_asm_attributes
579 [(set_attr "type" "multi")
580 (set_attr "can_delay" "no")])
582 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
583 ;; from the same template.
584 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
586 ;; A copy of GPR that can be used when a pattern has two independent
588 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
590 ;; This mode iterator allows :HILO to be used as the mode of the
591 ;; concatenated HI and LO registers.
592 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
594 ;; This mode iterator allows :P to be used for patterns that operate on
595 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
596 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
598 ;; This mode iterator allows :MOVECC to be used anywhere that a
599 ;; conditional-move-type condition is needed.
600 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
601 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
603 ;; 32-bit integer moves for which we provide move patterns.
604 (define_mode_iterator IMOVE32
613 (V4UQQ "TARGET_DSP")])
615 ;; 64-bit modes for which we provide move patterns.
616 (define_mode_iterator MOVE64
618 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
619 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
620 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
621 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
623 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
624 (define_mode_iterator MOVE128 [TI TF])
626 ;; This mode iterator allows the QI and HI extension patterns to be
627 ;; defined from the same template.
628 (define_mode_iterator SHORT [QI HI])
630 ;; Likewise the 64-bit truncate-and-shift patterns.
631 (define_mode_iterator SUBDI [QI HI SI])
633 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
634 ;; floating-point mode is allowed.
635 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
636 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
637 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
639 ;; Like ANYF, but only applies to scalar modes.
640 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
641 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
643 ;; A floating-point mode for which moves involving FPRs may need to be split.
644 (define_mode_iterator SPLITF
645 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
646 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
647 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
648 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
649 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
650 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
651 (TF "TARGET_64BIT && TARGET_FLOAT64")])
653 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
654 ;; 32-bit version and "dsubu" in the 64-bit version.
655 (define_mode_attr d [(SI "") (DI "d")
656 (QQ "") (HQ "") (SQ "") (DQ "d")
657 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
658 (HA "") (SA "") (DA "d")
659 (UHA "") (USA "") (UDA "d")])
661 ;; Same as d but upper-case.
662 (define_mode_attr D [(SI "") (DI "D")
663 (QQ "") (HQ "") (SQ "") (DQ "D")
664 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
665 (HA "") (SA "") (DA "D")
666 (UHA "") (USA "") (UDA "D")])
668 ;; This attribute gives the length suffix for a sign- or zero-extension
670 (define_mode_attr size [(QI "b") (HI "h")])
672 ;; This attributes gives the mode mask of a SHORT.
673 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
675 ;; Mode attributes for GPR loads.
676 (define_mode_attr load [(SI "lw") (DI "ld")])
677 ;; Instruction names for stores.
678 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
680 ;; Similarly for MIPS IV indexed FPR loads and stores.
681 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
682 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
684 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
685 ;; are different. Some forms of unextended addiu have an 8-bit immediate
686 ;; field but the equivalent daddiu has only a 5-bit field.
687 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
689 ;; This attribute gives the best constraint to use for registers of
691 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
693 ;; This attribute gives the format suffix for floating-point operations.
694 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
696 ;; This attribute gives the upper-case mode name for one unit of a
697 ;; floating-point mode.
698 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
700 ;; This attribute gives the integer mode that has the same size as a
702 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
703 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
704 (HA "HI") (SA "SI") (DA "DI")
705 (UHA "HI") (USA "SI") (UDA "DI")
706 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
707 (V2HQ "SI") (V2HA "SI")])
709 ;; This attribute gives the integer mode that has half the size of
710 ;; the controlling mode.
711 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
712 (V2SI "SI") (V4HI "SI") (V8QI "SI")
715 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
717 ;; In certain cases, div.s and div.ps may have a rounding error
718 ;; and/or wrong inexact flag.
720 ;; Therefore, we only allow div.s if not working around SB-1 rev2
721 ;; errata or if a slight loss of precision is OK.
722 (define_mode_attr divide_condition
723 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
724 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
726 ;; This attribute gives the conditions under which SQRT.fmt instructions
728 (define_mode_attr sqrt_condition
729 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
731 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
732 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
733 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
734 ;; so for safety's sake, we apply this restriction to all targets.
735 (define_mode_attr recip_condition
737 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
738 (V2SF "TARGET_SB1")])
740 ;; This code iterator allows signed and unsigned widening multiplications
741 ;; to use the same template.
742 (define_code_iterator any_extend [sign_extend zero_extend])
744 ;; This code iterator allows the two right shift instructions to be
745 ;; generated from the same template.
746 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
748 ;; This code iterator allows the three shift instructions to be generated
749 ;; from the same template.
750 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
752 ;; This code iterator allows unsigned and signed division to be generated
753 ;; from the same template.
754 (define_code_iterator any_div [div udiv])
756 ;; This code iterator allows unsigned and signed modulus to be generated
757 ;; from the same template.
758 (define_code_iterator any_mod [mod umod])
760 ;; This code iterator allows all native floating-point comparisons to be
761 ;; generated from the same template.
762 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
764 ;; This code iterator is used for comparisons that can be implemented
765 ;; by swapping the operands.
766 (define_code_iterator swapped_fcond [ge gt unge ungt])
768 ;; Equality operators.
769 (define_code_iterator equality_op [eq ne])
771 ;; These code iterators allow the signed and unsigned scc operations to use
772 ;; the same template.
773 (define_code_iterator any_gt [gt gtu])
774 (define_code_iterator any_ge [ge geu])
775 (define_code_iterator any_lt [lt ltu])
776 (define_code_iterator any_le [le leu])
778 ;; <u> expands to an empty string when doing a signed operation and
779 ;; "u" when doing an unsigned operation.
780 (define_code_attr u [(sign_extend "") (zero_extend "u")
788 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
789 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
791 ;; <optab> expands to the name of the optab for a particular code.
792 (define_code_attr optab [(ashift "ashl")
801 ;; <insn> expands to the name of the insn that implements a particular code.
802 (define_code_attr insn [(ashift "sll")
811 ;; <immediate_insn> expands to the name of the insn that implements
812 ;; a particular code to operate on immediate values.
813 (define_code_attr immediate_insn [(ior "ori")
817 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
818 (define_code_attr fcond [(unordered "un")
826 ;; Similar, but for swapped conditions.
827 (define_code_attr swapped_fcond [(ge "le")
832 ;; The value of the bit when the branch is taken for branch_bit patterns.
833 ;; Comparison is always against zero so this depends on the operator.
834 (define_code_attr bbv [(eq "0") (ne "1")])
836 ;; This is the inverse value of bbv.
837 (define_code_attr bbinv [(eq "1") (ne "0")])
839 ;; .........................
841 ;; Branch, call and jump delay slots
843 ;; .........................
845 (define_delay (and (eq_attr "type" "branch")
846 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
847 (eq_attr "branch_likely" "yes"))
848 [(eq_attr "can_delay" "yes")
850 (eq_attr "can_delay" "yes")])
852 ;; Branches that don't have likely variants do not annul on false.
853 (define_delay (and (eq_attr "type" "branch")
854 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
855 (eq_attr "branch_likely" "no"))
856 [(eq_attr "can_delay" "yes")
860 (define_delay (eq_attr "type" "jump")
861 [(eq_attr "can_delay" "yes")
865 (define_delay (and (eq_attr "type" "call")
866 (eq_attr "jal_macro" "no"))
867 [(eq_attr "can_delay" "yes")
871 ;; Pipeline descriptions.
873 ;; generic.md provides a fallback for processors without a specific
874 ;; pipeline description. It is derived from the old define_function_unit
875 ;; version and uses the "alu" and "imuldiv" units declared below.
877 ;; Some of the processor-specific files are also derived from old
878 ;; define_function_unit descriptions and simply override the parts of
879 ;; generic.md that don't apply. The other processor-specific files
880 ;; are self-contained.
881 (define_automaton "alu,imuldiv")
883 (define_cpu_unit "alu" "alu")
884 (define_cpu_unit "imuldiv" "imuldiv")
886 ;; Ghost instructions produce no real code and introduce no hazards.
887 ;; They exist purely to express an effect on dataflow.
888 (define_insn_reservation "ghost" 0
889 (eq_attr "type" "ghost")
910 (include "loongson2ef.md")
911 (include "octeon.md")
915 (include "generic.md")
918 ;; ....................
922 ;; ....................
926 [(trap_if (const_int 1) (const_int 0))]
929 if (ISA_HAS_COND_TRAP)
931 else if (TARGET_MIPS16)
936 [(set_attr "type" "trap")])
938 (define_expand "ctrap<mode>4"
939 [(trap_if (match_operator 0 "comparison_operator"
940 [(match_operand:GPR 1 "reg_or_0_operand")
941 (match_operand:GPR 2 "arith_operand")])
942 (match_operand 3 "const_0_operand"))]
945 mips_expand_conditional_trap (operands[0]);
949 (define_insn "*conditional_trap<mode>"
950 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
951 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
952 (match_operand:GPR 2 "arith_operand" "dI")])
956 [(set_attr "type" "trap")])
959 ;; ....................
963 ;; ....................
966 (define_insn "add<mode>3"
967 [(set (match_operand:ANYF 0 "register_operand" "=f")
968 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
969 (match_operand:ANYF 2 "register_operand" "f")))]
971 "add.<fmt>\t%0,%1,%2"
972 [(set_attr "type" "fadd")
973 (set_attr "mode" "<UNITMODE>")])
975 (define_expand "add<mode>3"
976 [(set (match_operand:GPR 0 "register_operand")
977 (plus:GPR (match_operand:GPR 1 "register_operand")
978 (match_operand:GPR 2 "arith_operand")))]
981 (define_insn "*add<mode>3"
982 [(set (match_operand:GPR 0 "register_operand" "=d,d")
983 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
984 (match_operand:GPR 2 "arith_operand" "d,Q")))]
989 [(set_attr "alu_type" "add")
990 (set_attr "mode" "<MODE>")])
992 (define_insn "*add<mode>3_mips16"
993 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
994 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
995 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1003 [(set_attr "alu_type" "add")
1004 (set_attr "mode" "<MODE>")
1005 (set_attr_alternative "length"
1006 [(if_then_else (match_operand 2 "m16_simm8_8")
1009 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1012 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1015 (if_then_else (match_operand 2 "m16_simm4_1")
1020 ;; On the mips16, we can sometimes split an add of a constant which is
1021 ;; a 4 byte instruction into two adds which are both 2 byte
1022 ;; instructions. There are two cases: one where we are adding a
1023 ;; constant plus a register to another register, and one where we are
1024 ;; simply adding a constant to a register.
1027 [(set (match_operand:SI 0 "d_operand")
1028 (plus:SI (match_dup 0)
1029 (match_operand:SI 1 "const_int_operand")))]
1030 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1031 && ((INTVAL (operands[1]) > 0x7f
1032 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1033 || (INTVAL (operands[1]) < - 0x80
1034 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1035 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1036 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1038 HOST_WIDE_INT val = INTVAL (operands[1]);
1042 operands[1] = GEN_INT (0x7f);
1043 operands[2] = GEN_INT (val - 0x7f);
1047 operands[1] = GEN_INT (- 0x80);
1048 operands[2] = GEN_INT (val + 0x80);
1053 [(set (match_operand:SI 0 "d_operand")
1054 (plus:SI (match_operand:SI 1 "d_operand")
1055 (match_operand:SI 2 "const_int_operand")))]
1056 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1057 && REGNO (operands[0]) != REGNO (operands[1])
1058 && ((INTVAL (operands[2]) > 0x7
1059 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1060 || (INTVAL (operands[2]) < - 0x8
1061 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1062 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1063 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1065 HOST_WIDE_INT val = INTVAL (operands[2]);
1069 operands[2] = GEN_INT (0x7);
1070 operands[3] = GEN_INT (val - 0x7);
1074 operands[2] = GEN_INT (- 0x8);
1075 operands[3] = GEN_INT (val + 0x8);
1080 [(set (match_operand:DI 0 "d_operand")
1081 (plus:DI (match_dup 0)
1082 (match_operand:DI 1 "const_int_operand")))]
1083 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1084 && ((INTVAL (operands[1]) > 0xf
1085 && INTVAL (operands[1]) <= 0xf + 0xf)
1086 || (INTVAL (operands[1]) < - 0x10
1087 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1088 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1089 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1091 HOST_WIDE_INT val = INTVAL (operands[1]);
1095 operands[1] = GEN_INT (0xf);
1096 operands[2] = GEN_INT (val - 0xf);
1100 operands[1] = GEN_INT (- 0x10);
1101 operands[2] = GEN_INT (val + 0x10);
1106 [(set (match_operand:DI 0 "d_operand")
1107 (plus:DI (match_operand:DI 1 "d_operand")
1108 (match_operand:DI 2 "const_int_operand")))]
1109 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1110 && REGNO (operands[0]) != REGNO (operands[1])
1111 && ((INTVAL (operands[2]) > 0x7
1112 && INTVAL (operands[2]) <= 0x7 + 0xf)
1113 || (INTVAL (operands[2]) < - 0x8
1114 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1115 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1116 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1118 HOST_WIDE_INT val = INTVAL (operands[2]);
1122 operands[2] = GEN_INT (0x7);
1123 operands[3] = GEN_INT (val - 0x7);
1127 operands[2] = GEN_INT (- 0x8);
1128 operands[3] = GEN_INT (val + 0x8);
1132 (define_insn "*addsi3_extended"
1133 [(set (match_operand:DI 0 "register_operand" "=d,d")
1135 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1136 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1137 "TARGET_64BIT && !TARGET_MIPS16"
1141 [(set_attr "alu_type" "add")
1142 (set_attr "mode" "SI")])
1144 ;; Split this insn so that the addiu splitters can have a crack at it.
1145 ;; Use a conservative length estimate until the split.
1146 (define_insn_and_split "*addsi3_extended_mips16"
1147 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1149 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1150 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1151 "TARGET_64BIT && TARGET_MIPS16"
1153 "&& reload_completed"
1154 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1155 { operands[3] = gen_lowpart (SImode, operands[0]); }
1156 [(set_attr "alu_type" "add")
1157 (set_attr "mode" "SI")
1158 (set_attr "extended_mips16" "yes")])
1160 ;; Combiner patterns for unsigned byte-add.
1162 (define_insn "*baddu_si_eb"
1163 [(set (match_operand:SI 0 "register_operand" "=d")
1166 (plus:SI (match_operand:SI 1 "register_operand" "d")
1167 (match_operand:SI 2 "register_operand" "d")) 3)))]
1168 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1170 [(set_attr "alu_type" "add")])
1172 (define_insn "*baddu_si_el"
1173 [(set (match_operand:SI 0 "register_operand" "=d")
1176 (plus:SI (match_operand:SI 1 "register_operand" "d")
1177 (match_operand:SI 2 "register_operand" "d")) 0)))]
1178 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1180 [(set_attr "alu_type" "add")])
1182 (define_insn "*baddu_di<mode>"
1183 [(set (match_operand:GPR 0 "register_operand" "=d")
1186 (plus:DI (match_operand:DI 1 "register_operand" "d")
1187 (match_operand:DI 2 "register_operand" "d")))))]
1188 "ISA_HAS_BADDU && TARGET_64BIT"
1190 [(set_attr "alu_type" "add")])
1193 ;; ....................
1197 ;; ....................
1200 (define_insn "sub<mode>3"
1201 [(set (match_operand:ANYF 0 "register_operand" "=f")
1202 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1203 (match_operand:ANYF 2 "register_operand" "f")))]
1205 "sub.<fmt>\t%0,%1,%2"
1206 [(set_attr "type" "fadd")
1207 (set_attr "mode" "<UNITMODE>")])
1209 (define_insn "sub<mode>3"
1210 [(set (match_operand:GPR 0 "register_operand" "=d")
1211 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1212 (match_operand:GPR 2 "register_operand" "d")))]
1215 [(set_attr "alu_type" "sub")
1216 (set_attr "mode" "<MODE>")])
1218 (define_insn "*subsi3_extended"
1219 [(set (match_operand:DI 0 "register_operand" "=d")
1221 (minus:SI (match_operand:SI 1 "register_operand" "d")
1222 (match_operand:SI 2 "register_operand" "d"))))]
1225 [(set_attr "alu_type" "sub")
1226 (set_attr "mode" "DI")])
1229 ;; ....................
1233 ;; ....................
1236 (define_expand "mul<mode>3"
1237 [(set (match_operand:SCALARF 0 "register_operand")
1238 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1239 (match_operand:SCALARF 2 "register_operand")))]
1243 (define_insn "*mul<mode>3"
1244 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1245 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1246 (match_operand:SCALARF 2 "register_operand" "f")))]
1247 "!TARGET_4300_MUL_FIX"
1248 "mul.<fmt>\t%0,%1,%2"
1249 [(set_attr "type" "fmul")
1250 (set_attr "mode" "<MODE>")])
1252 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1253 ;; operands may corrupt immediately following multiplies. This is a
1254 ;; simple fix to insert NOPs.
1256 (define_insn "*mul<mode>3_r4300"
1257 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1258 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1259 (match_operand:SCALARF 2 "register_operand" "f")))]
1260 "TARGET_4300_MUL_FIX"
1261 "mul.<fmt>\t%0,%1,%2\;nop"
1262 [(set_attr "type" "fmul")
1263 (set_attr "mode" "<MODE>")
1264 (set_attr "length" "8")])
1266 (define_insn "mulv2sf3"
1267 [(set (match_operand:V2SF 0 "register_operand" "=f")
1268 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1269 (match_operand:V2SF 2 "register_operand" "f")))]
1270 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1272 [(set_attr "type" "fmul")
1273 (set_attr "mode" "SF")])
1275 ;; The original R4000 has a cpu bug. If a double-word or a variable
1276 ;; shift executes while an integer multiplication is in progress, the
1277 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1278 ;; with the mult on the R4000.
1280 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1281 ;; (also valid for MIPS R4000MC processors):
1283 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1284 ;; this errata description.
1285 ;; The following code sequence causes the R4000 to incorrectly
1286 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1287 ;; instruction. If the dsra32 instruction is executed during an
1288 ;; integer multiply, the dsra32 will only shift by the amount in
1289 ;; specified in the instruction rather than the amount plus 32
1291 ;; instruction 1: mult rs,rt integer multiply
1292 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1293 ;; right arithmetic + 32
1294 ;; Workaround: A dsra32 instruction placed after an integer
1295 ;; multiply should not be one of the 11 instructions after the
1296 ;; multiply instruction."
1300 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1301 ;; the following description.
1302 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1303 ;; 64-bit versions) may produce incorrect results under the
1304 ;; following conditions:
1305 ;; 1) An integer multiply is currently executing
1306 ;; 2) These types of shift instructions are executed immediately
1307 ;; following an integer divide instruction.
1309 ;; 1) Make sure no integer multiply is running wihen these
1310 ;; instruction are executed. If this cannot be predicted at
1311 ;; compile time, then insert a "mfhi" to R0 instruction
1312 ;; immediately after the integer multiply instruction. This
1313 ;; will cause the integer multiply to complete before the shift
1315 ;; 2) Separate integer divide and these two classes of shift
1316 ;; instructions by another instruction or a noop."
1318 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1321 (define_expand "mul<mode>3"
1322 [(set (match_operand:GPR 0 "register_operand")
1323 (mult:GPR (match_operand:GPR 1 "register_operand")
1324 (match_operand:GPR 2 "register_operand")))]
1327 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1328 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1330 else if (ISA_HAS_<D>MUL3)
1331 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1332 else if (TARGET_FIX_R4000)
1333 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1336 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1340 (define_insn "mul<mode>3_mul3_loongson"
1341 [(set (match_operand:GPR 0 "register_operand" "=d")
1342 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1343 (match_operand:GPR 2 "register_operand" "d")))]
1344 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1346 if (TARGET_LOONGSON_2EF)
1347 return "<d>multu.g\t%0,%1,%2";
1349 return "gs<d>multu\t%0,%1,%2";
1351 [(set_attr "type" "imul3nc")
1352 (set_attr "mode" "<MODE>")])
1354 (define_insn "mul<mode>3_mul3"
1355 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1356 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1357 (match_operand:GPR 2 "register_operand" "d,d")))
1358 (clobber (match_scratch:GPR 3 "=l,X"))]
1361 if (which_alternative == 1)
1362 return "<d>mult\t%1,%2";
1363 if (<MODE>mode == SImode && TARGET_MIPS3900)
1364 return "mult\t%0,%1,%2";
1365 return "<d>mul\t%0,%1,%2";
1367 [(set_attr "type" "imul3,imul")
1368 (set_attr "mode" "<MODE>")])
1370 ;; If a register gets allocated to LO, and we spill to memory, the reload
1371 ;; will include a move from LO to a GPR. Merge it into the multiplication
1372 ;; if it can set the GPR directly.
1375 ;; Operand 1: GPR (1st multiplication operand)
1376 ;; Operand 2: GPR (2nd multiplication operand)
1377 ;; Operand 3: GPR (destination)
1380 [(set (match_operand:SI 0 "lo_operand")
1381 (mult:SI (match_operand:SI 1 "d_operand")
1382 (match_operand:SI 2 "d_operand")))
1383 (clobber (scratch:SI))])
1384 (set (match_operand:SI 3 "d_operand")
1386 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1389 (mult:SI (match_dup 1)
1391 (clobber (match_dup 0))])])
1393 (define_insn "mul<mode>3_internal"
1394 [(set (match_operand:GPR 0 "register_operand" "=l")
1395 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1396 (match_operand:GPR 2 "register_operand" "d")))]
1399 [(set_attr "type" "imul")
1400 (set_attr "mode" "<MODE>")])
1402 (define_insn "mul<mode>3_r4000"
1403 [(set (match_operand:GPR 0 "register_operand" "=d")
1404 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1405 (match_operand:GPR 2 "register_operand" "d")))
1406 (clobber (match_scratch:GPR 3 "=l"))]
1408 "<d>mult\t%1,%2\;mflo\t%0"
1409 [(set_attr "type" "imul")
1410 (set_attr "mode" "<MODE>")
1411 (set_attr "length" "8")])
1413 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1414 ;; of "mult; mflo". They have the same latency, but the first form gives
1415 ;; us an extra cycle to compute the operands.
1418 ;; Operand 1: GPR (1st multiplication operand)
1419 ;; Operand 2: GPR (2nd multiplication operand)
1420 ;; Operand 3: GPR (destination)
1422 [(set (match_operand:SI 0 "lo_operand")
1423 (mult:SI (match_operand:SI 1 "d_operand")
1424 (match_operand:SI 2 "d_operand")))
1425 (set (match_operand:SI 3 "d_operand")
1427 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1432 (plus:SI (mult:SI (match_dup 1)
1436 (plus:SI (mult:SI (match_dup 1)
1440 ;; Multiply-accumulate patterns
1442 ;; This pattern is first matched by combine, which tries to use the
1443 ;; pattern wherever it can. We don't know until later whether it
1444 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1445 ;; so we need to keep both options open.
1447 ;; The second alternative has a "?" marker because it is generally
1448 ;; one instruction more costly than the first alternative. This "?"
1449 ;; marker is enough to convey the relative costs to the register
1452 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1453 ;; reloads of the other operands, even though operands 4 and 5 need no
1454 ;; copy instructions. Reload therefore thinks that the second alternative
1455 ;; is two reloads more costly than the first. We add "*?*?" to the first
1456 ;; alternative as a counterweight.
1457 (define_insn "*mul_acc_si"
1458 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1459 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1460 (match_operand:SI 2 "register_operand" "d,d"))
1461 (match_operand:SI 3 "register_operand" "0,d")))
1462 (clobber (match_scratch:SI 4 "=X,l"))
1463 (clobber (match_scratch:SI 5 "=X,&d"))]
1464 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1468 [(set_attr "type" "imadd")
1469 (set_attr "mode" "SI")
1470 (set_attr "length" "4,8")])
1472 ;; The same idea applies here. The middle alternative needs one less
1473 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1474 (define_insn "*mul_acc_si_r3900"
1475 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1476 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1477 (match_operand:SI 2 "register_operand" "d,d,d"))
1478 (match_operand:SI 3 "register_operand" "0,l,d")))
1479 (clobber (match_scratch:SI 4 "=X,3,l"))
1480 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1481 "TARGET_MIPS3900 && !TARGET_MIPS16"
1486 [(set_attr "type" "imadd")
1487 (set_attr "mode" "SI")
1488 (set_attr "length" "4,4,8")])
1490 ;; Split *mul_acc_si if both the source and destination accumulator
1493 [(set (match_operand:SI 0 "d_operand")
1494 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1495 (match_operand:SI 2 "d_operand"))
1496 (match_operand:SI 3 "d_operand")))
1497 (clobber (match_operand:SI 4 "lo_operand"))
1498 (clobber (match_operand:SI 5 "d_operand"))]
1500 [(parallel [(set (match_dup 5)
1501 (mult:SI (match_dup 1) (match_dup 2)))
1502 (clobber (match_dup 4))])
1503 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1506 (define_insn "*macc"
1507 [(set (match_operand:SI 0 "register_operand" "=l,d")
1508 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1509 (match_operand:SI 2 "register_operand" "d,d"))
1510 (match_operand:SI 3 "register_operand" "0,l")))
1511 (clobber (match_scratch:SI 4 "=X,3"))]
1514 if (which_alternative == 1)
1515 return "macc\t%0,%1,%2";
1516 else if (TARGET_MIPS5500)
1517 return "madd\t%1,%2";
1519 /* The VR4130 assumes that there is a two-cycle latency between a macc
1520 that "writes" to $0 and an instruction that reads from it. We avoid
1521 this by assigning to $1 instead. */
1522 return "%[macc\t%@,%1,%2%]";
1524 [(set_attr "type" "imadd")
1525 (set_attr "mode" "SI")])
1527 (define_insn "*msac"
1528 [(set (match_operand:SI 0 "register_operand" "=l,d")
1529 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1530 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1531 (match_operand:SI 3 "register_operand" "d,d"))))
1532 (clobber (match_scratch:SI 4 "=X,1"))]
1535 if (which_alternative == 1)
1536 return "msac\t%0,%2,%3";
1537 else if (TARGET_MIPS5500)
1538 return "msub\t%2,%3";
1540 return "msac\t$0,%2,%3";
1542 [(set_attr "type" "imadd")
1543 (set_attr "mode" "SI")])
1545 ;; An msac-like instruction implemented using negation and a macc.
1546 (define_insn_and_split "*msac_using_macc"
1547 [(set (match_operand:SI 0 "register_operand" "=l,d")
1548 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1549 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1550 (match_operand:SI 3 "register_operand" "d,d"))))
1551 (clobber (match_scratch:SI 4 "=X,1"))
1552 (clobber (match_scratch:SI 5 "=d,d"))]
1553 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1555 "&& reload_completed"
1557 (neg:SI (match_dup 3)))
1560 (plus:SI (mult:SI (match_dup 2)
1563 (clobber (match_dup 4))])]
1565 [(set_attr "type" "imadd")
1566 (set_attr "length" "8")])
1568 ;; Patterns generated by the define_peephole2 below.
1570 (define_insn "*macc2"
1571 [(set (match_operand:SI 0 "register_operand" "=l")
1572 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1573 (match_operand:SI 2 "register_operand" "d"))
1575 (set (match_operand:SI 3 "register_operand" "=d")
1576 (plus:SI (mult:SI (match_dup 1)
1579 "ISA_HAS_MACC && reload_completed"
1581 [(set_attr "type" "imadd")
1582 (set_attr "mode" "SI")])
1584 (define_insn "*msac2"
1585 [(set (match_operand:SI 0 "register_operand" "=l")
1586 (minus:SI (match_dup 0)
1587 (mult:SI (match_operand:SI 1 "register_operand" "d")
1588 (match_operand:SI 2 "register_operand" "d"))))
1589 (set (match_operand:SI 3 "register_operand" "=d")
1590 (minus:SI (match_dup 0)
1591 (mult:SI (match_dup 1)
1593 "ISA_HAS_MSAC && reload_completed"
1595 [(set_attr "type" "imadd")
1596 (set_attr "mode" "SI")])
1598 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1602 ;; Operand 1: macc/msac
1603 ;; Operand 2: GPR (destination)
1606 [(set (match_operand:SI 0 "lo_operand")
1607 (match_operand:SI 1 "macc_msac_operand"))
1608 (clobber (scratch:SI))])
1609 (set (match_operand:SI 2 "d_operand")
1612 [(parallel [(set (match_dup 0)
1617 ;; When we have a three-address multiplication instruction, it should
1618 ;; be faster to do a separate multiply and add, rather than moving
1619 ;; something into LO in order to use a macc instruction.
1621 ;; This peephole needs a scratch register to cater for the case when one
1622 ;; of the multiplication operands is the same as the destination.
1624 ;; Operand 0: GPR (scratch)
1626 ;; Operand 2: GPR (addend)
1627 ;; Operand 3: GPR (destination)
1628 ;; Operand 4: macc/msac
1629 ;; Operand 5: new multiplication
1630 ;; Operand 6: new addition/subtraction
1632 [(match_scratch:SI 0 "d")
1633 (set (match_operand:SI 1 "lo_operand")
1634 (match_operand:SI 2 "d_operand"))
1637 [(set (match_operand:SI 3 "d_operand")
1638 (match_operand:SI 4 "macc_msac_operand"))
1639 (clobber (match_dup 1))])]
1640 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1641 [(parallel [(set (match_dup 0)
1643 (clobber (match_dup 1))])
1647 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1648 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1649 operands[2], operands[0]);
1652 ;; Same as above, except LO is the initial target of the macc.
1654 ;; Operand 0: GPR (scratch)
1656 ;; Operand 2: GPR (addend)
1657 ;; Operand 3: macc/msac
1658 ;; Operand 4: GPR (destination)
1659 ;; Operand 5: new multiplication
1660 ;; Operand 6: new addition/subtraction
1662 [(match_scratch:SI 0 "d")
1663 (set (match_operand:SI 1 "lo_operand")
1664 (match_operand:SI 2 "d_operand"))
1668 (match_operand:SI 3 "macc_msac_operand"))
1669 (clobber (scratch:SI))])
1671 (set (match_operand:SI 4 "d_operand")
1673 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1674 [(parallel [(set (match_dup 0)
1676 (clobber (match_dup 1))])
1680 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1681 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1682 operands[2], operands[0]);
1685 ;; See the comment above *mul_add_si for details.
1686 (define_insn "*mul_sub_si"
1687 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1688 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1689 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1690 (match_operand:SI 3 "register_operand" "d,d"))))
1691 (clobber (match_scratch:SI 4 "=X,l"))
1692 (clobber (match_scratch:SI 5 "=X,&d"))]
1693 "GENERATE_MADD_MSUB"
1697 [(set_attr "type" "imadd")
1698 (set_attr "mode" "SI")
1699 (set_attr "length" "4,8")])
1701 ;; Split *mul_sub_si if both the source and destination accumulator
1704 [(set (match_operand:SI 0 "d_operand")
1705 (minus:SI (match_operand:SI 1 "d_operand")
1706 (mult:SI (match_operand:SI 2 "d_operand")
1707 (match_operand:SI 3 "d_operand"))))
1708 (clobber (match_operand:SI 4 "lo_operand"))
1709 (clobber (match_operand:SI 5 "d_operand"))]
1711 [(parallel [(set (match_dup 5)
1712 (mult:SI (match_dup 2) (match_dup 3)))
1713 (clobber (match_dup 4))])
1714 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1717 (define_insn "*muls"
1718 [(set (match_operand:SI 0 "register_operand" "=l,d")
1719 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1720 (match_operand:SI 2 "register_operand" "d,d"))))
1721 (clobber (match_scratch:SI 3 "=X,l"))]
1726 [(set_attr "type" "imul,imul3")
1727 (set_attr "mode" "SI")])
1729 (define_expand "<u>mulsidi3"
1730 [(set (match_operand:DI 0 "register_operand")
1731 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1732 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1733 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1735 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1736 emit_insn (fn (operands[0], operands[1], operands[2]));
1740 ;; As well as being named patterns, these instructions are used by the
1741 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1742 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1743 (define_insn "<u>mulsidi3_32bit"
1744 [(set (match_operand:DI 0 "register_operand" "=ka")
1745 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1746 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1747 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1749 if (ISA_HAS_DSP_MULT)
1750 return "mult<u>\t%q0,%1,%2";
1752 return "mult<u>\t%1,%2";
1754 [(set_attr "type" "imul")
1755 (set_attr "mode" "SI")])
1757 (define_insn "<u>mulsidi3_32bit_r4000"
1758 [(set (match_operand:DI 0 "register_operand" "=d")
1759 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1760 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1761 (clobber (match_scratch:DI 3 "=x"))]
1762 "!TARGET_64BIT && TARGET_FIX_R4000"
1763 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1764 [(set_attr "type" "imul")
1765 (set_attr "mode" "SI")
1766 (set_attr "length" "12")])
1768 (define_insn "<u>mulsidi3_64bit"
1769 [(set (match_operand:DI 0 "register_operand" "=d")
1770 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1771 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1772 (clobber (match_scratch:TI 3 "=x"))
1773 (clobber (match_scratch:DI 4 "=d"))]
1774 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3"
1776 [(set_attr "type" "imul")
1777 (set_attr "mode" "SI")
1778 (set (attr "length")
1779 (if_then_else (ne (symbol_ref "ISA_HAS_EXT_INS") (const_int 0))
1784 [(set (match_operand:DI 0 "d_operand")
1785 (mult:DI (any_extend:DI (match_operand:SI 1 "d_operand"))
1786 (any_extend:DI (match_operand:SI 2 "d_operand"))))
1787 (clobber (match_operand:TI 3 "hilo_operand"))
1788 (clobber (match_operand:DI 4 "d_operand"))]
1789 "TARGET_64BIT && !TARGET_FIX_R4000 && ISA_HAS_EXT_INS && reload_completed"
1791 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1792 (any_extend:DI (match_dup 2)))]
1795 ;; OP0 <- LO, OP4 <- HI
1796 (set (match_dup 0) (match_dup 5))
1797 (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1799 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 32))
1801 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); })
1804 [(set (match_operand:DI 0 "d_operand")
1805 (mult:DI (any_extend:DI (match_operand:SI 1 "d_operand"))
1806 (any_extend:DI (match_operand:SI 2 "d_operand"))))
1807 (clobber (match_operand:TI 3 "hilo_operand"))
1808 (clobber (match_operand:DI 4 "d_operand"))]
1809 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_EXT_INS && reload_completed"
1811 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1812 (any_extend:DI (match_dup 2)))]
1815 ;; OP0 <- LO, OP4 <- HI
1816 (set (match_dup 0) (match_dup 5))
1817 (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1821 (ashift:DI (match_dup 0)
1824 (lshiftrt:DI (match_dup 0)
1827 ;; Shift OP4 into place.
1829 (ashift:DI (match_dup 4)
1832 ;; OR the two halves together
1834 (ior:DI (match_dup 0)
1836 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); })
1838 (define_insn "<u>mulsidi3_64bit_hilo"
1839 [(set (match_operand:TI 0 "register_operand" "=x")
1842 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1843 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1845 "TARGET_64BIT && !TARGET_FIX_R4000"
1847 [(set_attr "type" "imul")
1848 (set_attr "mode" "SI")])
1850 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
1851 (define_insn "mulsidi3_64bit_dmul"
1852 [(set (match_operand:DI 0 "register_operand" "=d")
1853 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1854 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1855 (clobber (match_scratch:DI 3 "=l"))]
1856 "TARGET_64BIT && ISA_HAS_DMUL3"
1858 [(set_attr "type" "imul3")
1859 (set_attr "mode" "DI")])
1861 ;; Widening multiply with negation.
1862 (define_insn "*muls<u>_di"
1863 [(set (match_operand:DI 0 "register_operand" "=x")
1866 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1867 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1868 "!TARGET_64BIT && ISA_HAS_MULS"
1870 [(set_attr "type" "imul")
1871 (set_attr "mode" "SI")])
1873 ;; As well as being named patterns, these instructions are used by the
1874 ;; __builtin_mips_msub<u>() functions. We must always make those functions
1875 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1877 ;; This leads to a slight inconsistency. We honor any tuning overrides
1878 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
1879 ;; even if !ISA_HAS_DSP_MULT.
1880 (define_insn "<u>msubsidi4"
1881 [(set (match_operand:DI 0 "register_operand" "=ka")
1883 (match_operand:DI 3 "register_operand" "0")
1885 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1886 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1887 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
1889 if (ISA_HAS_DSP_MULT)
1890 return "msub<u>\t%q0,%1,%2";
1891 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1892 return "msub<u>\t%1,%2";
1894 return "msac<u>\t$0,%1,%2";
1896 [(set_attr "type" "imadd")
1897 (set_attr "mode" "SI")])
1899 ;; _highpart patterns
1901 (define_expand "<su>mulsi3_highpart"
1902 [(set (match_operand:SI 0 "register_operand")
1905 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1906 (any_extend:DI (match_operand:SI 2 "register_operand")))
1911 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1915 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1920 (define_insn_and_split "<su>mulsi3_highpart_internal"
1921 [(set (match_operand:SI 0 "register_operand" "=d")
1924 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1925 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1927 (clobber (match_scratch:SI 3 "=l"))]
1929 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1930 "&& reload_completed && !TARGET_FIX_R4000"
1937 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1938 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1939 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1943 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1944 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1945 emit_insn (gen_mfhisi_di (operands[0], hilo));
1949 [(set_attr "type" "imul")
1950 (set_attr "mode" "SI")
1951 (set_attr "length" "8")])
1953 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1954 [(set (match_operand:SI 0 "register_operand" "=d")
1958 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1959 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1961 (clobber (match_scratch:SI 3 "=l"))]
1963 "mulhi<u>\t%0,%1,%2"
1964 [(set_attr "type" "imul3")
1965 (set_attr "mode" "SI")])
1967 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1968 [(set (match_operand:SI 0 "register_operand" "=d")
1973 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1974 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1976 (clobber (match_scratch:SI 3 "=l"))]
1978 "mulshi<u>\t%0,%1,%2"
1979 [(set_attr "type" "imul3")
1980 (set_attr "mode" "SI")])
1982 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1983 ;; errata MD(0), which says that dmultu does not always produce the
1985 (define_insn_and_split "<su>muldi3_highpart"
1986 [(set (match_operand:DI 0 "register_operand" "=d")
1989 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1990 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1992 (clobber (match_scratch:DI 3 "=l"))]
1993 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1994 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1995 "&& reload_completed && !TARGET_FIX_R4000"
2000 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2001 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2002 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2005 [(set_attr "type" "imul")
2006 (set_attr "mode" "DI")
2007 (set_attr "length" "8")])
2009 (define_expand "<u>mulditi3"
2010 [(set (match_operand:TI 0 "register_operand")
2011 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2012 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2013 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2015 if (TARGET_FIX_R4000)
2016 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2018 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2023 (define_insn "<u>mulditi3_internal"
2024 [(set (match_operand:TI 0 "register_operand" "=x")
2025 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2026 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2028 && !TARGET_FIX_R4000
2029 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2031 [(set_attr "type" "imul")
2032 (set_attr "mode" "DI")])
2034 (define_insn "<u>mulditi3_r4000"
2035 [(set (match_operand:TI 0 "register_operand" "=d")
2036 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2037 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2038 (clobber (match_scratch:TI 3 "=x"))]
2041 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2042 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2043 [(set_attr "type" "imul")
2044 (set_attr "mode" "DI")
2045 (set_attr "length" "12")])
2047 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2048 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2050 (define_insn "madsi"
2051 [(set (match_operand:SI 0 "register_operand" "+l")
2052 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2053 (match_operand:SI 2 "register_operand" "d"))
2057 [(set_attr "type" "imadd")
2058 (set_attr "mode" "SI")])
2060 ;; See the comment above <u>msubsidi4 for the relationship between
2061 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2062 (define_insn "<u>maddsidi4"
2063 [(set (match_operand:DI 0 "register_operand" "=ka")
2065 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2066 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2067 (match_operand:DI 3 "register_operand" "0")))]
2068 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2072 return "mad<u>\t%1,%2";
2073 else if (ISA_HAS_DSP_MULT)
2074 return "madd<u>\t%q0,%1,%2";
2075 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2076 return "madd<u>\t%1,%2";
2078 /* See comment in *macc. */
2079 return "%[macc<u>\t%@,%1,%2%]";
2081 [(set_attr "type" "imadd")
2082 (set_attr "mode" "SI")])
2084 ;; Floating point multiply accumulate instructions.
2086 (define_insn "*madd4<mode>"
2087 [(set (match_operand:ANYF 0 "register_operand" "=f")
2088 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2089 (match_operand:ANYF 2 "register_operand" "f"))
2090 (match_operand:ANYF 3 "register_operand" "f")))]
2091 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2092 "madd.<fmt>\t%0,%3,%1,%2"
2093 [(set_attr "type" "fmadd")
2094 (set_attr "mode" "<UNITMODE>")])
2096 (define_insn "*madd3<mode>"
2097 [(set (match_operand:ANYF 0 "register_operand" "=f")
2098 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2099 (match_operand:ANYF 2 "register_operand" "f"))
2100 (match_operand:ANYF 3 "register_operand" "0")))]
2101 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2102 "madd.<fmt>\t%0,%1,%2"
2103 [(set_attr "type" "fmadd")
2104 (set_attr "mode" "<UNITMODE>")])
2106 (define_insn "*msub4<mode>"
2107 [(set (match_operand:ANYF 0 "register_operand" "=f")
2108 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2109 (match_operand:ANYF 2 "register_operand" "f"))
2110 (match_operand:ANYF 3 "register_operand" "f")))]
2111 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2112 "msub.<fmt>\t%0,%3,%1,%2"
2113 [(set_attr "type" "fmadd")
2114 (set_attr "mode" "<UNITMODE>")])
2116 (define_insn "*msub3<mode>"
2117 [(set (match_operand:ANYF 0 "register_operand" "=f")
2118 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2119 (match_operand:ANYF 2 "register_operand" "f"))
2120 (match_operand:ANYF 3 "register_operand" "0")))]
2121 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2122 "msub.<fmt>\t%0,%1,%2"
2123 [(set_attr "type" "fmadd")
2124 (set_attr "mode" "<UNITMODE>")])
2126 (define_insn "*nmadd4<mode>"
2127 [(set (match_operand:ANYF 0 "register_operand" "=f")
2128 (neg:ANYF (plus:ANYF
2129 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2130 (match_operand:ANYF 2 "register_operand" "f"))
2131 (match_operand:ANYF 3 "register_operand" "f"))))]
2132 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2133 && TARGET_FUSED_MADD
2134 && HONOR_SIGNED_ZEROS (<MODE>mode)
2135 && !HONOR_NANS (<MODE>mode)"
2136 "nmadd.<fmt>\t%0,%3,%1,%2"
2137 [(set_attr "type" "fmadd")
2138 (set_attr "mode" "<UNITMODE>")])
2140 (define_insn "*nmadd3<mode>"
2141 [(set (match_operand:ANYF 0 "register_operand" "=f")
2142 (neg:ANYF (plus:ANYF
2143 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2144 (match_operand:ANYF 2 "register_operand" "f"))
2145 (match_operand:ANYF 3 "register_operand" "0"))))]
2146 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2147 && TARGET_FUSED_MADD
2148 && HONOR_SIGNED_ZEROS (<MODE>mode)
2149 && !HONOR_NANS (<MODE>mode)"
2150 "nmadd.<fmt>\t%0,%1,%2"
2151 [(set_attr "type" "fmadd")
2152 (set_attr "mode" "<UNITMODE>")])
2154 (define_insn "*nmadd4<mode>_fastmath"
2155 [(set (match_operand:ANYF 0 "register_operand" "=f")
2157 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2158 (match_operand:ANYF 2 "register_operand" "f"))
2159 (match_operand:ANYF 3 "register_operand" "f")))]
2160 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2161 && TARGET_FUSED_MADD
2162 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2163 && !HONOR_NANS (<MODE>mode)"
2164 "nmadd.<fmt>\t%0,%3,%1,%2"
2165 [(set_attr "type" "fmadd")
2166 (set_attr "mode" "<UNITMODE>")])
2168 (define_insn "*nmadd3<mode>_fastmath"
2169 [(set (match_operand:ANYF 0 "register_operand" "=f")
2171 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2172 (match_operand:ANYF 2 "register_operand" "f"))
2173 (match_operand:ANYF 3 "register_operand" "0")))]
2174 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2175 && TARGET_FUSED_MADD
2176 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2177 && !HONOR_NANS (<MODE>mode)"
2178 "nmadd.<fmt>\t%0,%1,%2"
2179 [(set_attr "type" "fmadd")
2180 (set_attr "mode" "<UNITMODE>")])
2182 (define_insn "*nmsub4<mode>"
2183 [(set (match_operand:ANYF 0 "register_operand" "=f")
2184 (neg:ANYF (minus:ANYF
2185 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2186 (match_operand:ANYF 3 "register_operand" "f"))
2187 (match_operand:ANYF 1 "register_operand" "f"))))]
2188 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2189 && TARGET_FUSED_MADD
2190 && HONOR_SIGNED_ZEROS (<MODE>mode)
2191 && !HONOR_NANS (<MODE>mode)"
2192 "nmsub.<fmt>\t%0,%1,%2,%3"
2193 [(set_attr "type" "fmadd")
2194 (set_attr "mode" "<UNITMODE>")])
2196 (define_insn "*nmsub3<mode>"
2197 [(set (match_operand:ANYF 0 "register_operand" "=f")
2198 (neg:ANYF (minus:ANYF
2199 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2200 (match_operand:ANYF 3 "register_operand" "f"))
2201 (match_operand:ANYF 1 "register_operand" "0"))))]
2202 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2203 && TARGET_FUSED_MADD
2204 && HONOR_SIGNED_ZEROS (<MODE>mode)
2205 && !HONOR_NANS (<MODE>mode)"
2206 "nmsub.<fmt>\t%0,%1,%2"
2207 [(set_attr "type" "fmadd")
2208 (set_attr "mode" "<UNITMODE>")])
2210 (define_insn "*nmsub4<mode>_fastmath"
2211 [(set (match_operand:ANYF 0 "register_operand" "=f")
2213 (match_operand:ANYF 1 "register_operand" "f")
2214 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2215 (match_operand:ANYF 3 "register_operand" "f"))))]
2216 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2217 && TARGET_FUSED_MADD
2218 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2219 && !HONOR_NANS (<MODE>mode)"
2220 "nmsub.<fmt>\t%0,%1,%2,%3"
2221 [(set_attr "type" "fmadd")
2222 (set_attr "mode" "<UNITMODE>")])
2224 (define_insn "*nmsub3<mode>_fastmath"
2225 [(set (match_operand:ANYF 0 "register_operand" "=f")
2227 (match_operand:ANYF 1 "register_operand" "f")
2228 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2229 (match_operand:ANYF 3 "register_operand" "0"))))]
2230 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2231 && TARGET_FUSED_MADD
2232 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2233 && !HONOR_NANS (<MODE>mode)"
2234 "nmsub.<fmt>\t%0,%1,%2"
2235 [(set_attr "type" "fmadd")
2236 (set_attr "mode" "<UNITMODE>")])
2239 ;; ....................
2241 ;; DIVISION and REMAINDER
2243 ;; ....................
2246 (define_expand "div<mode>3"
2247 [(set (match_operand:ANYF 0 "register_operand")
2248 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2249 (match_operand:ANYF 2 "register_operand")))]
2250 "<divide_condition>"
2252 if (const_1_operand (operands[1], <MODE>mode))
2253 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2254 operands[1] = force_reg (<MODE>mode, operands[1]);
2257 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2259 ;; If an mfc1 or dmfc1 happens to access the floating point register
2260 ;; file at the same time a long latency operation (div, sqrt, recip,
2261 ;; sqrt) iterates an intermediate result back through the floating
2262 ;; point register file bypass, then instead returning the correct
2263 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2264 ;; result of the long latency operation.
2266 ;; The workaround is to insert an unconditional 'mov' from/to the
2267 ;; long latency op destination register.
2269 (define_insn "*div<mode>3"
2270 [(set (match_operand:ANYF 0 "register_operand" "=f")
2271 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2272 (match_operand:ANYF 2 "register_operand" "f")))]
2273 "<divide_condition>"
2276 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2278 return "div.<fmt>\t%0,%1,%2";
2280 [(set_attr "type" "fdiv")
2281 (set_attr "mode" "<UNITMODE>")
2282 (set (attr "length")
2283 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2287 (define_insn "*recip<mode>3"
2288 [(set (match_operand:ANYF 0 "register_operand" "=f")
2289 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2290 (match_operand:ANYF 2 "register_operand" "f")))]
2291 "<recip_condition> && flag_unsafe_math_optimizations"
2294 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2296 return "recip.<fmt>\t%0,%2";
2298 [(set_attr "type" "frdiv")
2299 (set_attr "mode" "<UNITMODE>")
2300 (set (attr "length")
2301 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2305 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2306 ;; with negative operands. We use special libgcc functions instead.
2307 (define_insn_and_split "divmod<mode>4"
2308 [(set (match_operand:GPR 0 "register_operand" "=l")
2309 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2310 (match_operand:GPR 2 "register_operand" "d")))
2311 (set (match_operand:GPR 3 "register_operand" "=d")
2312 (mod:GPR (match_dup 1)
2314 "!TARGET_FIX_VR4120"
2316 "&& reload_completed"
2323 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2324 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2325 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2329 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2330 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2331 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2335 [(set_attr "type" "idiv")
2336 (set_attr "mode" "<MODE>")
2337 (set_attr "length" "8")])
2339 (define_insn_and_split "udivmod<mode>4"
2340 [(set (match_operand:GPR 0 "register_operand" "=l")
2341 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2342 (match_operand:GPR 2 "register_operand" "d")))
2343 (set (match_operand:GPR 3 "register_operand" "=d")
2344 (umod:GPR (match_dup 1)
2355 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2356 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2357 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2361 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2362 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2363 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2367 [(set_attr "type" "idiv")
2368 (set_attr "mode" "<MODE>")
2369 (set_attr "length" "8")])
2371 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2372 [(set (match_operand:HILO 0 "register_operand" "=x")
2374 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2375 (match_operand:GPR 2 "register_operand" "d"))]
2378 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2379 [(set_attr "type" "idiv")
2380 (set_attr "mode" "<GPR:MODE>")])
2383 ;; ....................
2387 ;; ....................
2389 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2390 ;; "*div[sd]f3" comment for details).
2392 (define_insn "sqrt<mode>2"
2393 [(set (match_operand:ANYF 0 "register_operand" "=f")
2394 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2398 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2400 return "sqrt.<fmt>\t%0,%1";
2402 [(set_attr "type" "fsqrt")
2403 (set_attr "mode" "<UNITMODE>")
2404 (set (attr "length")
2405 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2409 (define_insn "*rsqrt<mode>a"
2410 [(set (match_operand:ANYF 0 "register_operand" "=f")
2411 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2412 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2413 "<recip_condition> && flag_unsafe_math_optimizations"
2416 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2418 return "rsqrt.<fmt>\t%0,%2";
2420 [(set_attr "type" "frsqrt")
2421 (set_attr "mode" "<UNITMODE>")
2422 (set (attr "length")
2423 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2427 (define_insn "*rsqrt<mode>b"
2428 [(set (match_operand:ANYF 0 "register_operand" "=f")
2429 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2430 (match_operand:ANYF 2 "register_operand" "f"))))]
2431 "<recip_condition> && flag_unsafe_math_optimizations"
2434 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2436 return "rsqrt.<fmt>\t%0,%2";
2438 [(set_attr "type" "frsqrt")
2439 (set_attr "mode" "<UNITMODE>")
2440 (set (attr "length")
2441 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2446 ;; ....................
2450 ;; ....................
2452 ;; Do not use the integer abs macro instruction, since that signals an
2453 ;; exception on -2147483648 (sigh).
2455 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2456 ;; invalid; it does not clear their sign bits. We therefore can't use
2457 ;; abs.fmt if the signs of NaNs matter.
2459 (define_insn "abs<mode>2"
2460 [(set (match_operand:ANYF 0 "register_operand" "=f")
2461 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2462 "!HONOR_NANS (<MODE>mode)"
2464 [(set_attr "type" "fabs")
2465 (set_attr "mode" "<UNITMODE>")])
2468 ;; ...................
2470 ;; Count leading zeroes.
2472 ;; ...................
2475 (define_insn "clz<mode>2"
2476 [(set (match_operand:GPR 0 "register_operand" "=d")
2477 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2480 [(set_attr "type" "clz")
2481 (set_attr "mode" "<MODE>")])
2484 ;; ...................
2486 ;; Count number of set bits.
2488 ;; ...................
2491 (define_insn "popcount<mode>2"
2492 [(set (match_operand:GPR 0 "register_operand" "=d")
2493 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2496 [(set_attr "type" "pop")
2497 (set_attr "mode" "<MODE>")])
2500 ;; ....................
2502 ;; NEGATION and ONE'S COMPLEMENT
2504 ;; ....................
2506 (define_insn "negsi2"
2507 [(set (match_operand:SI 0 "register_operand" "=d")
2508 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2512 return "neg\t%0,%1";
2514 return "subu\t%0,%.,%1";
2516 [(set_attr "alu_type" "sub")
2517 (set_attr "mode" "SI")])
2519 (define_insn "negdi2"
2520 [(set (match_operand:DI 0 "register_operand" "=d")
2521 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2522 "TARGET_64BIT && !TARGET_MIPS16"
2524 [(set_attr "alu_type" "sub")
2525 (set_attr "mode" "DI")])
2527 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2528 ;; invalid; it does not flip their sign bit. We therefore can't use
2529 ;; neg.fmt if the signs of NaNs matter.
2531 (define_insn "neg<mode>2"
2532 [(set (match_operand:ANYF 0 "register_operand" "=f")
2533 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2534 "!HONOR_NANS (<MODE>mode)"
2536 [(set_attr "type" "fneg")
2537 (set_attr "mode" "<UNITMODE>")])
2539 (define_insn "one_cmpl<mode>2"
2540 [(set (match_operand:GPR 0 "register_operand" "=d")
2541 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2545 return "not\t%0,%1";
2547 return "nor\t%0,%.,%1";
2549 [(set_attr "alu_type" "not")
2550 (set_attr "mode" "<MODE>")])
2553 ;; ....................
2557 ;; ....................
2560 ;; Many of these instructions use trivial define_expands, because we
2561 ;; want to use a different set of constraints when TARGET_MIPS16.
2563 (define_expand "and<mode>3"
2564 [(set (match_operand:GPR 0 "register_operand")
2565 (and:GPR (match_operand:GPR 1 "register_operand")
2566 (match_operand:GPR 2 "and_reg_operand")))])
2568 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2569 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2570 ;; Note that this variant does not trigger for SI mode because we require
2571 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2572 ;; sign-extended SImode value.
2574 ;; These are possible combinations for operand 1 and 2. The table
2575 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2576 ;; 16=MIPS16, x=match, S=split):
2578 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2584 ;; 0xffff_ffff x S x S x
2589 (define_insn "*and<mode>3"
2590 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d")
2591 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d")
2592 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))]
2593 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2597 switch (which_alternative)
2600 operands[1] = gen_lowpart (QImode, operands[1]);
2601 return "lbu\t%0,%1";
2603 operands[1] = gen_lowpart (HImode, operands[1]);
2604 return "lhu\t%0,%1";
2606 operands[1] = gen_lowpart (SImode, operands[1]);
2607 return "lwu\t%0,%1";
2609 return "andi\t%0,%1,%x2";
2611 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2612 operands[2] = GEN_INT (len);
2613 return "<d>ext\t%0,%1,0,%2";
2617 return "and\t%0,%1,%2";
2622 [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical")
2623 (set_attr "mode" "<MODE>")])
2625 (define_insn "*and<mode>3_mips16"
2626 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2627 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
2628 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2629 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2631 switch (which_alternative)
2634 operands[1] = gen_lowpart (QImode, operands[1]);
2635 return "lbu\t%0,%1";
2637 operands[1] = gen_lowpart (HImode, operands[1]);
2638 return "lhu\t%0,%1";
2640 operands[1] = gen_lowpart (SImode, operands[1]);
2641 return "lwu\t%0,%1";
2645 return "and\t%0,%2";
2650 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2651 (set_attr "mode" "<MODE>")])
2653 (define_expand "ior<mode>3"
2654 [(set (match_operand:GPR 0 "register_operand")
2655 (ior:GPR (match_operand:GPR 1 "register_operand")
2656 (match_operand:GPR 2 "uns_arith_operand")))]
2660 operands[2] = force_reg (<MODE>mode, operands[2]);
2663 (define_insn "*ior<mode>3"
2664 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2665 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2666 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2671 [(set_attr "alu_type" "or")
2672 (set_attr "mode" "<MODE>")])
2674 (define_insn "*ior<mode>3_mips16"
2675 [(set (match_operand:GPR 0 "register_operand" "=d")
2676 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2677 (match_operand:GPR 2 "register_operand" "d")))]
2680 [(set_attr "alu_type" "or")
2681 (set_attr "mode" "<MODE>")])
2683 (define_expand "xor<mode>3"
2684 [(set (match_operand:GPR 0 "register_operand")
2685 (xor:GPR (match_operand:GPR 1 "register_operand")
2686 (match_operand:GPR 2 "uns_arith_operand")))]
2691 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2692 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2693 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2698 [(set_attr "alu_type" "xor")
2699 (set_attr "mode" "<MODE>")])
2702 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2703 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2704 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2710 [(set_attr "alu_type" "xor")
2711 (set_attr "mode" "<MODE>")
2712 (set_attr_alternative "length"
2714 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2719 (define_insn "*nor<mode>3"
2720 [(set (match_operand:GPR 0 "register_operand" "=d")
2721 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2722 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2725 [(set_attr "alu_type" "nor")
2726 (set_attr "mode" "<MODE>")])
2729 ;; ....................
2733 ;; ....................
2737 (define_insn "truncdfsf2"
2738 [(set (match_operand:SF 0 "register_operand" "=f")
2739 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2740 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2742 [(set_attr "type" "fcvt")
2743 (set_attr "cnv_mode" "D2S")
2744 (set_attr "mode" "SF")])
2746 ;; Integer truncation patterns. Truncating SImode values to smaller
2747 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2748 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2749 ;; need to make sure that the lower 32 bits are properly sign-extended
2750 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2751 ;; smaller than SImode is equivalent to two separate truncations:
2754 ;; DI ---> HI == DI ---> SI ---> HI
2755 ;; DI ---> QI == DI ---> SI ---> QI
2757 ;; Step A needs a real instruction but step B does not.
2759 (define_insn "truncdi<mode>2"
2760 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
2761 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
2766 [(set_attr "move_type" "sll0,store")
2767 (set_attr "mode" "SI")])
2769 ;; Combiner patterns to optimize shift/truncate combinations.
2771 (define_insn "*ashr_trunc<mode>"
2772 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2774 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2775 (match_operand:DI 2 "const_arith_operand" ""))))]
2776 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2778 [(set_attr "type" "shift")
2779 (set_attr "mode" "<MODE>")])
2781 (define_insn "*lshr32_trunc<mode>"
2782 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2784 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2786 "TARGET_64BIT && !TARGET_MIPS16"
2788 [(set_attr "type" "shift")
2789 (set_attr "mode" "<MODE>")])
2791 ;; Logical shift by more than 32 results in proper SI values so truncation is
2792 ;; removed by the middle end. Note that a logical shift by 32 is handled by
2793 ;; the previous pattern.
2794 (define_insn "*<optab>_trunc<mode>_exts"
2795 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2797 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2798 (match_operand:DI 2 "const_arith_operand" ""))))]
2799 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2801 [(set_attr "type" "arith")
2802 (set_attr "mode" "<MODE>")])
2805 ;; ....................
2809 ;; ....................
2813 (define_expand "zero_extendsidi2"
2814 [(set (match_operand:DI 0 "register_operand")
2815 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
2818 (define_insn_and_split "*zero_extendsidi2"
2819 [(set (match_operand:DI 0 "register_operand" "=d,d")
2820 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2821 "TARGET_64BIT && !ISA_HAS_EXT_INS"
2825 "&& reload_completed && REG_P (operands[1])"
2827 (ashift:DI (match_dup 1) (const_int 32)))
2829 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2830 { operands[1] = gen_lowpart (DImode, operands[1]); }
2831 [(set_attr "move_type" "shift_shift,load")
2832 (set_attr "mode" "DI")])
2834 (define_insn "*zero_extendsidi2_dext"
2835 [(set (match_operand:DI 0 "register_operand" "=d,d")
2836 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2837 "TARGET_64BIT && ISA_HAS_EXT_INS"
2841 [(set_attr "move_type" "arith,load")
2842 (set_attr "mode" "DI")])
2844 ;; See the comment before the *and<mode>3 pattern why this is generated by
2848 [(set (match_operand:DI 0 "register_operand")
2849 (and:DI (match_operand:DI 1 "register_operand")
2850 (const_int 4294967295)))]
2851 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
2853 (ashift:DI (match_dup 1) (const_int 32)))
2855 (lshiftrt:DI (match_dup 0) (const_int 32)))])
2857 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2858 [(set (match_operand:GPR 0 "register_operand")
2859 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2862 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2863 && !memory_operand (operands[1], <SHORT:MODE>mode))
2865 emit_insn (gen_and<GPR:mode>3 (operands[0],
2866 gen_lowpart (<GPR:MODE>mode, operands[1]),
2867 force_reg (<GPR:MODE>mode,
2868 GEN_INT (<SHORT:mask>))));
2873 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2874 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2876 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2879 andi\t%0,%1,<SHORT:mask>
2880 l<SHORT:size>u\t%0,%1"
2881 [(set_attr "move_type" "andi,load")
2882 (set_attr "mode" "<GPR:MODE>")])
2884 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2885 [(set (match_operand:GPR 0 "register_operand" "=d")
2886 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2888 "ze<SHORT:size>\t%0"
2889 ;; This instruction is effectively a special encoding of ANDI.
2890 [(set_attr "move_type" "andi")
2891 (set_attr "mode" "<GPR:MODE>")])
2893 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2894 [(set (match_operand:GPR 0 "register_operand" "=d")
2895 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2897 "l<SHORT:size>u\t%0,%1"
2898 [(set_attr "move_type" "load")
2899 (set_attr "mode" "<GPR:MODE>")])
2901 (define_expand "zero_extendqihi2"
2902 [(set (match_operand:HI 0 "register_operand")
2903 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2906 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2908 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2914 (define_insn "*zero_extendqihi2"
2915 [(set (match_operand:HI 0 "register_operand" "=d,d")
2916 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2921 [(set_attr "move_type" "andi,load")
2922 (set_attr "mode" "HI")])
2924 (define_insn "*zero_extendqihi2_mips16"
2925 [(set (match_operand:HI 0 "register_operand" "=d")
2926 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2929 [(set_attr "move_type" "load")
2930 (set_attr "mode" "HI")])
2932 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2934 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
2935 [(set (match_operand:GPR 0 "register_operand" "=d")
2937 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2938 "TARGET_64BIT && !TARGET_MIPS16"
2940 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
2941 return "andi\t%0,%1,%x2";
2943 [(set_attr "alu_type" "and")
2944 (set_attr "mode" "<GPR:MODE>")])
2946 (define_insn "*zero_extendhi_truncqi"
2947 [(set (match_operand:HI 0 "register_operand" "=d")
2949 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2950 "TARGET_64BIT && !TARGET_MIPS16"
2952 [(set_attr "alu_type" "and")
2953 (set_attr "mode" "HI")])
2956 ;; ....................
2960 ;; ....................
2963 ;; Those for integer source operand are ordered widest source type first.
2965 ;; When TARGET_64BIT, all SImode integer registers should already be in
2966 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2967 ;; therefore get rid of register->register instructions if we constrain
2968 ;; the source to be in the same register as the destination.
2970 ;; The register alternative has type "arith" so that the pre-reload
2971 ;; scheduler will treat it as a move. This reflects what happens if
2972 ;; the register alternative needs a reload.
2973 (define_insn_and_split "extendsidi2"
2974 [(set (match_operand:DI 0 "register_operand" "=d,d")
2975 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2980 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2983 emit_note (NOTE_INSN_DELETED);
2986 [(set_attr "move_type" "move,load")
2987 (set_attr "mode" "DI")])
2989 (define_expand "extend<SHORT:mode><GPR:mode>2"
2990 [(set (match_operand:GPR 0 "register_operand")
2991 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2994 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2995 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2996 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3000 l<SHORT:size>\t%0,%1"
3001 [(set_attr "move_type" "signext,load")
3002 (set_attr "mode" "<GPR:MODE>")])
3004 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3005 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3007 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3008 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3011 l<SHORT:size>\t%0,%1"
3012 "&& reload_completed && REG_P (operands[1])"
3013 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3014 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3016 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3017 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3018 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3020 [(set_attr "move_type" "shift_shift,load")
3021 (set_attr "mode" "<GPR:MODE>")])
3023 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3024 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3026 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3029 se<SHORT:size>\t%0,%1
3030 l<SHORT:size>\t%0,%1"
3031 [(set_attr "move_type" "signext,load")
3032 (set_attr "mode" "<GPR:MODE>")])
3034 (define_expand "extendqihi2"
3035 [(set (match_operand:HI 0 "register_operand")
3036 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3039 (define_insn "*extendqihi2_mips16e"
3040 [(set (match_operand:HI 0 "register_operand" "=d,d")
3041 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3046 [(set_attr "move_type" "signext,load")
3047 (set_attr "mode" "SI")])
3049 (define_insn_and_split "*extendqihi2"
3050 [(set (match_operand:HI 0 "register_operand" "=d,d")
3052 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3053 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3057 "&& reload_completed && REG_P (operands[1])"
3058 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3059 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3061 operands[0] = gen_lowpart (SImode, operands[0]);
3062 operands[1] = gen_lowpart (SImode, operands[1]);
3063 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3064 - GET_MODE_BITSIZE (QImode));
3066 [(set_attr "move_type" "shift_shift,load")
3067 (set_attr "mode" "SI")])
3069 (define_insn "*extendqihi2_seb"
3070 [(set (match_operand:HI 0 "register_operand" "=d,d")
3072 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3077 [(set_attr "move_type" "signext,load")
3078 (set_attr "mode" "SI")])
3080 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3081 ;; use the shift/truncate patterns.
3083 (define_insn_and_split "*extenddi_truncate<mode>"
3084 [(set (match_operand:DI 0 "register_operand" "=d")
3086 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3087 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3089 "&& reload_completed"
3091 (ashift:DI (match_dup 1)
3094 (ashiftrt:DI (match_dup 2)
3097 operands[2] = gen_lowpart (DImode, operands[0]);
3098 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3100 [(set_attr "move_type" "shift_shift")
3101 (set_attr "mode" "DI")])
3103 (define_insn_and_split "*extendsi_truncate<mode>"
3104 [(set (match_operand:SI 0 "register_operand" "=d")
3106 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3107 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3109 "&& reload_completed"
3111 (ashift:DI (match_dup 1)
3114 (truncate:SI (ashiftrt:DI (match_dup 2)
3117 operands[2] = gen_lowpart (DImode, operands[0]);
3118 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3120 [(set_attr "move_type" "shift_shift")
3121 (set_attr "mode" "SI")])
3123 (define_insn_and_split "*extendhi_truncateqi"
3124 [(set (match_operand:HI 0 "register_operand" "=d")
3126 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3127 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3129 "&& reload_completed"
3131 (ashift:DI (match_dup 1)
3134 (truncate:HI (ashiftrt:DI (match_dup 2)
3137 operands[2] = gen_lowpart (DImode, operands[0]);
3139 [(set_attr "move_type" "shift_shift")
3140 (set_attr "mode" "SI")])
3142 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3143 [(set (match_operand:GPR 0 "register_operand" "=d")
3145 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3146 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3148 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3149 return "exts\t%0,%1,0,%m2";
3151 [(set_attr "type" "arith")
3152 (set_attr "mode" "<GPR:MODE>")])
3154 (define_insn "*extendhi_truncateqi_exts"
3155 [(set (match_operand:HI 0 "register_operand" "=d")
3157 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3158 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3160 [(set_attr "type" "arith")
3161 (set_attr "mode" "SI")])
3163 (define_insn "extendsfdf2"
3164 [(set (match_operand:DF 0 "register_operand" "=f")
3165 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3166 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3168 [(set_attr "type" "fcvt")
3169 (set_attr "cnv_mode" "S2D")
3170 (set_attr "mode" "DF")])
3173 ;; ....................
3177 ;; ....................
3179 (define_expand "fix_truncdfsi2"
3180 [(set (match_operand:SI 0 "register_operand")
3181 (fix:SI (match_operand:DF 1 "register_operand")))]
3182 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3184 if (!ISA_HAS_TRUNC_W)
3186 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3191 (define_insn "fix_truncdfsi2_insn"
3192 [(set (match_operand:SI 0 "register_operand" "=f")
3193 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3194 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3196 [(set_attr "type" "fcvt")
3197 (set_attr "mode" "DF")
3198 (set_attr "cnv_mode" "D2I")])
3200 (define_insn "fix_truncdfsi2_macro"
3201 [(set (match_operand:SI 0 "register_operand" "=f")
3202 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3203 (clobber (match_scratch:DF 2 "=d"))]
3204 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3206 if (mips_nomacro.nesting_level > 0)
3207 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3209 return "trunc.w.d %0,%1,%2";
3211 [(set_attr "type" "fcvt")
3212 (set_attr "mode" "DF")
3213 (set_attr "cnv_mode" "D2I")
3214 (set_attr "length" "36")])
3216 (define_expand "fix_truncsfsi2"
3217 [(set (match_operand:SI 0 "register_operand")
3218 (fix:SI (match_operand:SF 1 "register_operand")))]
3221 if (!ISA_HAS_TRUNC_W)
3223 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3228 (define_insn "fix_truncsfsi2_insn"
3229 [(set (match_operand:SI 0 "register_operand" "=f")
3230 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3231 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3233 [(set_attr "type" "fcvt")
3234 (set_attr "mode" "SF")
3235 (set_attr "cnv_mode" "S2I")])
3237 (define_insn "fix_truncsfsi2_macro"
3238 [(set (match_operand:SI 0 "register_operand" "=f")
3239 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3240 (clobber (match_scratch:SF 2 "=d"))]
3241 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3243 if (mips_nomacro.nesting_level > 0)
3244 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3246 return "trunc.w.s %0,%1,%2";
3248 [(set_attr "type" "fcvt")
3249 (set_attr "mode" "SF")
3250 (set_attr "cnv_mode" "S2I")
3251 (set_attr "length" "36")])
3254 (define_insn "fix_truncdfdi2"
3255 [(set (match_operand:DI 0 "register_operand" "=f")
3256 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3257 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3259 [(set_attr "type" "fcvt")
3260 (set_attr "mode" "DF")
3261 (set_attr "cnv_mode" "D2I")])
3264 (define_insn "fix_truncsfdi2"
3265 [(set (match_operand:DI 0 "register_operand" "=f")
3266 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3267 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3269 [(set_attr "type" "fcvt")
3270 (set_attr "mode" "SF")
3271 (set_attr "cnv_mode" "S2I")])
3274 (define_insn "floatsidf2"
3275 [(set (match_operand:DF 0 "register_operand" "=f")
3276 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3277 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3279 [(set_attr "type" "fcvt")
3280 (set_attr "mode" "DF")
3281 (set_attr "cnv_mode" "I2D")])
3284 (define_insn "floatdidf2"
3285 [(set (match_operand:DF 0 "register_operand" "=f")
3286 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3287 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3289 [(set_attr "type" "fcvt")
3290 (set_attr "mode" "DF")
3291 (set_attr "cnv_mode" "I2D")])
3294 (define_insn "floatsisf2"
3295 [(set (match_operand:SF 0 "register_operand" "=f")
3296 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3299 [(set_attr "type" "fcvt")
3300 (set_attr "mode" "SF")
3301 (set_attr "cnv_mode" "I2S")])
3304 (define_insn "floatdisf2"
3305 [(set (match_operand:SF 0 "register_operand" "=f")
3306 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3307 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3309 [(set_attr "type" "fcvt")
3310 (set_attr "mode" "SF")
3311 (set_attr "cnv_mode" "I2S")])
3314 (define_expand "fixuns_truncdfsi2"
3315 [(set (match_operand:SI 0 "register_operand")
3316 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3317 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3319 rtx reg1 = gen_reg_rtx (DFmode);
3320 rtx reg2 = gen_reg_rtx (DFmode);
3321 rtx reg3 = gen_reg_rtx (SImode);
3322 rtx label1 = gen_label_rtx ();
3323 rtx label2 = gen_label_rtx ();
3325 REAL_VALUE_TYPE offset;
3327 real_2expN (&offset, 31, DFmode);
3329 if (reg1) /* Turn off complaints about unreached code. */
3331 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3332 do_pending_stack_adjust ();
3334 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3335 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3337 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3338 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3339 gen_rtx_LABEL_REF (VOIDmode, label2)));
3342 emit_label (label1);
3343 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3344 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3345 (BITMASK_HIGH, SImode)));
3347 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3348 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3350 emit_label (label2);
3352 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3353 fields, and can't be used for REG_NOTES anyway). */
3354 emit_use (stack_pointer_rtx);
3360 (define_expand "fixuns_truncdfdi2"
3361 [(set (match_operand:DI 0 "register_operand")
3362 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3363 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3365 rtx reg1 = gen_reg_rtx (DFmode);
3366 rtx reg2 = gen_reg_rtx (DFmode);
3367 rtx reg3 = gen_reg_rtx (DImode);
3368 rtx label1 = gen_label_rtx ();
3369 rtx label2 = gen_label_rtx ();
3371 REAL_VALUE_TYPE offset;
3373 real_2expN (&offset, 63, DFmode);
3375 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3376 do_pending_stack_adjust ();
3378 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3379 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3381 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3382 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3383 gen_rtx_LABEL_REF (VOIDmode, label2)));
3386 emit_label (label1);
3387 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3388 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3389 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3391 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3392 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3394 emit_label (label2);
3396 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3397 fields, and can't be used for REG_NOTES anyway). */
3398 emit_use (stack_pointer_rtx);
3403 (define_expand "fixuns_truncsfsi2"
3404 [(set (match_operand:SI 0 "register_operand")
3405 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3408 rtx reg1 = gen_reg_rtx (SFmode);
3409 rtx reg2 = gen_reg_rtx (SFmode);
3410 rtx reg3 = gen_reg_rtx (SImode);
3411 rtx label1 = gen_label_rtx ();
3412 rtx label2 = gen_label_rtx ();
3414 REAL_VALUE_TYPE offset;
3416 real_2expN (&offset, 31, SFmode);
3418 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3419 do_pending_stack_adjust ();
3421 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3422 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3424 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3425 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3426 gen_rtx_LABEL_REF (VOIDmode, label2)));
3429 emit_label (label1);
3430 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3431 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3432 (BITMASK_HIGH, SImode)));
3434 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3435 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3437 emit_label (label2);
3439 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3440 fields, and can't be used for REG_NOTES anyway). */
3441 emit_use (stack_pointer_rtx);
3446 (define_expand "fixuns_truncsfdi2"
3447 [(set (match_operand:DI 0 "register_operand")
3448 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3449 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3451 rtx reg1 = gen_reg_rtx (SFmode);
3452 rtx reg2 = gen_reg_rtx (SFmode);
3453 rtx reg3 = gen_reg_rtx (DImode);
3454 rtx label1 = gen_label_rtx ();
3455 rtx label2 = gen_label_rtx ();
3457 REAL_VALUE_TYPE offset;
3459 real_2expN (&offset, 63, SFmode);
3461 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3462 do_pending_stack_adjust ();
3464 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3465 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3467 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3468 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3469 gen_rtx_LABEL_REF (VOIDmode, label2)));
3472 emit_label (label1);
3473 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3474 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3475 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3477 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3478 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3480 emit_label (label2);
3482 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3483 fields, and can't be used for REG_NOTES anyway). */
3484 emit_use (stack_pointer_rtx);
3489 ;; ....................
3493 ;; ....................
3495 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3497 (define_expand "extv"
3498 [(set (match_operand 0 "register_operand")
3499 (sign_extract (match_operand 1 "nonimmediate_operand")
3500 (match_operand 2 "const_int_operand")
3501 (match_operand 3 "const_int_operand")))]
3504 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3505 INTVAL (operands[2]),
3506 INTVAL (operands[3])))
3508 else if (register_operand (operands[1], GET_MODE (operands[0]))
3509 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3511 if (GET_MODE (operands[0]) == DImode)
3512 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3515 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3523 (define_insn "extv<mode>"
3524 [(set (match_operand:GPR 0 "register_operand" "=d")
3525 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3526 (match_operand 2 "const_int_operand" "")
3527 (match_operand 3 "const_int_operand" "")))]
3528 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3529 "exts\t%0,%1,%3,%m2"
3530 [(set_attr "type" "arith")
3531 (set_attr "mode" "<MODE>")])
3534 (define_expand "extzv"
3535 [(set (match_operand 0 "register_operand")
3536 (zero_extract (match_operand 1 "nonimmediate_operand")
3537 (match_operand 2 "const_int_operand")
3538 (match_operand 3 "const_int_operand")))]
3541 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3542 INTVAL (operands[2]),
3543 INTVAL (operands[3])))
3545 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3546 INTVAL (operands[3])))
3548 if (GET_MODE (operands[0]) == DImode)
3549 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3552 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3560 (define_insn "extzv<mode>"
3561 [(set (match_operand:GPR 0 "register_operand" "=d")
3562 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3563 (match_operand 2 "const_int_operand" "")
3564 (match_operand 3 "const_int_operand" "")))]
3565 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3566 INTVAL (operands[3]))"
3567 "<d>ext\t%0,%1,%3,%2"
3568 [(set_attr "type" "arith")
3569 (set_attr "mode" "<MODE>")])
3571 (define_insn "*extzv_truncsi_exts"
3572 [(set (match_operand:SI 0 "register_operand" "=d")
3574 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3575 (match_operand 2 "const_int_operand" "")
3576 (match_operand 3 "const_int_operand" ""))))]
3577 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3579 [(set_attr "type" "arith")
3580 (set_attr "mode" "SI")])
3583 (define_expand "insv"
3584 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3585 (match_operand 1 "immediate_operand")
3586 (match_operand 2 "immediate_operand"))
3587 (match_operand 3 "reg_or_0_operand"))]
3590 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3591 INTVAL (operands[1]),
3592 INTVAL (operands[2])))
3594 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3595 INTVAL (operands[2])))
3597 if (GET_MODE (operands[0]) == DImode)
3598 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3601 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3609 (define_insn "insv<mode>"
3610 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3611 (match_operand:SI 1 "immediate_operand" "I")
3612 (match_operand:SI 2 "immediate_operand" "I"))
3613 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3614 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3615 INTVAL (operands[2]))"
3616 "<d>ins\t%0,%z3,%2,%1"
3617 [(set_attr "type" "arith")
3618 (set_attr "mode" "<MODE>")])
3620 ;; Combiner pattern for cins (clear and insert bit field). We can
3621 ;; implement mask-and-shift-left operation with this. Note that if
3622 ;; the upper bit of the mask is set in an SImode operation, the mask
3623 ;; itself will be sign-extended. mask_low_and_shift_len will
3624 ;; therefore be greater than our threshold of 32.
3626 (define_insn "*cins<mode>"
3627 [(set (match_operand:GPR 0 "register_operand" "=d")
3629 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3630 (match_operand:GPR 2 "const_int_operand" ""))
3631 (match_operand:GPR 3 "const_int_operand" "")))]
3633 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3636 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3637 return "cins\t%0,%1,%2,%m3";
3639 [(set_attr "type" "shift")
3640 (set_attr "mode" "<MODE>")])
3642 ;; Unaligned word moves generated by the bit field patterns.
3644 ;; As far as the rtl is concerned, both the left-part and right-part
3645 ;; instructions can access the whole field. However, the real operand
3646 ;; refers to just the first or the last byte (depending on endianness).
3647 ;; We therefore use two memory operands to each instruction, one to
3648 ;; describe the rtl effect and one to use in the assembly output.
3650 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3651 ;; This allows us to use the standard length calculations for the "load"
3652 ;; and "store" type attributes.
3654 (define_insn "mov_<load>l"
3655 [(set (match_operand:GPR 0 "register_operand" "=d")
3656 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3657 (match_operand:QI 2 "memory_operand" "m")]
3659 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3661 [(set_attr "move_type" "load")
3662 (set_attr "mode" "<MODE>")])
3664 (define_insn "mov_<load>r"
3665 [(set (match_operand:GPR 0 "register_operand" "=d")
3666 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3667 (match_operand:QI 2 "memory_operand" "m")
3668 (match_operand:GPR 3 "register_operand" "0")]
3669 UNSPEC_LOAD_RIGHT))]
3670 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3672 [(set_attr "move_type" "load")
3673 (set_attr "mode" "<MODE>")])
3675 (define_insn "mov_<store>l"
3676 [(set (match_operand:BLK 0 "memory_operand" "=m")
3677 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3678 (match_operand:QI 2 "memory_operand" "m")]
3679 UNSPEC_STORE_LEFT))]
3680 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3682 [(set_attr "move_type" "store")
3683 (set_attr "mode" "<MODE>")])
3685 (define_insn "mov_<store>r"
3686 [(set (match_operand:BLK 0 "memory_operand" "+m")
3687 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3688 (match_operand:QI 2 "memory_operand" "m")
3690 UNSPEC_STORE_RIGHT))]
3691 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3693 [(set_attr "move_type" "store")
3694 (set_attr "mode" "<MODE>")])
3696 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3697 ;; The required value is:
3699 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3701 ;; which translates to:
3703 ;; lui op0,%highest(op1)
3704 ;; daddiu op0,op0,%higher(op1)
3706 ;; daddiu op0,op0,%hi(op1)
3709 ;; The split is deferred until after flow2 to allow the peephole2 below
3711 (define_insn_and_split "*lea_high64"
3712 [(set (match_operand:DI 0 "register_operand" "=d")
3713 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3714 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3716 "&& epilogue_completed"
3717 [(set (match_dup 0) (high:DI (match_dup 2)))
3718 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3719 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3720 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3721 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3723 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3724 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3726 [(set_attr "length" "20")])
3728 ;; Use a scratch register to reduce the latency of the above pattern
3729 ;; on superscalar machines. The optimized sequence is:
3731 ;; lui op1,%highest(op2)
3733 ;; daddiu op1,op1,%higher(op2)
3735 ;; daddu op1,op1,op0
3737 [(set (match_operand:DI 1 "d_operand")
3738 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3739 (match_scratch:DI 0 "d")]
3740 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3741 [(set (match_dup 1) (high:DI (match_dup 3)))
3742 (set (match_dup 0) (high:DI (match_dup 4)))
3743 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3744 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3745 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3747 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3748 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3751 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3752 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3753 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3754 ;; used once. We can then use the sequence:
3756 ;; lui op0,%highest(op1)
3758 ;; daddiu op0,op0,%higher(op1)
3759 ;; daddiu op2,op2,%lo(op1)
3761 ;; daddu op0,op0,op2
3763 ;; which takes 4 cycles on most superscalar targets.
3764 (define_insn_and_split "*lea64"
3765 [(set (match_operand:DI 0 "register_operand" "=d")
3766 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3767 (clobber (match_scratch:DI 2 "=&d"))]
3768 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3770 "&& reload_completed"
3771 [(set (match_dup 0) (high:DI (match_dup 3)))
3772 (set (match_dup 2) (high:DI (match_dup 4)))
3773 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3774 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3775 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3776 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3778 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3779 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3781 [(set_attr "length" "24")])
3783 ;; Split HIGHs into:
3788 ;; on MIPS16 targets.
3790 [(set (match_operand:SI 0 "d_operand")
3791 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3792 "TARGET_MIPS16 && reload_completed"
3793 [(set (match_dup 0) (match_dup 2))
3794 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3796 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3799 ;; Insns to fetch a symbol from a big GOT.
3801 (define_insn_and_split "*xgot_hi<mode>"
3802 [(set (match_operand:P 0 "register_operand" "=d")
3803 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3804 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3806 "&& reload_completed"
3807 [(set (match_dup 0) (high:P (match_dup 2)))
3808 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3810 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3811 operands[3] = pic_offset_table_rtx;
3813 [(set_attr "got" "xgot_high")
3814 (set_attr "mode" "<MODE>")])
3816 (define_insn_and_split "*xgot_lo<mode>"
3817 [(set (match_operand:P 0 "register_operand" "=d")
3818 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3819 (match_operand:P 2 "got_disp_operand" "")))]
3820 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3822 "&& reload_completed"
3824 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3825 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3826 [(set_attr "got" "load")
3827 (set_attr "mode" "<MODE>")])
3829 ;; Insns to fetch a symbol from a normal GOT.
3831 (define_insn_and_split "*got_disp<mode>"
3832 [(set (match_operand:P 0 "register_operand" "=d")
3833 (match_operand:P 1 "got_disp_operand" ""))]
3834 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3836 "&& reload_completed"
3837 [(set (match_dup 0) (match_dup 2))]
3838 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3839 [(set_attr "got" "load")
3840 (set_attr "mode" "<MODE>")])
3842 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3844 (define_insn_and_split "*got_page<mode>"
3845 [(set (match_operand:P 0 "register_operand" "=d")
3846 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3847 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3849 "&& reload_completed"
3850 [(set (match_dup 0) (match_dup 2))]
3851 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3852 [(set_attr "got" "load")
3853 (set_attr "mode" "<MODE>")])
3855 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3856 (define_expand "unspec_got<mode>"
3857 [(unspec:P [(match_operand:P 0)
3858 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3860 ;; Lower-level instructions for loading an address from the GOT.
3861 ;; We could use MEMs, but an unspec gives more optimization
3864 (define_insn "load_got<mode>"
3865 [(set (match_operand:P 0 "register_operand" "=d")
3866 (unspec:P [(match_operand:P 1 "register_operand" "d")
3867 (match_operand:P 2 "immediate_operand" "")]
3870 "<load>\t%0,%R2(%1)"
3871 [(set_attr "got" "load")
3872 (set_attr "mode" "<MODE>")])
3874 ;; Instructions for adding the low 16 bits of an address to a register.
3875 ;; Operand 2 is the address: mips_print_operand works out which relocation
3876 ;; should be applied.
3878 (define_insn "*low<mode>"
3879 [(set (match_operand:P 0 "register_operand" "=d")
3880 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3881 (match_operand:P 2 "immediate_operand" "")))]
3883 "<d>addiu\t%0,%1,%R2"
3884 [(set_attr "alu_type" "add")
3885 (set_attr "mode" "<MODE>")])
3887 (define_insn "*low<mode>_mips16"
3888 [(set (match_operand:P 0 "register_operand" "=d")
3889 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3890 (match_operand:P 2 "immediate_operand" "")))]
3893 [(set_attr "alu_type" "add")
3894 (set_attr "mode" "<MODE>")
3895 (set_attr "extended_mips16" "yes")])
3897 ;; Expose MIPS16 uses of the global pointer after reload if the function
3898 ;; is responsible for setting up the register itself.
3900 [(set (match_operand:GPR 0 "d_operand")
3901 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3902 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3903 [(set (match_dup 0) (match_dup 1))]
3904 { operands[1] = pic_offset_table_rtx; })
3906 ;; Allow combine to split complex const_int load sequences, using operand 2
3907 ;; to store the intermediate results. See move_operand for details.
3909 [(set (match_operand:GPR 0 "register_operand")
3910 (match_operand:GPR 1 "splittable_const_int_operand"))
3911 (clobber (match_operand:GPR 2 "register_operand"))]
3915 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3919 ;; Likewise, for symbolic operands.
3921 [(set (match_operand:P 0 "register_operand")
3922 (match_operand:P 1))
3923 (clobber (match_operand:P 2 "register_operand"))]
3924 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3925 [(set (match_dup 0) (match_dup 3))]
3927 mips_split_symbol (operands[2], operands[1],
3928 MAX_MACHINE_MODE, &operands[3]);
3931 ;; 64-bit integer moves
3933 ;; Unlike most other insns, the move insns can't be split with
3934 ;; different predicates, because register spilling and other parts of
3935 ;; the compiler, have memoized the insn number already.
3937 (define_expand "movdi"
3938 [(set (match_operand:DI 0 "")
3939 (match_operand:DI 1 ""))]
3942 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3946 ;; For mips16, we need a special case to handle storing $31 into
3947 ;; memory, since we don't have a constraint to match $31. This
3948 ;; instruction can be generated by save_restore_insns.
3950 (define_insn "*mov<mode>_ra"
3951 [(set (match_operand:GPR 0 "stack_operand" "=m")
3952 (reg:GPR RETURN_ADDR_REGNUM))]
3955 [(set_attr "move_type" "store")
3956 (set_attr "mode" "<MODE>")])
3958 (define_insn "*movdi_32bit"
3959 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3960 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3961 "!TARGET_64BIT && !TARGET_MIPS16
3962 && (register_operand (operands[0], DImode)
3963 || reg_or_0_operand (operands[1], DImode))"
3964 { return mips_output_move (operands[0], operands[1]); }
3965 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3966 (set_attr "mode" "DI")])
3968 (define_insn "*movdi_32bit_mips16"
3969 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3970 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3971 "!TARGET_64BIT && TARGET_MIPS16
3972 && (register_operand (operands[0], DImode)
3973 || register_operand (operands[1], DImode))"
3974 { return mips_output_move (operands[0], operands[1]); }
3975 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3976 (set_attr "mode" "DI")])
3978 (define_insn "*movdi_64bit"
3979 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3980 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3981 "TARGET_64BIT && !TARGET_MIPS16
3982 && (register_operand (operands[0], DImode)
3983 || reg_or_0_operand (operands[1], DImode))"
3984 { return mips_output_move (operands[0], operands[1]); }
3985 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3986 (set_attr "mode" "DI")])
3988 (define_insn "*movdi_64bit_mips16"
3989 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3990 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3991 "TARGET_64BIT && TARGET_MIPS16
3992 && (register_operand (operands[0], DImode)
3993 || register_operand (operands[1], DImode))"
3994 { return mips_output_move (operands[0], operands[1]); }
3995 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3996 (set_attr "mode" "DI")])
3998 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3999 ;; when the original load is a 4 byte instruction but the add and the
4000 ;; load are 2 2 byte instructions.
4003 [(set (match_operand:DI 0 "d_operand")
4004 (mem:DI (plus:DI (match_dup 0)
4005 (match_operand:DI 1 "const_int_operand"))))]
4006 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4007 && !TARGET_DEBUG_D_MODE
4008 && ((INTVAL (operands[1]) < 0
4009 && INTVAL (operands[1]) >= -0x10)
4010 || (INTVAL (operands[1]) >= 32 * 8
4011 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4012 || (INTVAL (operands[1]) >= 0
4013 && INTVAL (operands[1]) < 32 * 8
4014 && (INTVAL (operands[1]) & 7) != 0))"
4015 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4016 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4018 HOST_WIDE_INT val = INTVAL (operands[1]);
4021 operands[2] = const0_rtx;
4022 else if (val >= 32 * 8)
4026 operands[1] = GEN_INT (0x8 + off);
4027 operands[2] = GEN_INT (val - off - 0x8);
4033 operands[1] = GEN_INT (off);
4034 operands[2] = GEN_INT (val - off);
4038 ;; 32-bit Integer moves
4040 ;; Unlike most other insns, the move insns can't be split with
4041 ;; different predicates, because register spilling and other parts of
4042 ;; the compiler, have memoized the insn number already.
4044 (define_expand "mov<mode>"
4045 [(set (match_operand:IMOVE32 0 "")
4046 (match_operand:IMOVE32 1 ""))]
4049 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4053 ;; The difference between these two is whether or not ints are allowed
4054 ;; in FP registers (off by default, use -mdebugh to enable).
4056 (define_insn "*mov<mode>_internal"
4057 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4058 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4060 && (register_operand (operands[0], <MODE>mode)
4061 || reg_or_0_operand (operands[1], <MODE>mode))"
4062 { return mips_output_move (operands[0], operands[1]); }
4063 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
4064 (set_attr "mode" "SI")])
4066 (define_insn "*mov<mode>_mips16"
4067 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4068 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4070 && (register_operand (operands[0], <MODE>mode)
4071 || register_operand (operands[1], <MODE>mode))"
4072 { return mips_output_move (operands[0], operands[1]); }
4073 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
4074 (set_attr "mode" "SI")])
4076 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4077 ;; when the original load is a 4 byte instruction but the add and the
4078 ;; load are 2 2 byte instructions.
4081 [(set (match_operand:SI 0 "d_operand")
4082 (mem:SI (plus:SI (match_dup 0)
4083 (match_operand:SI 1 "const_int_operand"))))]
4084 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4085 && ((INTVAL (operands[1]) < 0
4086 && INTVAL (operands[1]) >= -0x80)
4087 || (INTVAL (operands[1]) >= 32 * 4
4088 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4089 || (INTVAL (operands[1]) >= 0
4090 && INTVAL (operands[1]) < 32 * 4
4091 && (INTVAL (operands[1]) & 3) != 0))"
4092 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4093 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4095 HOST_WIDE_INT val = INTVAL (operands[1]);
4098 operands[2] = const0_rtx;
4099 else if (val >= 32 * 4)
4103 operands[1] = GEN_INT (0x7c + off);
4104 operands[2] = GEN_INT (val - off - 0x7c);
4110 operands[1] = GEN_INT (off);
4111 operands[2] = GEN_INT (val - off);
4115 ;; On the mips16, we can split a load of certain constants into a load
4116 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4120 [(set (match_operand:SI 0 "d_operand")
4121 (match_operand:SI 1 "const_int_operand"))]
4122 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4123 && INTVAL (operands[1]) >= 0x100
4124 && INTVAL (operands[1]) <= 0xff + 0x7f"
4125 [(set (match_dup 0) (match_dup 1))
4126 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4128 int val = INTVAL (operands[1]);
4130 operands[1] = GEN_INT (0xff);
4131 operands[2] = GEN_INT (val - 0xff);
4134 ;; This insn handles moving CCmode values. It's really just a
4135 ;; slightly simplified copy of movsi_internal2, with additional cases
4136 ;; to move a condition register to a general register and to move
4137 ;; between the general registers and the floating point registers.
4139 (define_insn "movcc"
4140 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4141 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4142 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4143 { return mips_output_move (operands[0], operands[1]); }
4144 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4145 (set_attr "mode" "SI")])
4147 ;; Reload condition code registers. reload_incc and reload_outcc
4148 ;; both handle moves from arbitrary operands into condition code
4149 ;; registers. reload_incc handles the more common case in which
4150 ;; a source operand is constrained to be in a condition-code
4151 ;; register, but has not been allocated to one.
4153 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4154 ;; constraints do not include 'z'. reload_outcc handles the case
4155 ;; when such an operand is allocated to a condition-code register.
4157 ;; Note that reloads from a condition code register to some
4158 ;; other location can be done using ordinary moves. Moving
4159 ;; into a GPR takes a single movcc, moving elsewhere takes
4160 ;; two. We can leave these cases to the generic reload code.
4161 (define_expand "reload_incc"
4162 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4163 (match_operand:CC 1 "general_operand" ""))
4164 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4165 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4167 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4171 (define_expand "reload_outcc"
4172 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4173 (match_operand:CC 1 "register_operand" ""))
4174 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4175 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4177 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4181 ;; MIPS4 supports loading and storing a floating point register from
4182 ;; the sum of two general registers. We use two versions for each of
4183 ;; these four instructions: one where the two general registers are
4184 ;; SImode, and one where they are DImode. This is because general
4185 ;; registers will be in SImode when they hold 32-bit values, but,
4186 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4187 ;; instructions will still work correctly.
4189 ;; ??? Perhaps it would be better to support these instructions by
4190 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4191 ;; these instructions can only be used to load and store floating
4192 ;; point registers, that would probably cause trouble in reload.
4194 (define_insn "*<ANYF:loadx>_<P:mode>"
4195 [(set (match_operand:ANYF 0 "register_operand" "=f")
4196 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4197 (match_operand:P 2 "register_operand" "d"))))]
4199 "<ANYF:loadx>\t%0,%1(%2)"
4200 [(set_attr "type" "fpidxload")
4201 (set_attr "mode" "<ANYF:UNITMODE>")])
4203 (define_insn "*<ANYF:storex>_<P:mode>"
4204 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4205 (match_operand:P 2 "register_operand" "d")))
4206 (match_operand:ANYF 0 "register_operand" "f"))]
4208 "<ANYF:storex>\t%0,%1(%2)"
4209 [(set_attr "type" "fpidxstore")
4210 (set_attr "mode" "<ANYF:UNITMODE>")])
4212 ;; Scaled indexed address load.
4213 ;; Per md.texi, we only need to look for a pattern with multiply in the
4214 ;; address expression, not shift.
4216 (define_insn "*lwxs"
4217 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4219 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4221 (match_operand:P 2 "register_operand" "d"))))]
4224 [(set_attr "type" "load")
4225 (set_attr "mode" "SI")])
4227 ;; 16-bit Integer moves
4229 ;; Unlike most other insns, the move insns can't be split with
4230 ;; different predicates, because register spilling and other parts of
4231 ;; the compiler, have memoized the insn number already.
4232 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4234 (define_expand "movhi"
4235 [(set (match_operand:HI 0 "")
4236 (match_operand:HI 1 ""))]
4239 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4243 (define_insn "*movhi_internal"
4244 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4245 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4247 && (register_operand (operands[0], HImode)
4248 || reg_or_0_operand (operands[1], HImode))"
4249 { return mips_output_move (operands[0], operands[1]); }
4250 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4251 (set_attr "mode" "HI")])
4253 (define_insn "*movhi_mips16"
4254 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4255 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4257 && (register_operand (operands[0], HImode)
4258 || register_operand (operands[1], HImode))"
4259 { return mips_output_move (operands[0], operands[1]); }
4260 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4261 (set_attr "mode" "HI")])
4263 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4264 ;; when the original load is a 4 byte instruction but the add and the
4265 ;; load are 2 2 byte instructions.
4268 [(set (match_operand:HI 0 "d_operand")
4269 (mem:HI (plus:SI (match_dup 0)
4270 (match_operand:SI 1 "const_int_operand"))))]
4271 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4272 && ((INTVAL (operands[1]) < 0
4273 && INTVAL (operands[1]) >= -0x80)
4274 || (INTVAL (operands[1]) >= 32 * 2
4275 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4276 || (INTVAL (operands[1]) >= 0
4277 && INTVAL (operands[1]) < 32 * 2
4278 && (INTVAL (operands[1]) & 1) != 0))"
4279 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4280 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4282 HOST_WIDE_INT val = INTVAL (operands[1]);
4285 operands[2] = const0_rtx;
4286 else if (val >= 32 * 2)
4290 operands[1] = GEN_INT (0x7e + off);
4291 operands[2] = GEN_INT (val - off - 0x7e);
4297 operands[1] = GEN_INT (off);
4298 operands[2] = GEN_INT (val - off);
4302 ;; 8-bit Integer moves
4304 ;; Unlike most other insns, the move insns can't be split with
4305 ;; different predicates, because register spilling and other parts of
4306 ;; the compiler, have memoized the insn number already.
4307 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4309 (define_expand "movqi"
4310 [(set (match_operand:QI 0 "")
4311 (match_operand:QI 1 ""))]
4314 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4318 (define_insn "*movqi_internal"
4319 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4320 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4322 && (register_operand (operands[0], QImode)
4323 || reg_or_0_operand (operands[1], QImode))"
4324 { return mips_output_move (operands[0], operands[1]); }
4325 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4326 (set_attr "mode" "QI")])
4328 (define_insn "*movqi_mips16"
4329 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4330 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4332 && (register_operand (operands[0], QImode)
4333 || register_operand (operands[1], QImode))"
4334 { return mips_output_move (operands[0], operands[1]); }
4335 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4336 (set_attr "mode" "QI")])
4338 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4339 ;; when the original load is a 4 byte instruction but the add and the
4340 ;; load are 2 2 byte instructions.
4343 [(set (match_operand:QI 0 "d_operand")
4344 (mem:QI (plus:SI (match_dup 0)
4345 (match_operand:SI 1 "const_int_operand"))))]
4346 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4347 && ((INTVAL (operands[1]) < 0
4348 && INTVAL (operands[1]) >= -0x80)
4349 || (INTVAL (operands[1]) >= 32
4350 && INTVAL (operands[1]) <= 31 + 0x7f))"
4351 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4352 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4354 HOST_WIDE_INT val = INTVAL (operands[1]);
4357 operands[2] = const0_rtx;
4360 operands[1] = GEN_INT (0x7f);
4361 operands[2] = GEN_INT (val - 0x7f);
4365 ;; 32-bit floating point moves
4367 (define_expand "movsf"
4368 [(set (match_operand:SF 0 "")
4369 (match_operand:SF 1 ""))]
4372 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4376 (define_insn "*movsf_hardfloat"
4377 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4378 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4380 && (register_operand (operands[0], SFmode)
4381 || reg_or_0_operand (operands[1], SFmode))"
4382 { return mips_output_move (operands[0], operands[1]); }
4383 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4384 (set_attr "mode" "SF")])
4386 (define_insn "*movsf_softfloat"
4387 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4388 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4389 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4390 && (register_operand (operands[0], SFmode)
4391 || reg_or_0_operand (operands[1], SFmode))"
4392 { return mips_output_move (operands[0], operands[1]); }
4393 [(set_attr "move_type" "move,load,store")
4394 (set_attr "mode" "SF")])
4396 (define_insn "*movsf_mips16"
4397 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4398 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4400 && (register_operand (operands[0], SFmode)
4401 || register_operand (operands[1], SFmode))"
4402 { return mips_output_move (operands[0], operands[1]); }
4403 [(set_attr "move_type" "move,move,move,load,store")
4404 (set_attr "mode" "SF")])
4406 ;; 64-bit floating point moves
4408 (define_expand "movdf"
4409 [(set (match_operand:DF 0 "")
4410 (match_operand:DF 1 ""))]
4413 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4417 (define_insn "*movdf_hardfloat"
4418 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4419 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4420 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4421 && (register_operand (operands[0], DFmode)
4422 || reg_or_0_operand (operands[1], DFmode))"
4423 { return mips_output_move (operands[0], operands[1]); }
4424 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4425 (set_attr "mode" "DF")])
4427 (define_insn "*movdf_softfloat"
4428 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4429 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4430 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4431 && (register_operand (operands[0], DFmode)
4432 || reg_or_0_operand (operands[1], DFmode))"
4433 { return mips_output_move (operands[0], operands[1]); }
4434 [(set_attr "move_type" "move,load,store")
4435 (set_attr "mode" "DF")])
4437 (define_insn "*movdf_mips16"
4438 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4439 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4441 && (register_operand (operands[0], DFmode)
4442 || register_operand (operands[1], DFmode))"
4443 { return mips_output_move (operands[0], operands[1]); }
4444 [(set_attr "move_type" "move,move,move,load,store")
4445 (set_attr "mode" "DF")])
4447 ;; 128-bit integer moves
4449 (define_expand "movti"
4450 [(set (match_operand:TI 0)
4451 (match_operand:TI 1))]
4454 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4458 (define_insn "*movti"
4459 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4460 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4463 && (register_operand (operands[0], TImode)
4464 || reg_or_0_operand (operands[1], TImode))"
4466 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4467 (set_attr "mode" "TI")])
4469 (define_insn "*movti_mips16"
4470 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4471 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4474 && (register_operand (operands[0], TImode)
4475 || register_operand (operands[1], TImode))"
4477 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4478 (set_attr "mode" "TI")])
4480 ;; 128-bit floating point moves
4482 (define_expand "movtf"
4483 [(set (match_operand:TF 0)
4484 (match_operand:TF 1))]
4487 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4491 ;; This pattern handles both hard- and soft-float cases.
4492 (define_insn "*movtf"
4493 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4494 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4497 && (register_operand (operands[0], TFmode)
4498 || reg_or_0_operand (operands[1], TFmode))"
4500 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4501 (set_attr "mode" "TF")])
4503 (define_insn "*movtf_mips16"
4504 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4505 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4508 && (register_operand (operands[0], TFmode)
4509 || register_operand (operands[1], TFmode))"
4511 [(set_attr "move_type" "move,move,move,load,store")
4512 (set_attr "mode" "TF")])
4515 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4516 (match_operand:MOVE64 1 "move_operand"))]
4517 "reload_completed && !TARGET_64BIT
4518 && mips_split_64bit_move_p (operands[0], operands[1])"
4521 mips_split_doubleword_move (operands[0], operands[1]);
4526 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4527 (match_operand:MOVE128 1 "move_operand"))]
4528 "TARGET_64BIT && reload_completed"
4531 mips_split_doubleword_move (operands[0], operands[1]);
4535 ;; When generating mips16 code, split moves of negative constants into
4536 ;; a positive "li" followed by a negation.
4538 [(set (match_operand 0 "d_operand")
4539 (match_operand 1 "const_int_operand"))]
4540 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4544 (neg:SI (match_dup 2)))]
4546 operands[2] = gen_lowpart (SImode, operands[0]);
4547 operands[3] = GEN_INT (-INTVAL (operands[1]));
4550 ;; 64-bit paired-single floating point moves
4552 (define_expand "movv2sf"
4553 [(set (match_operand:V2SF 0)
4554 (match_operand:V2SF 1))]
4555 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4557 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4561 (define_insn "*movv2sf"
4562 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4563 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4565 && TARGET_PAIRED_SINGLE_FLOAT
4566 && (register_operand (operands[0], V2SFmode)
4567 || reg_or_0_operand (operands[1], V2SFmode))"
4568 { return mips_output_move (operands[0], operands[1]); }
4569 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4570 (set_attr "mode" "DF")])
4572 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4573 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4575 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4576 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4577 ;; and the errata related to -mfix-vr4130.
4578 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4579 [(set (match_operand:GPR 0 "register_operand" "=d")
4580 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4583 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4584 [(set_attr "move_type" "mfhilo")
4585 (set_attr "mode" "<GPR:MODE>")])
4587 ;; Set the high part of a HI/LO value, given that the low part has
4588 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4589 ;; why we can't just use (reg:GPR HI_REGNUM).
4590 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4591 [(set (match_operand:HILO 0 "register_operand" "=x")
4592 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4593 (match_operand:GPR 2 "register_operand" "l")]
4597 [(set_attr "move_type" "mthilo")
4598 (set_attr "mode" "SI")])
4600 ;; Emit a doubleword move in which exactly one of the operands is
4601 ;; a floating-point register. We can't just emit two normal moves
4602 ;; because of the constraints imposed by the FPU register model;
4603 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4604 ;; the FPR whole and use special patterns to refer to each word of
4605 ;; the other operand.
4607 (define_expand "move_doubleword_fpr<mode>"
4608 [(set (match_operand:SPLITF 0)
4609 (match_operand:SPLITF 1))]
4612 if (FP_REG_RTX_P (operands[0]))
4614 rtx low = mips_subword (operands[1], 0);
4615 rtx high = mips_subword (operands[1], 1);
4616 emit_insn (gen_load_low<mode> (operands[0], low));
4617 if (TARGET_FLOAT64 && !TARGET_64BIT)
4618 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4620 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4624 rtx low = mips_subword (operands[0], 0);
4625 rtx high = mips_subword (operands[0], 1);
4626 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4627 if (TARGET_FLOAT64 && !TARGET_64BIT)
4628 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4630 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4635 ;; Load the low word of operand 0 with operand 1.
4636 (define_insn "load_low<mode>"
4637 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4638 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4642 operands[0] = mips_subword (operands[0], 0);
4643 return mips_output_move (operands[0], operands[1]);
4645 [(set_attr "move_type" "mtc,fpload")
4646 (set_attr "mode" "<HALFMODE>")])
4648 ;; Load the high word of operand 0 from operand 1, preserving the value
4650 (define_insn "load_high<mode>"
4651 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4652 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4653 (match_operand:SPLITF 2 "register_operand" "0,0")]
4657 operands[0] = mips_subword (operands[0], 1);
4658 return mips_output_move (operands[0], operands[1]);
4660 [(set_attr "move_type" "mtc,fpload")
4661 (set_attr "mode" "<HALFMODE>")])
4663 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4664 ;; high word and 0 to store the low word.
4665 (define_insn "store_word<mode>"
4666 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4667 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4668 (match_operand 2 "const_int_operand")]
4669 UNSPEC_STORE_WORD))]
4672 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4673 return mips_output_move (operands[0], operands[1]);
4675 [(set_attr "move_type" "mfc,fpstore")
4676 (set_attr "mode" "<HALFMODE>")])
4678 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4679 ;; value in the low word.
4680 (define_insn "mthc1<mode>"
4681 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4682 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4683 (match_operand:SPLITF 2 "register_operand" "0")]
4685 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4687 [(set_attr "move_type" "mtc")
4688 (set_attr "mode" "<HALFMODE>")])
4690 ;; Move high word of operand 1 to operand 0 using mfhc1.
4691 (define_insn "mfhc1<mode>"
4692 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4693 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4695 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4697 [(set_attr "move_type" "mfc")
4698 (set_attr "mode" "<HALFMODE>")])
4700 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4701 (define_expand "load_const_gp_<mode>"
4702 [(set (match_operand:P 0 "register_operand" "=d")
4703 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4705 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4706 ;; of _gp from the start of this function. Operand 1 is the incoming
4707 ;; function address.
4708 (define_insn_and_split "loadgp_newabi_<mode>"
4709 [(set (match_operand:P 0 "register_operand" "=d")
4710 (unspec:P [(match_operand:P 1)
4711 (match_operand:P 2 "register_operand" "d")]
4713 "mips_current_loadgp_style () == LOADGP_NEWABI"
4714 { return mips_must_initialize_gp_p () ? "#" : ""; }
4715 "&& mips_must_initialize_gp_p ()"
4716 [(set (match_dup 0) (match_dup 3))
4717 (set (match_dup 0) (match_dup 4))
4718 (set (match_dup 0) (match_dup 5))]
4720 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4721 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4722 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4724 [(set_attr "type" "ghost")])
4726 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4727 (define_insn_and_split "loadgp_absolute_<mode>"
4728 [(set (match_operand:P 0 "register_operand" "=d")
4729 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4730 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4731 { return mips_must_initialize_gp_p () ? "#" : ""; }
4732 "&& mips_must_initialize_gp_p ()"
4735 mips_emit_move (operands[0], operands[1]);
4738 [(set_attr "type" "ghost")])
4740 ;; This blockage instruction prevents the gp load from being
4741 ;; scheduled after an implicit use of gp. It also prevents
4742 ;; the load from being deleted as dead.
4743 (define_insn "loadgp_blockage"
4744 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4747 [(set_attr "type" "ghost")])
4749 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4750 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4751 (define_insn_and_split "loadgp_rtp_<mode>"
4752 [(set (match_operand:P 0 "register_operand" "=d")
4753 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
4754 (match_operand:P 2 "symbol_ref_operand")]
4756 "mips_current_loadgp_style () == LOADGP_RTP"
4757 { return mips_must_initialize_gp_p () ? "#" : ""; }
4758 "&& mips_must_initialize_gp_p ()"
4759 [(set (match_dup 0) (high:P (match_dup 3)))
4760 (set (match_dup 0) (unspec:P [(match_dup 0)
4761 (match_dup 3)] UNSPEC_LOAD_GOT))
4762 (set (match_dup 0) (unspec:P [(match_dup 0)
4763 (match_dup 4)] UNSPEC_LOAD_GOT))]
4765 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4766 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4768 [(set_attr "type" "ghost")])
4770 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4771 ;; global pointer and operand 1 is the MIPS16 register that holds
4772 ;; the required value.
4773 (define_insn_and_split "copygp_mips16"
4774 [(set (match_operand:SI 0 "register_operand" "=y")
4775 (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
4778 { return mips_must_initialize_gp_p () ? "#" : ""; }
4779 "&& mips_must_initialize_gp_p ()"
4780 [(set (match_dup 0) (match_dup 1))]
4782 [(set_attr "type" "ghost")])
4784 ;; A placeholder for where the cprestore instruction should go,
4785 ;; if we decide we need one. Operand 0 and operand 1 are as for
4786 ;; "cprestore". Operand 2 is a register that holds the gp value.
4788 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
4789 ;; otherwise any register that holds the correct value will do.
4790 (define_insn_and_split "potential_cprestore"
4791 [(set (match_operand:SI 0 "cprestore_save_slot_operand" "=X,X")
4792 (unspec:SI [(match_operand:SI 1 "const_int_operand" "I,i")
4793 (match_operand:SI 2 "register_operand" "d,d")]
4794 UNSPEC_POTENTIAL_CPRESTORE))
4795 (clobber (match_operand:SI 3 "scratch_operand" "=X,&d"))]
4796 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
4797 { return mips_must_initialize_gp_p () ? "#" : ""; }
4798 "mips_must_initialize_gp_p ()"
4801 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
4802 operands[2], operands[3]);
4805 [(set_attr "type" "ghost")])
4807 ;; Emit a .cprestore directive, which normally expands to a single store
4808 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
4809 ;; for the cprestore slot. Operand 1 is the offset of the slot from
4810 ;; the stack pointer. (This is redundant with operand 0, but it makes
4811 ;; things a little simpler.)
4812 (define_insn "cprestore"
4813 [(set (match_operand:SI 0 "cprestore_save_slot_operand" "=X,X")
4814 (unspec:SI [(match_operand:SI 1 "const_int_operand" "I,i")
4817 "TARGET_CPRESTORE_DIRECTIVE"
4819 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
4820 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
4822 return ".cprestore\t%1";
4824 [(set_attr "type" "store")
4825 (set_attr "length" "4,12")])
4827 (define_insn "use_cprestore"
4828 [(set (reg:SI CPRESTORE_SLOT_REGNUM)
4829 (match_operand:SI 0 "cprestore_load_slot_operand"))]
4832 [(set_attr "type" "ghost")])
4834 ;; Expand in-line code to clear the instruction cache between operand[0] and
4836 (define_expand "clear_cache"
4837 [(match_operand 0 "pmode_register_operand")
4838 (match_operand 1 "pmode_register_operand")]
4844 mips_expand_synci_loop (operands[0], operands[1]);
4845 emit_insn (gen_sync ());
4846 emit_insn (Pmode == SImode
4847 ? gen_clear_hazard_si ()
4848 : gen_clear_hazard_di ());
4850 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4852 rtx len = gen_reg_rtx (Pmode);
4853 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4854 MIPS_ICACHE_SYNC (operands[0], len);
4860 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4862 { return mips_output_sync (); })
4864 (define_insn "synci"
4865 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4870 (define_insn "rdhwr_synci_step_<mode>"
4871 [(set (match_operand:P 0 "register_operand" "=d")
4872 (unspec_volatile [(const_int 1)]
4877 (define_insn "clear_hazard_<mode>"
4878 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4879 (clobber (reg:P RETURN_ADDR_REGNUM))]
4882 return "%(%<bal\t1f\n"
4884 "1:\t<d>addiu\t$31,$31,12\n"
4888 [(set_attr "length" "20")])
4890 ;; Cache operations for R4000-style caches.
4891 (define_insn "mips_cache"
4892 [(set (mem:BLK (scratch))
4893 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4894 (match_operand:QI 1 "address_operand" "p")]
4895 UNSPEC_MIPS_CACHE))]
4899 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4900 ;; operation. We keep the pattern distinct so that we can identify
4901 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4902 ;; the operation is never inserted into a delay slot.
4903 (define_insn "r10k_cache_barrier"
4904 [(set (mem:BLK (scratch))
4905 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4908 [(set_attr "can_delay" "no")])
4910 ;; Block moves, see mips.c for more details.
4911 ;; Argument 0 is the destination
4912 ;; Argument 1 is the source
4913 ;; Argument 2 is the length
4914 ;; Argument 3 is the alignment
4916 (define_expand "movmemsi"
4917 [(parallel [(set (match_operand:BLK 0 "general_operand")
4918 (match_operand:BLK 1 "general_operand"))
4919 (use (match_operand:SI 2 ""))
4920 (use (match_operand:SI 3 "const_int_operand"))])]
4921 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4923 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4930 ;; ....................
4934 ;; ....................
4936 (define_expand "<optab><mode>3"
4937 [(set (match_operand:GPR 0 "register_operand")
4938 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4939 (match_operand:SI 2 "arith_operand")))]
4942 /* On the mips16, a shift of more than 8 is a four byte instruction,
4943 so, for a shift between 8 and 16, it is just as fast to do two
4944 shifts of 8 or less. If there is a lot of shifting going on, we
4945 may win in CSE. Otherwise combine will put the shifts back
4946 together again. This can be called by mips_function_arg, so we must
4947 be careful not to allocate a new register if we've reached the
4951 && CONST_INT_P (operands[2])
4952 && INTVAL (operands[2]) > 8
4953 && INTVAL (operands[2]) <= 16
4954 && !reload_in_progress
4955 && !reload_completed)
4957 rtx temp = gen_reg_rtx (<MODE>mode);
4959 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4960 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4961 GEN_INT (INTVAL (operands[2]) - 8)));
4966 (define_insn "*<optab><mode>3"
4967 [(set (match_operand:GPR 0 "register_operand" "=d")
4968 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4969 (match_operand:SI 2 "arith_operand" "dI")))]
4972 if (CONST_INT_P (operands[2]))
4973 operands[2] = GEN_INT (INTVAL (operands[2])
4974 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4976 return "<d><insn>\t%0,%1,%2";
4978 [(set_attr "type" "shift")
4979 (set_attr "mode" "<MODE>")])
4981 (define_insn "*<optab>si3_extend"
4982 [(set (match_operand:DI 0 "register_operand" "=d")
4984 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4985 (match_operand:SI 2 "arith_operand" "dI"))))]
4986 "TARGET_64BIT && !TARGET_MIPS16"
4988 if (CONST_INT_P (operands[2]))
4989 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4991 return "<insn>\t%0,%1,%2";
4993 [(set_attr "type" "shift")
4994 (set_attr "mode" "SI")])
4996 (define_insn "*<optab>si3_mips16"
4997 [(set (match_operand:SI 0 "register_operand" "=d,d")
4998 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4999 (match_operand:SI 2 "arith_operand" "d,I")))]
5002 if (which_alternative == 0)
5003 return "<insn>\t%0,%2";
5005 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5006 return "<insn>\t%0,%1,%2";
5008 [(set_attr "type" "shift")
5009 (set_attr "mode" "SI")
5010 (set_attr_alternative "length"
5012 (if_then_else (match_operand 2 "m16_uimm3_b")
5016 ;; We need separate DImode MIPS16 patterns because of the irregularity
5018 (define_insn "*ashldi3_mips16"
5019 [(set (match_operand:DI 0 "register_operand" "=d,d")
5020 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
5021 (match_operand:SI 2 "arith_operand" "d,I")))]
5022 "TARGET_64BIT && TARGET_MIPS16"
5024 if (which_alternative == 0)
5025 return "dsll\t%0,%2";
5027 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5028 return "dsll\t%0,%1,%2";
5030 [(set_attr "type" "shift")
5031 (set_attr "mode" "DI")
5032 (set_attr_alternative "length"
5034 (if_then_else (match_operand 2 "m16_uimm3_b")
5038 (define_insn "*ashrdi3_mips16"
5039 [(set (match_operand:DI 0 "register_operand" "=d,d")
5040 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5041 (match_operand:SI 2 "arith_operand" "d,I")))]
5042 "TARGET_64BIT && TARGET_MIPS16"
5044 if (CONST_INT_P (operands[2]))
5045 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5047 return "dsra\t%0,%2";
5049 [(set_attr "type" "shift")
5050 (set_attr "mode" "DI")
5051 (set_attr_alternative "length"
5053 (if_then_else (match_operand 2 "m16_uimm3_b")
5057 (define_insn "*lshrdi3_mips16"
5058 [(set (match_operand:DI 0 "register_operand" "=d,d")
5059 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5060 (match_operand:SI 2 "arith_operand" "d,I")))]
5061 "TARGET_64BIT && TARGET_MIPS16"
5063 if (CONST_INT_P (operands[2]))
5064 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5066 return "dsrl\t%0,%2";
5068 [(set_attr "type" "shift")
5069 (set_attr "mode" "DI")
5070 (set_attr_alternative "length"
5072 (if_then_else (match_operand 2 "m16_uimm3_b")
5076 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5079 [(set (match_operand:GPR 0 "d_operand")
5080 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5081 (match_operand:GPR 2 "const_int_operand")))]
5082 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5083 && INTVAL (operands[2]) > 8
5084 && INTVAL (operands[2]) <= 16"
5085 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5086 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5087 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5089 ;; If we load a byte on the mips16 as a bitfield, the resulting
5090 ;; sequence of instructions is too complicated for combine, because it
5091 ;; involves four instructions: a load, a shift, a constant load into a
5092 ;; register, and an and (the key problem here is that the mips16 does
5093 ;; not have and immediate). We recognize a shift of a load in order
5094 ;; to make it simple enough for combine to understand.
5096 ;; The length here is the worst case: the length of the split version
5097 ;; will be more accurate.
5098 (define_insn_and_split ""
5099 [(set (match_operand:SI 0 "register_operand" "=d")
5100 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5101 (match_operand:SI 2 "immediate_operand" "I")))]
5105 [(set (match_dup 0) (match_dup 1))
5106 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5108 [(set_attr "type" "load")
5109 (set_attr "mode" "SI")
5110 (set_attr "length" "16")])
5112 (define_insn "rotr<mode>3"
5113 [(set (match_operand:GPR 0 "register_operand" "=d")
5114 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5115 (match_operand:SI 2 "arith_operand" "dI")))]
5118 if (CONST_INT_P (operands[2]))
5119 gcc_assert (INTVAL (operands[2]) >= 0
5120 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5122 return "<d>ror\t%0,%1,%2";
5124 [(set_attr "type" "shift")
5125 (set_attr "mode" "<MODE>")])
5128 ;; ....................
5130 ;; CONDITIONAL BRANCHES
5132 ;; ....................
5134 ;; Conditional branches on floating-point equality tests.
5136 (define_insn "*branch_fp"
5139 (match_operator 1 "equality_operator"
5140 [(match_operand:CC 2 "register_operand" "z")
5142 (label_ref (match_operand 0 "" ""))
5146 return mips_output_conditional_branch (insn, operands,
5147 MIPS_BRANCH ("b%F1", "%Z2%0"),
5148 MIPS_BRANCH ("b%W1", "%Z2%0"));
5150 [(set_attr "type" "branch")])
5152 (define_insn "*branch_fp_inverted"
5155 (match_operator 1 "equality_operator"
5156 [(match_operand:CC 2 "register_operand" "z")
5159 (label_ref (match_operand 0 "" ""))))]
5162 return mips_output_conditional_branch (insn, operands,
5163 MIPS_BRANCH ("b%W1", "%Z2%0"),
5164 MIPS_BRANCH ("b%F1", "%Z2%0"));
5166 [(set_attr "type" "branch")])
5168 ;; Conditional branches on ordered comparisons with zero.
5170 (define_insn "*branch_order<mode>"
5173 (match_operator 1 "order_operator"
5174 [(match_operand:GPR 2 "register_operand" "d")
5176 (label_ref (match_operand 0 "" ""))
5179 { return mips_output_order_conditional_branch (insn, operands, false); }
5180 [(set_attr "type" "branch")])
5182 (define_insn "*branch_order<mode>_inverted"
5185 (match_operator 1 "order_operator"
5186 [(match_operand:GPR 2 "register_operand" "d")
5189 (label_ref (match_operand 0 "" ""))))]
5191 { return mips_output_order_conditional_branch (insn, operands, true); }
5192 [(set_attr "type" "branch")])
5194 ;; Conditional branch on equality comparison.
5196 (define_insn "*branch_equality<mode>"
5199 (match_operator 1 "equality_operator"
5200 [(match_operand:GPR 2 "register_operand" "d")
5201 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5202 (label_ref (match_operand 0 "" ""))
5206 return mips_output_conditional_branch (insn, operands,
5207 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5208 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5210 [(set_attr "type" "branch")])
5212 (define_insn "*branch_equality<mode>_inverted"
5215 (match_operator 1 "equality_operator"
5216 [(match_operand:GPR 2 "register_operand" "d")
5217 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5219 (label_ref (match_operand 0 "" ""))))]
5222 return mips_output_conditional_branch (insn, operands,
5223 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5224 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5226 [(set_attr "type" "branch")])
5230 (define_insn "*branch_equality<mode>_mips16"
5233 (match_operator 0 "equality_operator"
5234 [(match_operand:GPR 1 "register_operand" "d,t")
5236 (match_operand 2 "pc_or_label_operand" "")
5237 (match_operand 3 "pc_or_label_operand" "")))]
5240 if (operands[2] != pc_rtx)
5242 if (which_alternative == 0)
5243 return "b%C0z\t%1,%2";
5245 return "bt%C0z\t%2";
5249 if (which_alternative == 0)
5250 return "b%N0z\t%1,%3";
5252 return "bt%N0z\t%3";
5255 [(set_attr "type" "branch")])
5257 (define_expand "cbranch<mode>4"
5259 (if_then_else (match_operator 0 "comparison_operator"
5260 [(match_operand:GPR 1 "register_operand")
5261 (match_operand:GPR 2 "nonmemory_operand")])
5262 (label_ref (match_operand 3 ""))
5266 mips_expand_conditional_branch (operands);
5270 (define_expand "cbranch<mode>4"
5272 (if_then_else (match_operator 0 "comparison_operator"
5273 [(match_operand:SCALARF 1 "register_operand")
5274 (match_operand:SCALARF 2 "register_operand")])
5275 (label_ref (match_operand 3 ""))
5279 mips_expand_conditional_branch (operands);
5283 ;; Used to implement built-in functions.
5284 (define_expand "condjump"
5286 (if_then_else (match_operand 0)
5287 (label_ref (match_operand 1))
5290 ;; Branch if bit is set/clear.
5292 (define_insn "*branch_bit<bbv><mode>"
5295 (equality_op (zero_extract:GPR
5296 (match_operand:GPR 1 "register_operand" "d")
5298 (match_operand 2 "const_int_operand" ""))
5300 (label_ref (match_operand 0 ""))
5302 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5305 mips_output_conditional_branch (insn, operands,
5306 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5307 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5309 [(set_attr "type" "branch")
5310 (set_attr "branch_likely" "no")])
5312 (define_insn "*branch_bit<bbv><mode>_inverted"
5315 (equality_op (zero_extract:GPR
5316 (match_operand:GPR 1 "register_operand" "d")
5318 (match_operand 2 "const_int_operand" ""))
5321 (label_ref (match_operand 0 ""))))]
5322 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5325 mips_output_conditional_branch (insn, operands,
5326 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5327 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5329 [(set_attr "type" "branch")
5330 (set_attr "branch_likely" "no")])
5333 ;; ....................
5335 ;; SETTING A REGISTER FROM A COMPARISON
5337 ;; ....................
5339 ;; Destination is always set in SI mode.
5341 (define_expand "cstore<mode>4"
5342 [(set (match_operand:SI 0 "register_operand")
5343 (match_operator:SI 1 "mips_cstore_operator"
5344 [(match_operand:GPR 2 "register_operand")
5345 (match_operand:GPR 3 "nonmemory_operand")]))]
5348 mips_expand_scc (operands);
5352 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5353 [(set (match_operand:GPR2 0 "register_operand" "=d")
5354 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5356 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5358 [(set_attr "type" "slt")
5359 (set_attr "mode" "<GPR:MODE>")])
5361 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5362 [(set (match_operand:GPR2 0 "register_operand" "=t")
5363 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5365 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5367 [(set_attr "type" "slt")
5368 (set_attr "mode" "<GPR:MODE>")])
5370 ;; Generate sltiu unless using seq results in better code.
5371 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5372 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5373 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5374 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5380 [(set_attr "type" "slt")
5381 (set_attr "mode" "<GPR:MODE>")])
5383 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5384 [(set (match_operand:GPR2 0 "register_operand" "=d")
5385 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5387 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5389 [(set_attr "type" "slt")
5390 (set_attr "mode" "<GPR:MODE>")])
5392 ;; Generate sltu unless using sne results in better code.
5393 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5394 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5395 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5396 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5402 [(set_attr "type" "slt")
5403 (set_attr "mode" "<GPR:MODE>")])
5405 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5406 [(set (match_operand:GPR2 0 "register_operand" "=d")
5407 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5408 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5411 [(set_attr "type" "slt")
5412 (set_attr "mode" "<GPR:MODE>")])
5414 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5415 [(set (match_operand:GPR2 0 "register_operand" "=t")
5416 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5417 (match_operand:GPR 2 "register_operand" "d")))]
5420 [(set_attr "type" "slt")
5421 (set_attr "mode" "<GPR:MODE>")])
5423 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5424 [(set (match_operand:GPR2 0 "register_operand" "=d")
5425 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5429 [(set_attr "type" "slt")
5430 (set_attr "mode" "<GPR:MODE>")])
5432 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5433 [(set (match_operand:GPR2 0 "register_operand" "=d")
5434 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5435 (match_operand:GPR 2 "arith_operand" "dI")))]
5438 [(set_attr "type" "slt")
5439 (set_attr "mode" "<GPR:MODE>")])
5441 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5442 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5443 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5444 (match_operand:GPR 2 "arith_operand" "d,I")))]
5447 [(set_attr "type" "slt")
5448 (set_attr "mode" "<GPR:MODE>")
5449 (set_attr_alternative "length"
5451 (if_then_else (match_operand 2 "m16_uimm8_1")
5455 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5456 [(set (match_operand:GPR2 0 "register_operand" "=d")
5457 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5458 (match_operand:GPR 2 "sle_operand" "")))]
5461 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5462 return "slt<u>\t%0,%1,%2";
5464 [(set_attr "type" "slt")
5465 (set_attr "mode" "<GPR:MODE>")])
5467 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5468 [(set (match_operand:GPR2 0 "register_operand" "=t")
5469 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5470 (match_operand:GPR 2 "sle_operand" "")))]
5473 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5474 return "slt<u>\t%1,%2";
5476 [(set_attr "type" "slt")
5477 (set_attr "mode" "<GPR:MODE>")
5478 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5483 ;; ....................
5485 ;; FLOATING POINT COMPARISONS
5487 ;; ....................
5489 (define_insn "s<code>_<mode>"
5490 [(set (match_operand:CC 0 "register_operand" "=z")
5491 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5492 (match_operand:SCALARF 2 "register_operand" "f")))]
5494 "c.<fcond>.<fmt>\t%Z0%1,%2"
5495 [(set_attr "type" "fcmp")
5496 (set_attr "mode" "FPSW")])
5498 (define_insn "s<code>_<mode>"
5499 [(set (match_operand:CC 0 "register_operand" "=z")
5500 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5501 (match_operand:SCALARF 2 "register_operand" "f")))]
5503 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5504 [(set_attr "type" "fcmp")
5505 (set_attr "mode" "FPSW")])
5508 ;; ....................
5510 ;; UNCONDITIONAL BRANCHES
5512 ;; ....................
5514 ;; Unconditional branches.
5516 (define_expand "jump"
5518 (label_ref (match_operand 0)))])
5520 (define_insn "*jump_absolute"
5522 (label_ref (match_operand 0)))]
5523 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5524 { return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); }
5525 [(set_attr "type" "jump")])
5527 (define_insn "*jump_pic"
5529 (label_ref (match_operand 0)))]
5530 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5532 if (get_attr_length (insn) <= 8)
5533 return "%*b\t%l0%/";
5536 mips_output_load_label (operands[0]);
5537 return "%*jr\t%@%/%]";
5540 [(set_attr "type" "branch")])
5542 ;; We need a different insn for the mips16, because a mips16 branch
5543 ;; does not have a delay slot.
5545 (define_insn "*jump_mips16"
5547 (label_ref (match_operand 0 "" "")))]
5550 [(set_attr "type" "branch")])
5552 (define_expand "indirect_jump"
5553 [(set (pc) (match_operand 0 "register_operand"))]
5556 operands[0] = force_reg (Pmode, operands[0]);
5557 if (Pmode == SImode)
5558 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5560 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5564 (define_insn "indirect_jump<mode>"
5565 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5568 [(set_attr "type" "jump")
5569 (set_attr "mode" "none")])
5571 (define_expand "tablejump"
5573 (match_operand 0 "register_operand"))
5574 (use (label_ref (match_operand 1 "")))]
5577 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5578 operands[0] = expand_binop (Pmode, add_optab,
5579 convert_to_mode (Pmode, operands[0], false),
5580 gen_rtx_LABEL_REF (Pmode, operands[1]),
5582 else if (TARGET_GPWORD)
5583 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5584 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5585 else if (TARGET_RTP_PIC)
5587 /* When generating RTP PIC, we use case table entries that are relative
5588 to the start of the function. Add the function's address to the
5590 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5591 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5592 start, 0, 0, OPTAB_WIDEN);
5595 if (Pmode == SImode)
5596 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5598 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5602 (define_insn "tablejump<mode>"
5604 (match_operand:P 0 "register_operand" "d"))
5605 (use (label_ref (match_operand 1 "" "")))]
5608 [(set_attr "type" "jump")
5609 (set_attr "mode" "none")])
5611 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5612 ;; While it is possible to either pull it off the stack (in the
5613 ;; o32 case) or recalculate it given t9 and our target label,
5614 ;; it takes 3 or 4 insns to do so.
5616 (define_expand "builtin_setjmp_setup"
5617 [(use (match_operand 0 "register_operand"))]
5622 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5623 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5627 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5628 ;; that older code did recalculate the gp from $25. Continue to jump through
5629 ;; $25 for compatibility (we lose nothing by doing so).
5631 (define_expand "builtin_longjmp"
5632 [(use (match_operand 0 "register_operand"))]
5635 /* The elements of the buffer are, in order: */
5636 int W = GET_MODE_SIZE (Pmode);
5637 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5638 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5639 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5640 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5641 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5642 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5643 The target is bound to be using $28 as the global pointer
5644 but the current function might not be. */
5645 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5647 /* This bit is similar to expand_builtin_longjmp except that it
5648 restores $gp as well. */
5649 mips_emit_move (hard_frame_pointer_rtx, fp);
5650 mips_emit_move (pv, lab);
5651 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5652 mips_emit_move (gp, gpv);
5653 emit_use (hard_frame_pointer_rtx);
5654 emit_use (stack_pointer_rtx);
5656 emit_indirect_jump (pv);
5661 ;; ....................
5663 ;; Function prologue/epilogue
5665 ;; ....................
5668 (define_expand "prologue"
5672 mips_expand_prologue ();
5676 ;; Block any insns from being moved before this point, since the
5677 ;; profiling call to mcount can use various registers that aren't
5678 ;; saved or used to pass arguments.
5680 (define_insn "blockage"
5681 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5684 [(set_attr "type" "ghost")
5685 (set_attr "mode" "none")])
5687 (define_expand "epilogue"
5691 mips_expand_epilogue (false);
5695 (define_expand "sibcall_epilogue"
5699 mips_expand_epilogue (true);
5703 ;; Trivial return. Make it look like a normal return insn as that
5704 ;; allows jump optimizations to work better.
5706 (define_expand "return"
5708 "mips_can_use_return_insn ()"
5709 { mips_expand_before_return (); })
5711 (define_insn "*return"
5713 "mips_can_use_return_insn ()"
5715 [(set_attr "type" "jump")
5716 (set_attr "mode" "none")])
5720 (define_insn "return_internal"
5722 (use (match_operand 0 "pmode_register_operand" ""))]
5725 [(set_attr "type" "jump")
5726 (set_attr "mode" "none")])
5728 ;; Exception return.
5729 (define_insn "mips_eret"
5731 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
5734 [(set_attr "type" "trap")
5735 (set_attr "mode" "none")])
5737 ;; Debug exception return.
5738 (define_insn "mips_deret"
5740 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
5743 [(set_attr "type" "trap")
5744 (set_attr "mode" "none")])
5746 ;; Disable interrupts.
5747 (define_insn "mips_di"
5748 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
5751 [(set_attr "type" "trap")
5752 (set_attr "mode" "none")])
5754 ;; Execution hazard barrier.
5755 (define_insn "mips_ehb"
5756 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
5759 [(set_attr "type" "trap")
5760 (set_attr "mode" "none")])
5762 ;; Read GPR from previous shadow register set.
5763 (define_insn "mips_rdpgpr"
5764 [(set (match_operand:SI 0 "register_operand" "=d")
5765 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
5769 [(set_attr "type" "move")
5770 (set_attr "mode" "SI")])
5772 ;; Move involving COP0 registers.
5773 (define_insn "cop0_move"
5774 [(set (match_operand:SI 0 "register_operand" "=B,d")
5775 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
5778 { return mips_output_move (operands[0], operands[1]); }
5779 [(set_attr "type" "mtc,mfc")
5780 (set_attr "mode" "SI")])
5782 ;; This is used in compiling the unwind routines.
5783 (define_expand "eh_return"
5784 [(use (match_operand 0 "general_operand"))]
5787 if (GET_MODE (operands[0]) != word_mode)
5788 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5790 emit_insn (gen_eh_set_lr_di (operands[0]));
5792 emit_insn (gen_eh_set_lr_si (operands[0]));
5796 ;; Clobber the return address on the stack. We can't expand this
5797 ;; until we know where it will be put in the stack frame.
5799 (define_insn "eh_set_lr_si"
5800 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5801 (clobber (match_scratch:SI 1 "=&d"))]
5805 (define_insn "eh_set_lr_di"
5806 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5807 (clobber (match_scratch:DI 1 "=&d"))]
5812 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5813 (clobber (match_scratch 1))]
5817 mips_set_return_address (operands[0], operands[1]);
5821 (define_expand "exception_receiver"
5825 /* See the comment above load_call<mode> for details. */
5826 emit_insn (gen_set_got_version ());
5828 /* If we have a call-clobbered $gp, restore it from its save slot. */
5829 if (HAVE_restore_gp)
5830 emit_insn (gen_restore_gp ());
5834 (define_expand "nonlocal_goto_receiver"
5838 /* See the comment above load_call<mode> for details. */
5839 emit_insn (gen_set_got_version ());
5843 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5844 ;; volatile until all uses of $28 are exposed.
5845 (define_insn_and_split "restore_gp"
5847 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5848 (clobber (match_scratch:SI 0 "=&d"))]
5849 "TARGET_CALL_CLOBBERED_GP"
5851 "&& epilogue_completed"
5854 mips_restore_gp_from_cprestore_slot (operands[0]);
5857 [(set_attr "type" "ghost")])
5859 ;; Move between $gp and its register save slot.
5860 (define_insn_and_split "move_gp<mode>"
5861 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
5862 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
5865 { return mips_must_initialize_gp_p () ? "#" : ""; }
5866 "mips_must_initialize_gp_p ()"
5869 mips_emit_move (operands[0], operands[1]);
5872 [(set_attr "type" "ghost")])
5875 ;; ....................
5879 ;; ....................
5881 ;; Instructions to load a call address from the GOT. The address might
5882 ;; point to a function or to a lazy binding stub. In the latter case,
5883 ;; the stub will use the dynamic linker to resolve the function, which
5884 ;; in turn will change the GOT entry to point to the function's real
5887 ;; This means that every call, even pure and constant ones, can
5888 ;; potentially modify the GOT entry. And once a stub has been called,
5889 ;; we must not call it again.
5891 ;; We represent this restriction using an imaginary, fixed, call-saved
5892 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5893 ;; live throughout the function and to change its value after every
5894 ;; potential call site. This stops any rtx value that uses the register
5895 ;; from being computed before an earlier call. To do this, we:
5897 ;; - Ensure that the register is live on entry to the function,
5898 ;; so that it is never thought to be used uninitalized.
5900 ;; - Ensure that the register is live on exit from the function,
5901 ;; so that it is live throughout.
5903 ;; - Make each call (lazily-bound or not) use the current value
5904 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5905 ;; not moved across call boundaries.
5907 ;; - Add "ghost" definitions of the register to the beginning of
5908 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5909 ;; edges may involve calls that normal paths don't. (E.g. the
5910 ;; unwinding code that handles a non-call exception may change
5911 ;; lazily-bound GOT entries.) We do this by making the
5912 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5913 ;; a set_got_version instruction.
5915 ;; - After each call (lazily-bound or not), use a "ghost"
5916 ;; update_got_version instruction to change the register's value.
5917 ;; This instruction mimics the _possible_ effect of the dynamic
5918 ;; resolver during the call and it remains live even if the call
5919 ;; itself becomes dead.
5921 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5922 ;; The register is therefore not a valid register_operand
5923 ;; and cannot be moved to or from other registers.
5925 (define_insn "load_call<mode>"
5926 [(set (match_operand:P 0 "register_operand" "=d")
5927 (unspec:P [(match_operand:P 1 "register_operand" "d")
5928 (match_operand:P 2 "immediate_operand" "")
5929 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5931 "<load>\t%0,%R2(%1)"
5932 [(set_attr "got" "load")
5933 (set_attr "mode" "<MODE>")])
5935 (define_insn "set_got_version"
5936 [(set (reg:SI GOT_VERSION_REGNUM)
5937 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5940 [(set_attr "type" "ghost")])
5942 (define_insn "update_got_version"
5943 [(set (reg:SI GOT_VERSION_REGNUM)
5944 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5947 [(set_attr "type" "ghost")])
5949 ;; Sibling calls. All these patterns use jump instructions.
5951 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5952 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5953 ;; is defined in terms of call_insn_operand, the same is true of the
5956 ;; When we use an indirect jump, we need a register that will be
5957 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5958 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5959 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5962 (define_expand "sibcall"
5963 [(parallel [(call (match_operand 0 "")
5964 (match_operand 1 ""))
5965 (use (match_operand 2 "")) ;; next_arg_reg
5966 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5969 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5970 operands[1], operands[2], false);
5974 (define_insn "sibcall_internal"
5975 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5976 (match_operand 1 "" ""))]
5977 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5978 { return MIPS_CALL ("j", operands, 0, 1); }
5979 [(set_attr "type" "call")])
5981 (define_expand "sibcall_value"
5982 [(parallel [(set (match_operand 0 "")
5983 (call (match_operand 1 "")
5984 (match_operand 2 "")))
5985 (use (match_operand 3 ""))])] ;; next_arg_reg
5988 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5989 operands[2], operands[3], false);
5993 (define_insn "sibcall_value_internal"
5994 [(set (match_operand 0 "register_operand" "")
5995 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5996 (match_operand 2 "" "")))]
5997 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5998 { return MIPS_CALL ("j", operands, 1, 2); }
5999 [(set_attr "type" "call")])
6001 (define_insn "sibcall_value_multiple_internal"
6002 [(set (match_operand 0 "register_operand" "")
6003 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6004 (match_operand 2 "" "")))
6005 (set (match_operand 3 "register_operand" "")
6006 (call (mem:SI (match_dup 1))
6008 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6009 { return MIPS_CALL ("j", operands, 1, 2); }
6010 [(set_attr "type" "call")])
6012 (define_expand "call"
6013 [(parallel [(call (match_operand 0 "")
6014 (match_operand 1 ""))
6015 (use (match_operand 2 "")) ;; next_arg_reg
6016 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6019 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6020 operands[1], operands[2], false);
6024 ;; This instruction directly corresponds to an assembly-language "jal".
6025 ;; There are four cases:
6028 ;; Both symbolic and register destinations are OK. The pattern
6029 ;; always expands to a single mips instruction.
6031 ;; - -mabicalls/-mno-explicit-relocs:
6032 ;; Again, both symbolic and register destinations are OK.
6033 ;; The call is treated as a multi-instruction black box.
6035 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6036 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6039 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6040 ;; Only "jal $25" is allowed. The call is actually two instructions:
6041 ;; "jalr $25" followed by an insn to reload $gp.
6043 ;; In the last case, we can generate the individual instructions with
6044 ;; a define_split. There are several things to be wary of:
6046 ;; - We can't expose the load of $gp before reload. If we did,
6047 ;; it might get removed as dead, but reload can introduce new
6048 ;; uses of $gp by rematerializing constants.
6050 ;; - We shouldn't restore $gp after calls that never return.
6051 ;; It isn't valid to insert instructions between a noreturn
6052 ;; call and the following barrier.
6054 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6055 ;; instruction preserves $gp and so have no effect on its liveness.
6056 ;; But once we generate the separate insns, it becomes obvious that
6057 ;; $gp is not live on entry to the call.
6059 (define_insn_and_split "call_internal"
6060 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6061 (match_operand 1 "" ""))
6062 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6064 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6065 "reload_completed && TARGET_SPLIT_CALLS"
6068 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6071 [(set_attr "jal" "indirect,direct")])
6073 (define_insn "call_split"
6074 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
6075 (match_operand 1 "" ""))
6076 (clobber (reg:SI RETURN_ADDR_REGNUM))
6077 (clobber (reg:SI 28))]
6078 "TARGET_SPLIT_CALLS"
6079 { return MIPS_CALL ("jal", operands, 0, 1); }
6080 [(set_attr "type" "call")])
6082 ;; A pattern for calls that must be made directly. It is used for
6083 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6084 ;; stub; the linker relies on the call relocation type to detect when
6085 ;; such redirection is needed.
6086 (define_insn_and_split "call_internal_direct"
6087 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6090 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6092 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6093 "reload_completed && TARGET_SPLIT_CALLS"
6096 mips_split_call (curr_insn,
6097 gen_call_direct_split (operands[0], operands[1]));
6100 [(set_attr "type" "call")])
6102 (define_insn "call_direct_split"
6103 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6106 (clobber (reg:SI RETURN_ADDR_REGNUM))
6107 (clobber (reg:SI 28))]
6108 "TARGET_SPLIT_CALLS"
6109 { return MIPS_CALL ("jal", operands, 0, -1); }
6110 [(set_attr "type" "call")])
6112 (define_expand "call_value"
6113 [(parallel [(set (match_operand 0 "")
6114 (call (match_operand 1 "")
6115 (match_operand 2 "")))
6116 (use (match_operand 3 ""))])] ;; next_arg_reg
6119 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6120 operands[2], operands[3], false);
6124 ;; See comment for call_internal.
6125 (define_insn_and_split "call_value_internal"
6126 [(set (match_operand 0 "register_operand" "")
6127 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6128 (match_operand 2 "" "")))
6129 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6131 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6132 "reload_completed && TARGET_SPLIT_CALLS"
6135 mips_split_call (curr_insn,
6136 gen_call_value_split (operands[0], operands[1],
6140 [(set_attr "jal" "indirect,direct")])
6142 (define_insn "call_value_split"
6143 [(set (match_operand 0 "register_operand" "")
6144 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6145 (match_operand 2 "" "")))
6146 (clobber (reg:SI RETURN_ADDR_REGNUM))
6147 (clobber (reg:SI 28))]
6148 "TARGET_SPLIT_CALLS"
6149 { return MIPS_CALL ("jal", operands, 1, 2); }
6150 [(set_attr "type" "call")])
6152 ;; See call_internal_direct.
6153 (define_insn_and_split "call_value_internal_direct"
6154 [(set (match_operand 0 "register_operand")
6155 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6158 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6160 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6161 "reload_completed && TARGET_SPLIT_CALLS"
6164 mips_split_call (curr_insn,
6165 gen_call_value_direct_split (operands[0], operands[1],
6169 [(set_attr "type" "call")])
6171 (define_insn "call_value_direct_split"
6172 [(set (match_operand 0 "register_operand")
6173 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6176 (clobber (reg:SI RETURN_ADDR_REGNUM))
6177 (clobber (reg:SI 28))]
6178 "TARGET_SPLIT_CALLS"
6179 { return MIPS_CALL ("jal", operands, 1, -1); }
6180 [(set_attr "type" "call")])
6182 ;; See comment for call_internal.
6183 (define_insn_and_split "call_value_multiple_internal"
6184 [(set (match_operand 0 "register_operand" "")
6185 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6186 (match_operand 2 "" "")))
6187 (set (match_operand 3 "register_operand" "")
6188 (call (mem:SI (match_dup 1))
6190 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6192 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6193 "reload_completed && TARGET_SPLIT_CALLS"
6196 mips_split_call (curr_insn,
6197 gen_call_value_multiple_split (operands[0], operands[1],
6198 operands[2], operands[3]));
6201 [(set_attr "jal" "indirect,direct")])
6203 (define_insn "call_value_multiple_split"
6204 [(set (match_operand 0 "register_operand" "")
6205 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6206 (match_operand 2 "" "")))
6207 (set (match_operand 3 "register_operand" "")
6208 (call (mem:SI (match_dup 1))
6210 (clobber (reg:SI RETURN_ADDR_REGNUM))
6211 (clobber (reg:SI 28))]
6212 "TARGET_SPLIT_CALLS"
6213 { return MIPS_CALL ("jal", operands, 1, 2); }
6214 [(set_attr "type" "call")])
6216 ;; Call subroutine returning any type.
6218 (define_expand "untyped_call"
6219 [(parallel [(call (match_operand 0 "")
6221 (match_operand 1 "")
6222 (match_operand 2 "")])]
6227 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6229 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6231 rtx set = XVECEXP (operands[2], 0, i);
6232 mips_emit_move (SET_DEST (set), SET_SRC (set));
6235 emit_insn (gen_blockage ());
6240 ;; ....................
6244 ;; ....................
6248 (define_insn "prefetch"
6249 [(prefetch (match_operand:QI 0 "address_operand" "p")
6250 (match_operand 1 "const_int_operand" "n")
6251 (match_operand 2 "const_int_operand" "n"))]
6252 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6254 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6255 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6256 return "ld\t$0,%a0";
6257 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6258 return "pref\t%1,%a0";
6260 [(set_attr "type" "prefetch")])
6262 (define_insn "*prefetch_indexed_<mode>"
6263 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6264 (match_operand:P 1 "register_operand" "d"))
6265 (match_operand 2 "const_int_operand" "n")
6266 (match_operand 3 "const_int_operand" "n"))]
6267 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6269 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6270 return "prefx\t%2,%1(%0)";
6272 [(set_attr "type" "prefetchx")])
6278 [(set_attr "type" "nop")
6279 (set_attr "mode" "none")])
6281 ;; Like nop, but commented out when outside a .set noreorder block.
6282 (define_insn "hazard_nop"
6286 if (mips_noreorder.nesting_level > 0)
6291 [(set_attr "type" "nop")])
6293 ;; MIPS4 Conditional move instructions.
6295 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6296 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6298 (match_operator:MOVECC 4 "equality_operator"
6299 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6301 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6302 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6307 [(set_attr "type" "condmove")
6308 (set_attr "mode" "<GPR:MODE>")])
6310 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6311 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6312 (if_then_else:SCALARF
6313 (match_operator:MOVECC 4 "equality_operator"
6314 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6316 (match_operand:SCALARF 2 "register_operand" "f,0")
6317 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6318 "ISA_HAS_FP_CONDMOVE"
6320 mov%T4.<fmt>\t%0,%2,%1
6321 mov%t4.<fmt>\t%0,%3,%1"
6322 [(set_attr "type" "condmove")
6323 (set_attr "mode" "<SCALARF:MODE>")])
6325 ;; These are the main define_expand's used to make conditional moves.
6327 (define_expand "mov<mode>cc"
6328 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6329 (set (match_operand:GPR 0 "register_operand")
6330 (if_then_else:GPR (match_dup 5)
6331 (match_operand:GPR 2 "reg_or_0_operand")
6332 (match_operand:GPR 3 "reg_or_0_operand")))]
6335 mips_expand_conditional_move (operands);
6339 (define_expand "mov<mode>cc"
6340 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6341 (set (match_operand:SCALARF 0 "register_operand")
6342 (if_then_else:SCALARF (match_dup 5)
6343 (match_operand:SCALARF 2 "register_operand")
6344 (match_operand:SCALARF 3 "register_operand")))]
6345 "ISA_HAS_FP_CONDMOVE"
6347 mips_expand_conditional_move (operands);
6352 ;; ....................
6354 ;; mips16 inline constant tables
6356 ;; ....................
6359 (define_insn "consttable_int"
6360 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6361 (match_operand 1 "const_int_operand" "")]
6362 UNSPEC_CONSTTABLE_INT)]
6365 assemble_integer (operands[0], INTVAL (operands[1]),
6366 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6369 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6371 (define_insn "consttable_float"
6372 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6373 UNSPEC_CONSTTABLE_FLOAT)]
6378 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6379 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6380 assemble_real (d, GET_MODE (operands[0]),
6381 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6384 [(set (attr "length")
6385 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6387 (define_insn "align"
6388 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6391 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6394 [(match_operand 0 "small_data_pattern")]
6397 { operands[0] = mips_rewrite_small_data (operands[0]); })
6400 ;; ....................
6402 ;; MIPS16e Save/Restore
6404 ;; ....................
6407 (define_insn "*mips16e_save_restore"
6408 [(match_parallel 0 ""
6409 [(set (match_operand:SI 1 "register_operand")
6410 (plus:SI (match_dup 1)
6411 (match_operand:SI 2 "const_int_operand")))])]
6412 "operands[1] == stack_pointer_rtx
6413 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6414 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6415 [(set_attr "type" "arith")
6416 (set_attr "extended_mips16" "yes")])
6418 ;; Thread-Local Storage
6420 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6421 ;; MIPS architecture defines this register, and no current
6422 ;; implementation provides it; instead, any OS which supports TLS is
6423 ;; expected to trap and emulate this instruction. rdhwr is part of the
6424 ;; MIPS 32r2 specification, but we use it on any architecture because
6425 ;; we expect it to be emulated. Use .set to force the assembler to
6428 ;; We do not use a constraint to force the destination to be $3
6429 ;; because $3 can appear explicitly as a function return value.
6430 ;; If we leave the use of $3 implicit in the constraints until
6431 ;; reload, we may end up making a $3 return value live across
6432 ;; the instruction, leading to a spill failure when reloading it.
6433 (define_insn_and_split "tls_get_tp_<mode>"
6434 [(set (match_operand:P 0 "register_operand" "=d")
6435 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6436 (clobber (reg:P TLS_GET_TP_REGNUM))]
6437 "HAVE_AS_TLS && !TARGET_MIPS16"
6439 "&& reload_completed"
6440 [(set (reg:P TLS_GET_TP_REGNUM)
6441 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6442 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6444 [(set_attr "type" "unknown")
6445 ; Since rdhwr always generates a trap for now, putting it in a delay
6446 ; slot would make the kernel's emulation of it much slower.
6447 (set_attr "can_delay" "no")
6448 (set_attr "mode" "<MODE>")
6449 (set_attr "length" "8")])
6451 (define_insn "*tls_get_tp_<mode>_split"
6452 [(set (reg:P TLS_GET_TP_REGNUM)
6453 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6454 "HAVE_AS_TLS && !TARGET_MIPS16"
6455 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6456 [(set_attr "type" "unknown")
6457 ; See tls_get_tp_<mode>
6458 (set_attr "can_delay" "no")
6459 (set_attr "mode" "<MODE>")])
6461 ;; Synchronization instructions.
6465 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6467 (include "mips-ps-3d.md")
6469 ; The MIPS DSP Instructions.
6471 (include "mips-dsp.md")
6473 ; The MIPS DSP REV 2 Instructions.
6475 (include "mips-dspr2.md")
6477 ; MIPS fixed-point instructions.
6478 (include "mips-fixed.md")
6480 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6481 (include "loongson.md")
6483 (define_c_enum "unspec" [
6484 UNSPEC_ADDRESS_FIRST