1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
43 #include "diagnostic-core.h"
49 #include "tree-pass.h"
53 static int reload_cse_noop_set_p (rtx
);
54 static void reload_cse_simplify (rtx
, rtx
);
55 static void reload_cse_regs_1 (rtx
);
56 static int reload_cse_simplify_set (rtx
, rtx
);
57 static int reload_cse_simplify_operands (rtx
, rtx
);
59 static void reload_combine (void);
60 static void reload_combine_note_use (rtx
*, rtx
, int, rtx
);
61 static void reload_combine_note_store (rtx
, const_rtx
, void *);
63 static bool reload_cse_move2add (rtx
);
64 static void move2add_note_store (rtx
, const_rtx
, void *);
66 /* Call cse / combine like post-reload optimization phases.
67 FIRST is the first instruction. */
69 reload_cse_regs (rtx first ATTRIBUTE_UNUSED
)
72 reload_cse_regs_1 (first
);
74 moves_converted
= reload_cse_move2add (first
);
75 if (flag_expensive_optimizations
)
79 reload_cse_regs_1 (first
);
83 /* See whether a single set SET is a noop. */
85 reload_cse_noop_set_p (rtx set
)
87 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
90 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
93 /* Try to simplify INSN. */
95 reload_cse_simplify (rtx insn
, rtx testreg
)
97 rtx body
= PATTERN (insn
);
99 if (GET_CODE (body
) == SET
)
103 /* Simplify even if we may think it is a no-op.
104 We may think a memory load of a value smaller than WORD_SIZE
105 is redundant because we haven't taken into account possible
106 implicit extension. reload_cse_simplify_set() will bring
107 this out, so it's safer to simplify before we delete. */
108 count
+= reload_cse_simplify_set (body
, insn
);
110 if (!count
&& reload_cse_noop_set_p (body
))
112 rtx value
= SET_DEST (body
);
114 && ! REG_FUNCTION_VALUE_P (value
))
116 delete_insn_and_edges (insn
);
121 apply_change_group ();
123 reload_cse_simplify_operands (insn
, testreg
);
125 else if (GET_CODE (body
) == PARALLEL
)
129 rtx value
= NULL_RTX
;
131 /* Registers mentioned in the clobber list for an asm cannot be reused
132 within the body of the asm. Invalidate those registers now so that
133 we don't try to substitute values for them. */
134 if (asm_noperands (body
) >= 0)
136 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
138 rtx part
= XVECEXP (body
, 0, i
);
139 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
140 cselib_invalidate_rtx (XEXP (part
, 0));
144 /* If every action in a PARALLEL is a noop, we can delete
145 the entire PARALLEL. */
146 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
148 rtx part
= XVECEXP (body
, 0, i
);
149 if (GET_CODE (part
) == SET
)
151 if (! reload_cse_noop_set_p (part
))
153 if (REG_P (SET_DEST (part
))
154 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
158 value
= SET_DEST (part
);
161 else if (GET_CODE (part
) != CLOBBER
)
167 delete_insn_and_edges (insn
);
168 /* We're done with this insn. */
172 /* It's not a no-op, but we can try to simplify it. */
173 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
174 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
175 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
178 apply_change_group ();
180 reload_cse_simplify_operands (insn
, testreg
);
184 /* Do a very simple CSE pass over the hard registers.
186 This function detects no-op moves where we happened to assign two
187 different pseudo-registers to the same hard register, and then
188 copied one to the other. Reload will generate a useless
189 instruction copying a register to itself.
191 This function also detects cases where we load a value from memory
192 into two different registers, and (if memory is more expensive than
193 registers) changes it to simply copy the first register into the
196 Another optimization is performed that scans the operands of each
197 instruction to see whether the value is already available in a
198 hard register. It then replaces the operand with the hard register
199 if possible, much like an optional reload would. */
202 reload_cse_regs_1 (rtx first
)
205 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
207 cselib_init (CSELIB_RECORD_MEMORY
);
208 init_alias_analysis ();
210 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
213 reload_cse_simplify (insn
, testreg
);
215 cselib_process_insn (insn
);
219 end_alias_analysis ();
223 /* Try to simplify a single SET instruction. SET is the set pattern.
224 INSN is the instruction it came from.
225 This function only handles one case: if we set a register to a value
226 which is not a register, we try to find that value in some other register
227 and change the set into a register copy. */
230 reload_cse_simplify_set (rtx set
, rtx insn
)
235 enum reg_class dclass
;
238 struct elt_loc_list
*l
;
239 #ifdef LOAD_EXTEND_OP
240 enum rtx_code extend_op
= UNKNOWN
;
242 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
244 dreg
= true_regnum (SET_DEST (set
));
249 if (side_effects_p (src
) || true_regnum (src
) >= 0)
252 dclass
= REGNO_REG_CLASS (dreg
);
254 #ifdef LOAD_EXTEND_OP
255 /* When replacing a memory with a register, we need to honor assumptions
256 that combine made wrt the contents of sign bits. We'll do this by
257 generating an extend instruction instead of a reg->reg copy. Thus
258 the destination must be a register that we can widen. */
260 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
261 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
262 && !REG_P (SET_DEST (set
)))
266 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
270 /* If memory loads are cheaper than register copies, don't change them. */
272 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
273 else if (REG_P (src
))
274 old_cost
= register_move_cost (GET_MODE (src
),
275 REGNO_REG_CLASS (REGNO (src
)), dclass
);
277 old_cost
= rtx_cost (src
, SET
, speed
);
279 for (l
= val
->locs
; l
; l
= l
->next
)
281 rtx this_rtx
= l
->loc
;
284 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
286 #ifdef LOAD_EXTEND_OP
287 if (extend_op
!= UNKNOWN
)
289 HOST_WIDE_INT this_val
;
291 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
292 constants, such as SYMBOL_REF, cannot be extended. */
293 if (!CONST_INT_P (this_rtx
))
296 this_val
= INTVAL (this_rtx
);
300 this_val
&= GET_MODE_MASK (GET_MODE (src
));
303 /* ??? In theory we're already extended. */
304 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
309 this_rtx
= GEN_INT (this_val
);
312 this_cost
= rtx_cost (this_rtx
, SET
, speed
);
314 else if (REG_P (this_rtx
))
316 #ifdef LOAD_EXTEND_OP
317 if (extend_op
!= UNKNOWN
)
319 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
320 this_cost
= rtx_cost (this_rtx
, SET
, speed
);
324 this_cost
= register_move_cost (GET_MODE (this_rtx
),
325 REGNO_REG_CLASS (REGNO (this_rtx
)),
331 /* If equal costs, prefer registers over anything else. That
332 tends to lead to smaller instructions on some machines. */
333 if (this_cost
< old_cost
334 || (this_cost
== old_cost
336 && !REG_P (SET_SRC (set
))))
338 #ifdef LOAD_EXTEND_OP
339 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
340 && extend_op
!= UNKNOWN
341 #ifdef CANNOT_CHANGE_MODE_CLASS
342 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
344 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
348 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
349 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
350 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
354 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
355 old_cost
= this_cost
, did_change
= 1;
362 /* Try to replace operands in INSN with equivalent values that are already
363 in registers. This can be viewed as optional reloading.
365 For each non-register operand in the insn, see if any hard regs are
366 known to be equivalent to that operand. Record the alternatives which
367 can accept these hard registers. Among all alternatives, select the
368 ones which are better or equal to the one currently matching, where
369 "better" is in terms of '?' and '!' constraints. Among the remaining
370 alternatives, select the one which replaces most operands with
374 reload_cse_simplify_operands (rtx insn
, rtx testreg
)
378 /* For each operand, all registers that are equivalent to it. */
379 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
381 const char *constraints
[MAX_RECOG_OPERANDS
];
383 /* Vector recording how bad an alternative is. */
384 int *alternative_reject
;
385 /* Vector recording how many registers can be introduced by choosing
387 int *alternative_nregs
;
388 /* Array of vectors recording, for each operand and each alternative,
389 which hard register to substitute, or -1 if the operand should be
391 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
392 /* Array of alternatives, sorted in order of decreasing desirability. */
393 int *alternative_order
;
397 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
400 /* Figure out which alternative currently matches. */
401 if (! constrain_operands (1))
402 fatal_insn_not_found (insn
);
404 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
405 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
406 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
407 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
408 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
410 /* For each operand, find out which regs are equivalent. */
411 for (i
= 0; i
< recog_data
.n_operands
; i
++)
414 struct elt_loc_list
*l
;
417 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
419 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
420 right, so avoid the problem here. Likewise if we have a constant
421 and the insn pattern doesn't tell us the mode we need. */
422 if (LABEL_P (recog_data
.operand
[i
])
423 || (CONSTANT_P (recog_data
.operand
[i
])
424 && recog_data
.operand_mode
[i
] == VOIDmode
))
427 op
= recog_data
.operand
[i
];
428 #ifdef LOAD_EXTEND_OP
430 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
431 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
433 rtx set
= single_set (insn
);
435 /* We might have multiple sets, some of which do implicit
436 extension. Punt on this for now. */
439 /* If the destination is also a MEM or a STRICT_LOW_PART, no
441 Also, if there is an explicit extension, we don't have to
442 worry about an implicit one. */
443 else if (MEM_P (SET_DEST (set
))
444 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
445 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
446 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
447 ; /* Continue ordinary processing. */
448 #ifdef CANNOT_CHANGE_MODE_CLASS
449 /* If the register cannot change mode to word_mode, it follows that
450 it cannot have been used in word_mode. */
451 else if (REG_P (SET_DEST (set
))
452 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
454 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
455 ; /* Continue ordinary processing. */
457 /* If this is a straight load, make the extension explicit. */
458 else if (REG_P (SET_DEST (set
))
459 && recog_data
.n_operands
== 2
460 && SET_SRC (set
) == op
461 && SET_DEST (set
) == recog_data
.operand
[1-i
])
463 validate_change (insn
, recog_data
.operand_loc
[i
],
464 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
467 validate_change (insn
, recog_data
.operand_loc
[1-i
],
468 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
470 if (! apply_change_group ())
472 return reload_cse_simplify_operands (insn
, testreg
);
475 /* ??? There might be arithmetic operations with memory that are
476 safe to optimize, but is it worth the trouble? */
479 #endif /* LOAD_EXTEND_OP */
480 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0);
484 for (l
= v
->locs
; l
; l
= l
->next
)
486 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
489 for (i
= 0; i
< recog_data
.n_operands
; i
++)
491 enum machine_mode mode
;
495 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
496 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
497 op_alt_regno
[i
][j
] = -1;
499 p
= constraints
[i
] = recog_data
.constraints
[i
];
500 mode
= recog_data
.operand_mode
[i
];
502 /* Add the reject values for each alternative given by the constraints
511 alternative_reject
[j
] += 3;
513 alternative_reject
[j
] += 300;
516 /* We won't change operands which are already registers. We
517 also don't want to modify output operands. */
518 regno
= true_regnum (recog_data
.operand
[i
]);
520 || constraints
[i
][0] == '='
521 || constraints
[i
][0] == '+')
524 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
526 enum reg_class rclass
= NO_REGS
;
528 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
531 SET_REGNO (testreg
, regno
);
532 PUT_MODE (testreg
, mode
);
534 /* We found a register equal to this operand. Now look for all
535 alternatives that can accept this register and have not been
536 assigned a register they can use yet. */
545 case '=': case '+': case '?':
546 case '#': case '&': case '!':
548 case '0': case '1': case '2': case '3': case '4':
549 case '5': case '6': case '7': case '8': case '9':
550 case '<': case '>': case 'V': case 'o':
551 case 'E': case 'F': case 'G': case 'H':
552 case 's': case 'i': case 'n':
553 case 'I': case 'J': case 'K': case 'L':
554 case 'M': case 'N': case 'O': case 'P':
555 case 'p': case 'X': case TARGET_MEM_CONSTRAINT
:
556 /* These don't say anything we care about. */
560 rclass
= reg_class_subunion
[(int) rclass
][(int) GENERAL_REGS
];
565 = (reg_class_subunion
567 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
571 /* See if REGNO fits this alternative, and set it up as the
572 replacement register if we don't have one for this
573 alternative yet and the operand being replaced is not
574 a cheap CONST_INT. */
575 if (op_alt_regno
[i
][j
] == -1
576 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
577 && (!CONST_INT_P (recog_data
.operand
[i
])
578 || (rtx_cost (recog_data
.operand
[i
], SET
,
579 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
580 > rtx_cost (testreg
, SET
,
581 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
))))))
583 alternative_nregs
[j
]++;
584 op_alt_regno
[i
][j
] = regno
;
590 p
+= CONSTRAINT_LEN (c
, p
);
598 /* Record all alternatives which are better or equal to the currently
599 matching one in the alternative_order array. */
600 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
601 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
602 alternative_order
[j
++] = i
;
603 recog_data
.n_alternatives
= j
;
605 /* Sort it. Given a small number of alternatives, a dumb algorithm
606 won't hurt too much. */
607 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
610 int best_reject
= alternative_reject
[alternative_order
[i
]];
611 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
614 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
616 int this_reject
= alternative_reject
[alternative_order
[j
]];
617 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
619 if (this_reject
< best_reject
620 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
623 best_reject
= this_reject
;
624 best_nregs
= this_nregs
;
628 tmp
= alternative_order
[best
];
629 alternative_order
[best
] = alternative_order
[i
];
630 alternative_order
[i
] = tmp
;
633 /* Substitute the operands as determined by op_alt_regno for the best
635 j
= alternative_order
[0];
637 for (i
= 0; i
< recog_data
.n_operands
; i
++)
639 enum machine_mode mode
= recog_data
.operand_mode
[i
];
640 if (op_alt_regno
[i
][j
] == -1)
643 validate_change (insn
, recog_data
.operand_loc
[i
],
644 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
647 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
649 int op
= recog_data
.dup_num
[i
];
650 enum machine_mode mode
= recog_data
.operand_mode
[op
];
652 if (op_alt_regno
[op
][j
] == -1)
655 validate_change (insn
, recog_data
.dup_loc
[i
],
656 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
659 return apply_change_group ();
662 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
664 This code might also be useful when reload gave up on reg+reg addressing
665 because of clashes between the return register and INDEX_REG_CLASS. */
667 /* The maximum number of uses of a register we can keep track of to
668 replace them with reg+reg addressing. */
669 #define RELOAD_COMBINE_MAX_USES 16
671 /* Describes a recorded use of a register. */
674 /* The insn where a register has been used. */
676 /* Points to the memory reference enclosing the use, if any, NULL_RTX
679 /* Location of the register withing INSN. */
681 /* The reverse uid of the insn. */
685 /* If the register is used in some unknown fashion, USE_INDEX is negative.
686 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
687 indicates where it is first set or clobbered.
688 Otherwise, USE_INDEX is the index of the last encountered use of the
689 register (which is first among these we have seen since we scan backwards).
690 USE_RUID indicates the first encountered, i.e. last, of these uses.
691 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
692 with a constant offset; OFFSET contains this constant in that case.
693 STORE_RUID is always meaningful if we only want to use a value in a
694 register in a different place: it denotes the next insn in the insn
695 stream (i.e. the last encountered) that sets or clobbers the register.
696 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
699 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
705 bool all_offsets_match
;
706 } reg_state
[FIRST_PSEUDO_REGISTER
];
708 /* Reverse linear uid. This is increased in reload_combine while scanning
709 the instructions from last to first. It is used to set last_label_ruid
710 and the store_ruid / use_ruid fields in reg_state. */
711 static int reload_combine_ruid
;
713 /* The RUID of the last label we encountered in reload_combine. */
714 static int last_label_ruid
;
716 /* The RUID of the last jump we encountered in reload_combine. */
717 static int last_jump_ruid
;
719 /* The register numbers of the first and last index register. A value of
720 -1 in LAST_INDEX_REG indicates that we've previously computed these
721 values and found no suitable index registers. */
722 static int first_index_reg
= -1;
723 static int last_index_reg
;
725 #define LABEL_LIVE(LABEL) \
726 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
728 /* Subroutine of reload_combine_split_ruids, called to fix up a single
729 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
732 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
734 if (*pruid
> split_ruid
)
738 /* Called when we insert a new insn in a position we've already passed in
739 the scan. Examine all our state, increasing all ruids that are higher
740 than SPLIT_RUID by one in order to make room for a new insn. */
743 reload_combine_split_ruids (int split_ruid
)
747 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
748 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
749 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
751 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
753 int j
, idx
= reg_state
[i
].use_index
;
754 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
755 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
756 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
760 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
762 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
768 /* Called when we are about to rescan a previously encountered insn with
769 reload_combine_note_use after modifying some part of it. This clears all
770 information about uses in that particular insn. */
773 reload_combine_purge_insn_uses (rtx insn
)
777 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
779 int j
, k
, idx
= reg_state
[i
].use_index
;
782 j
= k
= RELOAD_COMBINE_MAX_USES
;
785 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
789 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
792 reg_state
[i
].use_index
= k
;
796 /* Called when we need to forget about all uses of REGNO after an insn
797 which is identified by RUID. */
800 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
802 int j
, k
, idx
= reg_state
[regno
].use_index
;
805 j
= k
= RELOAD_COMBINE_MAX_USES
;
808 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
812 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
815 reg_state
[regno
].use_index
= k
;
818 /* Find the use of REGNO with the ruid that is highest among those
819 lower than RUID_LIMIT, and return it if it is the only use of this
820 reg in the insn. Return NULL otherwise. */
822 static struct reg_use
*
823 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
825 int i
, best_ruid
= 0;
826 int use_idx
= reg_state
[regno
].use_index
;
827 struct reg_use
*retval
;
832 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
834 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
835 int this_ruid
= use
->ruid
;
836 if (this_ruid
>= ruid_limit
)
838 if (this_ruid
> best_ruid
)
840 best_ruid
= this_ruid
;
843 else if (this_ruid
== best_ruid
)
846 if (last_label_ruid
>= best_ruid
)
851 /* After we've moved an add insn, fix up any debug insns that occur
852 between the old location of the add and the new location. REG is
853 the destination register of the add insn; REPLACEMENT is the
854 SET_SRC of the add. FROM and TO specify the range in which we
855 should make this change on debug insns. */
858 fixup_debug_insns (rtx reg
, rtx replacement
, rtx from
, rtx to
)
861 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
865 if (!DEBUG_INSN_P (insn
))
868 t
= INSN_VAR_LOCATION_LOC (insn
);
869 t
= simplify_replace_rtx (t
, reg
, replacement
);
870 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
874 /* Called by reload_combine when scanning INSN. This function tries to detect
875 patterns where a constant is added to a register, and the result is used
877 Return true if no further processing is needed on INSN; false if it wasn't
878 recognized and should be handled normally. */
881 reload_combine_recognize_const_pattern (rtx insn
)
883 int from_ruid
= reload_combine_ruid
;
884 rtx set
, pat
, reg
, src
, addreg
;
888 rtx add_moved_after_insn
= NULL_RTX
;
889 int add_moved_after_ruid
= 0;
890 int clobbered_regno
= -1;
892 set
= single_set (insn
);
896 reg
= SET_DEST (set
);
899 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1
900 || GET_MODE (reg
) != Pmode
901 || reg
== stack_pointer_rtx
)
906 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
907 uses of REG1 inside an address, or inside another add insn. If
908 possible and profitable, merge the addition into subsequent
910 if (GET_CODE (src
) != PLUS
911 || !REG_P (XEXP (src
, 0))
912 || !CONSTANT_P (XEXP (src
, 1)))
915 addreg
= XEXP (src
, 0);
916 must_move_add
= rtx_equal_p (reg
, addreg
);
918 pat
= PATTERN (insn
);
919 if (must_move_add
&& set
!= pat
)
921 /* We have to be careful when moving the add; apart from the
922 single_set there may also be clobbers. Recognize one special
923 case, that of one clobber alongside the set (likely a clobber
924 of the CC register). */
925 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
926 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
927 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
928 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
930 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
935 use
= reload_combine_closest_single_use (regno
, from_ruid
);
938 /* Start the search for the next use from here. */
939 from_ruid
= use
->ruid
;
941 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
943 rtx use_insn
= use
->insn
;
944 int use_ruid
= use
->ruid
;
945 rtx mem
= use
->containing_mem
;
946 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
948 /* Avoid moving the add insn past a jump. */
949 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
952 /* If the add clobbers another hard reg in parallel, don't move
953 it past a real set of this hard reg. */
954 if (must_move_add
&& clobbered_regno
>= 0
955 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
958 /* Avoid moving a use of ADDREG past a point where it
960 if (reg_state
[REGNO (addreg
)].store_ruid
>= use_ruid
)
965 addr_space_t as
= MEM_ADDR_SPACE (mem
);
966 rtx oldaddr
= XEXP (mem
, 0);
967 rtx newaddr
= NULL_RTX
;
968 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
971 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
972 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
974 XEXP (mem
, 0) = newaddr
;
975 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
976 XEXP (mem
, 0) = oldaddr
;
977 if (new_cost
<= old_cost
978 && validate_change (use_insn
,
979 &XEXP (mem
, 0), newaddr
, 0))
981 reload_combine_purge_insn_uses (use_insn
);
982 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
987 add_moved_after_insn
= use_insn
;
988 add_moved_after_ruid
= use_ruid
;
996 rtx new_set
= single_set (use_insn
);
998 && REG_P (SET_DEST (new_set
))
999 && GET_CODE (SET_SRC (new_set
)) == PLUS
1000 && REG_P (XEXP (SET_SRC (new_set
), 0))
1001 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
1004 int old_cost
= rtx_cost (SET_SRC (new_set
), SET
, speed
);
1006 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
1007 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
1009 if (rtx_cost (new_src
, SET
, speed
) <= old_cost
1010 && validate_change (use_insn
, &SET_SRC (new_set
),
1013 reload_combine_purge_insn_uses (use_insn
);
1014 reload_combine_note_use (&SET_SRC (new_set
), use_insn
,
1015 use_ruid
, NULL_RTX
);
1019 /* See if that took care of the add insn. */
1020 if (rtx_equal_p (SET_DEST (new_set
), reg
))
1022 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1028 add_moved_after_insn
= use_insn
;
1029 add_moved_after_ruid
= use_ruid
;
1036 /* If we get here, we couldn't handle this use. */
1043 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1044 /* Process the add normally. */
1047 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1049 reorder_insns (insn
, insn
, add_moved_after_insn
);
1050 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1051 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1052 reload_combine_note_use (&PATTERN (insn
), insn
,
1053 add_moved_after_ruid
, NULL_RTX
);
1054 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1059 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1060 can handle and improve. Return true if no further processing is needed on
1061 INSN; false if it wasn't recognized and should be handled normally. */
1064 reload_combine_recognize_pattern (rtx insn
)
1069 set
= single_set (insn
);
1070 if (set
== NULL_RTX
)
1073 reg
= SET_DEST (set
);
1074 src
= SET_SRC (set
);
1076 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1)
1079 regno
= REGNO (reg
);
1081 /* Look for (set (REGX) (CONST_INT))
1082 (set (REGX) (PLUS (REGX) (REGY)))
1084 ... (MEM (REGX)) ...
1086 (set (REGZ) (CONST_INT))
1088 ... (MEM (PLUS (REGZ) (REGY)))... .
1090 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1091 and that we know all uses of REGX before it dies.
1092 Also, explicitly check that REGX != REGY; our life information
1093 does not yet show whether REGY changes in this insn. */
1095 if (GET_CODE (src
) == PLUS
1096 && reg_state
[regno
].all_offsets_match
1097 && last_index_reg
!= -1
1098 && REG_P (XEXP (src
, 1))
1099 && rtx_equal_p (XEXP (src
, 0), reg
)
1100 && !rtx_equal_p (XEXP (src
, 1), reg
)
1101 && reg_state
[regno
].use_index
>= 0
1102 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1103 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1105 rtx base
= XEXP (src
, 1);
1106 rtx prev
= prev_nonnote_insn (insn
);
1107 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1108 rtx index_reg
= NULL_RTX
;
1109 rtx reg_sum
= NULL_RTX
;
1112 /* Now we need to set INDEX_REG to an index register (denoted as
1113 REGZ in the illustration above) and REG_SUM to the expression
1114 register+register that we want to use to substitute uses of REG
1115 (typically in MEMs) with. First check REG and BASE for being
1116 index registers; we can use them even if they are not dead. */
1117 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1118 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1126 /* Otherwise, look for a free index register. Since we have
1127 checked above that neither REG nor BASE are index registers,
1128 if we find anything at all, it will be different from these
1130 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1132 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1133 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1134 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1135 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1136 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1137 && !fixed_regs
[i
] && !global_regs
[i
]
1138 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1139 && targetm
.hard_regno_scratch_ok (i
))
1141 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1142 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1148 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1149 (REGY), i.e. BASE, is not clobbered before the last use we'll
1153 && CONST_INT_P (SET_SRC (prev_set
))
1154 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1155 && (reg_state
[REGNO (base
)].store_ruid
1156 <= reg_state
[regno
].use_ruid
))
1158 /* Change destination register and, if necessary, the constant
1159 value in PREV, the constant loading instruction. */
1160 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1161 if (reg_state
[regno
].offset
!= const0_rtx
)
1162 validate_change (prev
,
1163 &SET_SRC (prev_set
),
1164 GEN_INT (INTVAL (SET_SRC (prev_set
))
1165 + INTVAL (reg_state
[regno
].offset
)),
1168 /* Now for every use of REG that we have recorded, replace REG
1170 for (i
= reg_state
[regno
].use_index
;
1171 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1172 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1173 reg_state
[regno
].reg_use
[i
].usep
,
1174 /* Each change must have its own
1178 if (apply_change_group ())
1180 struct reg_use
*lowest_ruid
= NULL
;
1182 /* For every new use of REG_SUM, we have to record the use
1183 of BASE therein, i.e. operand 1. */
1184 for (i
= reg_state
[regno
].use_index
;
1185 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1187 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1188 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1189 use
->ruid
, use
->containing_mem
);
1190 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1194 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1196 /* Delete the reg-reg addition. */
1199 if (reg_state
[regno
].offset
!= const0_rtx
)
1200 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1202 remove_reg_equal_equiv_notes (prev
);
1204 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1213 reload_combine (void)
1219 int min_labelno
, n_labels
;
1220 HARD_REG_SET ever_live_at_start
, *label_live
;
1222 /* To avoid wasting too much time later searching for an index register,
1223 determine the minimum and maximum index register numbers. */
1224 if (INDEX_REG_CLASS
== NO_REGS
)
1225 last_index_reg
= -1;
1226 else if (first_index_reg
== -1 && last_index_reg
== 0)
1228 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1229 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1231 if (first_index_reg
== -1)
1232 first_index_reg
= r
;
1237 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1238 to -1 so we'll know to quit early the next time we get here. */
1239 if (first_index_reg
== -1)
1241 last_index_reg
= -1;
1246 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1247 information is a bit fuzzy immediately after reload, but it's
1248 still good enough to determine which registers are live at a jump
1250 min_labelno
= get_first_label_num ();
1251 n_labels
= max_label_num () - min_labelno
;
1252 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1253 CLEAR_HARD_REG_SET (ever_live_at_start
);
1255 FOR_EACH_BB_REVERSE (bb
)
1257 insn
= BB_HEAD (bb
);
1261 bitmap live_in
= df_get_live_in (bb
);
1263 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1264 compute_use_by_pseudos (&live
, live_in
);
1265 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1266 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1270 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1271 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1272 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1274 reg_state
[r
].store_ruid
= 0;
1275 reg_state
[r
].real_store_ruid
= 0;
1277 reg_state
[r
].use_index
= -1;
1279 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1282 for (insn
= get_last_insn (); insn
; insn
= prev
)
1286 prev
= PREV_INSN (insn
);
1288 /* We cannot do our optimization across labels. Invalidating all the use
1289 information we have would be costly, so we just note where the label
1290 is and then later disable any optimization that would cross it. */
1292 last_label_ruid
= reload_combine_ruid
;
1293 else if (BARRIER_P (insn
))
1294 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1295 if (! fixed_regs
[r
])
1296 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1298 if (! NONDEBUG_INSN_P (insn
))
1301 reload_combine_ruid
++;
1303 if (control_flow_insn_p (insn
))
1304 last_jump_ruid
= reload_combine_ruid
;
1306 if (reload_combine_recognize_const_pattern (insn
)
1307 || reload_combine_recognize_pattern (insn
))
1310 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1316 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1317 if (call_used_regs
[r
])
1319 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1320 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1323 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1324 link
= XEXP (link
, 1))
1326 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
1327 if (REG_P (usage_rtx
))
1330 unsigned int start_reg
= REGNO (usage_rtx
);
1331 unsigned int num_regs
=
1332 hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
1333 unsigned int end_reg
= start_reg
+ num_regs
- 1;
1334 for (i
= start_reg
; i
<= end_reg
; i
++)
1335 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1337 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1338 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1341 reg_state
[i
].use_index
= -1;
1346 else if (JUMP_P (insn
)
1347 && GET_CODE (PATTERN (insn
)) != RETURN
)
1349 /* Non-spill registers might be used at the call destination in
1350 some unknown fashion, so we have to mark the unknown use. */
1353 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1354 && JUMP_LABEL (insn
))
1355 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1357 live
= &ever_live_at_start
;
1359 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
1360 if (TEST_HARD_REG_BIT (*live
, i
))
1361 reg_state
[i
].use_index
= -1;
1364 reload_combine_note_use (&PATTERN (insn
), insn
,
1365 reload_combine_ruid
, NULL_RTX
);
1366 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1368 if (REG_NOTE_KIND (note
) == REG_INC
1369 && REG_P (XEXP (note
, 0)))
1371 int regno
= REGNO (XEXP (note
, 0));
1373 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1374 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1375 reg_state
[regno
].use_index
= -1;
1383 /* Check if DST is a register or a subreg of a register; if it is,
1384 update store_ruid, real_store_ruid and use_index in the reg_state
1385 structure accordingly. Called via note_stores from reload_combine. */
1388 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1392 enum machine_mode mode
= GET_MODE (dst
);
1394 if (GET_CODE (dst
) == SUBREG
)
1396 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1397 GET_MODE (SUBREG_REG (dst
)),
1400 dst
= SUBREG_REG (dst
);
1404 regno
+= REGNO (dst
);
1406 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1407 careful with registers / register parts that are not full words.
1408 Similarly for ZERO_EXTRACT. */
1409 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1410 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1412 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1414 reg_state
[i
].use_index
= -1;
1415 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1416 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1421 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1423 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1424 if (GET_CODE (set
) == SET
)
1425 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1426 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1431 /* XP points to a piece of rtl that has to be checked for any uses of
1433 *XP is the pattern of INSN, or a part of it.
1434 Called from reload_combine, and recursively by itself. */
1436 reload_combine_note_use (rtx
*xp
, rtx insn
, int ruid
, rtx containing_mem
)
1439 enum rtx_code code
= x
->code
;
1442 rtx offset
= const0_rtx
; /* For the REG case below. */
1447 if (REG_P (SET_DEST (x
)))
1449 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1455 /* If this is the USE of a return value, we can't change it. */
1456 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1458 /* Mark the return register as used in an unknown fashion. */
1459 rtx reg
= XEXP (x
, 0);
1460 int regno
= REGNO (reg
);
1461 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1463 while (--nregs
>= 0)
1464 reg_state
[regno
+ nregs
].use_index
= -1;
1470 if (REG_P (SET_DEST (x
)))
1472 /* No spurious CLOBBERs of pseudo registers may remain. */
1473 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1479 /* We are interested in (plus (reg) (const_int)) . */
1480 if (!REG_P (XEXP (x
, 0))
1481 || !CONST_INT_P (XEXP (x
, 1)))
1483 offset
= XEXP (x
, 1);
1488 int regno
= REGNO (x
);
1492 /* No spurious USEs of pseudo registers may remain. */
1493 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1495 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1497 /* We can't substitute into multi-hard-reg uses. */
1500 while (--nregs
>= 0)
1501 reg_state
[regno
+ nregs
].use_index
= -1;
1505 /* We may be called to update uses in previously seen insns.
1506 Don't add uses beyond the last store we saw. */
1507 if (ruid
< reg_state
[regno
].store_ruid
)
1510 /* If this register is already used in some unknown fashion, we
1512 If we decrement the index from zero to -1, we can't store more
1513 uses, so this register becomes used in an unknown fashion. */
1514 use_index
= --reg_state
[regno
].use_index
;
1518 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1520 /* This is the first use of this register we have seen since we
1521 marked it as dead. */
1522 reg_state
[regno
].offset
= offset
;
1523 reg_state
[regno
].all_offsets_match
= true;
1524 reg_state
[regno
].use_ruid
= ruid
;
1528 if (reg_state
[regno
].use_ruid
> ruid
)
1529 reg_state
[regno
].use_ruid
= ruid
;
1531 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1532 reg_state
[regno
].all_offsets_match
= false;
1535 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1536 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1537 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1538 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1550 /* Recursively process the components of X. */
1551 fmt
= GET_RTX_FORMAT (code
);
1552 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1555 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1556 else if (fmt
[i
] == 'E')
1558 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1559 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1565 /* See if we can reduce the cost of a constant by replacing a move
1566 with an add. We track situations in which a register is set to a
1567 constant or to a register plus a constant. */
1568 /* We cannot do our optimization across labels. Invalidating all the
1569 information about register contents we have would be costly, so we
1570 use move2add_last_label_luid to note where the label is and then
1571 later disable any optimization that would cross it.
1572 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1573 are only valid if reg_set_luid[n] is greater than
1574 move2add_last_label_luid. */
1575 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1577 /* If reg_base_reg[n] is negative, register n has been set to
1578 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1579 If reg_base_reg[n] is non-negative, register n has been set to the
1580 sum of reg_offset[n] and the value of register reg_base_reg[n]
1581 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1582 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1583 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1584 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1585 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1587 /* move2add_luid is linearly increased while scanning the instructions
1588 from first to last. It is used to set reg_set_luid in
1589 reload_cse_move2add and move2add_note_store. */
1590 static int move2add_luid
;
1592 /* move2add_last_label_luid is set whenever a label is found. Labels
1593 invalidate all previously collected reg_offset data. */
1594 static int move2add_last_label_luid
;
1596 /* ??? We don't know how zero / sign extension is handled, hence we
1597 can't go from a narrower to a wider mode. */
1598 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1599 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1600 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1601 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
1602 GET_MODE_BITSIZE (INMODE))))
1604 /* This function is called with INSN that sets REG to (SYM + OFF),
1605 while REG is known to already have value (SYM + offset).
1606 This function tries to change INSN into an add instruction
1607 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1608 It also updates the information about REG's known value.
1609 Return true if we made a change. */
1612 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx insn
)
1614 rtx pat
= PATTERN (insn
);
1615 rtx src
= SET_SRC (pat
);
1616 int regno
= REGNO (reg
);
1617 rtx new_src
= gen_int_mode (INTVAL (off
) - reg_offset
[regno
],
1619 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1620 bool changed
= false;
1622 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1623 use (set (reg) (reg)) instead.
1624 We don't delete this insn, nor do we convert it into a
1625 note, to avoid losing register notes or the return
1626 value flag. jump2 already knows how to get rid of
1628 if (new_src
== const0_rtx
)
1630 /* If the constants are different, this is a
1631 truncation, that, if turned into (set (reg)
1632 (reg)), would be discarded. Maybe we should
1633 try a truncMN pattern? */
1634 if (INTVAL (off
) == reg_offset
[regno
])
1635 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1637 else if (rtx_cost (new_src
, PLUS
, speed
) < rtx_cost (src
, SET
, speed
)
1638 && have_add2_insn (reg
, new_src
))
1640 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1641 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1643 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1645 enum machine_mode narrow_mode
;
1646 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1647 narrow_mode
!= VOIDmode
1648 && narrow_mode
!= GET_MODE (reg
);
1649 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1651 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1652 && ((reg_offset
[regno
]
1653 & ~GET_MODE_MASK (narrow_mode
))
1655 & ~GET_MODE_MASK (narrow_mode
))))
1657 rtx narrow_reg
= gen_rtx_REG (narrow_mode
,
1659 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1662 gen_rtx_SET (VOIDmode
,
1663 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1666 changed
= validate_change (insn
, &PATTERN (insn
),
1673 reg_set_luid
[regno
] = move2add_luid
;
1674 reg_base_reg
[regno
] = -1;
1675 reg_mode
[regno
] = GET_MODE (reg
);
1676 reg_symbol_ref
[regno
] = sym
;
1677 reg_offset
[regno
] = INTVAL (off
);
1682 /* This function is called with INSN that sets REG to (SYM + OFF),
1683 but REG doesn't have known value (SYM + offset). This function
1684 tries to find another register which is known to already have
1685 value (SYM + offset) and change INSN into an add instruction
1686 (set (REG) (plus (the found register) (OFF - offset))) if such
1687 a register is found. It also updates the information about
1689 Return true iff we made a change. */
1692 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx insn
)
1694 rtx pat
= PATTERN (insn
);
1695 rtx src
= SET_SRC (pat
);
1696 int regno
= REGNO (reg
);
1697 int min_cost
= INT_MAX
;
1699 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1701 bool changed
= false;
1703 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1704 if (reg_set_luid
[i
] > move2add_last_label_luid
1705 && reg_mode
[i
] == GET_MODE (reg
)
1706 && reg_base_reg
[i
] < 0
1707 && reg_symbol_ref
[i
] != NULL_RTX
1708 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1710 rtx new_src
= gen_int_mode (INTVAL (off
) - reg_offset
[i
],
1712 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1713 use (set (reg) (reg)) instead.
1714 We don't delete this insn, nor do we convert it into a
1715 note, to avoid losing register notes or the return
1716 value flag. jump2 already knows how to get rid of
1718 if (new_src
== const0_rtx
)
1726 int cost
= rtx_cost (new_src
, PLUS
, speed
);
1727 if (cost
< min_cost
)
1735 if (min_cost
< rtx_cost (src
, SET
, speed
))
1739 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1742 rtx new_src
= gen_int_mode (INTVAL (off
) - reg_offset
[min_regno
],
1744 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1746 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1749 reg_set_luid
[regno
] = move2add_luid
;
1750 reg_base_reg
[regno
] = -1;
1751 reg_mode
[regno
] = GET_MODE (reg
);
1752 reg_symbol_ref
[regno
] = sym
;
1753 reg_offset
[regno
] = INTVAL (off
);
1757 /* Convert move insns with constant inputs to additions if they are cheaper.
1758 Return true if any changes were made. */
1760 reload_cse_move2add (rtx first
)
1764 bool changed
= false;
1766 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1768 reg_set_luid
[i
] = 0;
1770 reg_base_reg
[i
] = 0;
1771 reg_symbol_ref
[i
] = NULL_RTX
;
1772 reg_mode
[i
] = VOIDmode
;
1775 move2add_last_label_luid
= 0;
1777 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1783 move2add_last_label_luid
= move2add_luid
;
1784 /* We're going to increment move2add_luid twice after a
1785 label, so that we can use move2add_last_label_luid + 1 as
1786 the luid for constants. */
1790 if (! INSN_P (insn
))
1792 pat
= PATTERN (insn
);
1793 /* For simplicity, we only perform this optimization on
1794 straightforward SETs. */
1795 if (GET_CODE (pat
) == SET
1796 && REG_P (SET_DEST (pat
)))
1798 rtx reg
= SET_DEST (pat
);
1799 int regno
= REGNO (reg
);
1800 rtx src
= SET_SRC (pat
);
1802 /* Check if we have valid information on the contents of this
1803 register in the mode of REG. */
1804 if (reg_set_luid
[regno
] > move2add_last_label_luid
1805 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
])
1806 && dbg_cnt (cse2_move2add
))
1808 /* Try to transform (set (REGX) (CONST_INT A))
1810 (set (REGX) (CONST_INT B))
1812 (set (REGX) (CONST_INT A))
1814 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1816 (set (REGX) (CONST_INT A))
1818 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1821 if (CONST_INT_P (src
)
1822 && reg_base_reg
[regno
] < 0
1823 && reg_symbol_ref
[regno
] == NULL_RTX
)
1825 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1829 /* Try to transform (set (REGX) (REGY))
1830 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1833 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1836 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1838 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1839 else if (REG_P (src
)
1840 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1841 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1842 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
1843 reg_mode
[REGNO (src
)]))
1845 rtx next
= next_nonnote_insn (insn
);
1848 set
= single_set (next
);
1850 && SET_DEST (set
) == reg
1851 && GET_CODE (SET_SRC (set
)) == PLUS
1852 && XEXP (SET_SRC (set
), 0) == reg
1853 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
1855 rtx src3
= XEXP (SET_SRC (set
), 1);
1856 HOST_WIDE_INT added_offset
= INTVAL (src3
);
1857 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1858 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1860 gen_int_mode (added_offset
1864 bool success
= false;
1865 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1867 if (new_src
== const0_rtx
)
1868 /* See above why we create (set (reg) (reg)) here. */
1870 = validate_change (next
, &SET_SRC (set
), reg
, 0);
1871 else if ((rtx_cost (new_src
, PLUS
, speed
)
1872 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
, speed
))
1873 && have_add2_insn (reg
, new_src
))
1875 rtx newpat
= gen_rtx_SET (VOIDmode
,
1877 gen_rtx_PLUS (GET_MODE (reg
),
1881 = validate_change (next
, &PATTERN (next
),
1888 reg_mode
[regno
] = GET_MODE (reg
);
1890 trunc_int_for_mode (added_offset
+ base_offset
,
1898 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1900 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
1902 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1904 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
1905 if ((GET_CODE (src
) == SYMBOL_REF
1906 || (GET_CODE (src
) == CONST
1907 && GET_CODE (XEXP (src
, 0)) == PLUS
1908 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
1909 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
1910 && dbg_cnt (cse2_move2add
))
1914 if (GET_CODE (src
) == SYMBOL_REF
)
1921 sym
= XEXP (XEXP (src
, 0), 0);
1922 off
= XEXP (XEXP (src
, 0), 1);
1925 /* If the reg already contains the value which is sum of
1926 sym and some constant value, we can use an add2 insn. */
1927 if (reg_set_luid
[regno
] > move2add_last_label_luid
1928 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
])
1929 && reg_base_reg
[regno
] < 0
1930 && reg_symbol_ref
[regno
] != NULL_RTX
1931 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
1932 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
1934 /* Otherwise, we have to find a register whose value is sum
1935 of sym and some constant value. */
1937 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
1943 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1945 if (REG_NOTE_KIND (note
) == REG_INC
1946 && REG_P (XEXP (note
, 0)))
1948 /* Reset the information about this register. */
1949 int regno
= REGNO (XEXP (note
, 0));
1950 if (regno
< FIRST_PSEUDO_REGISTER
)
1951 reg_set_luid
[regno
] = 0;
1954 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
1956 /* If INSN is a conditional branch, we try to extract an
1957 implicit set out of it. */
1958 if (any_condjump_p (insn
))
1960 rtx cnd
= fis_get_condition (insn
);
1963 && GET_CODE (cnd
) == NE
1964 && REG_P (XEXP (cnd
, 0))
1965 && !reg_set_p (XEXP (cnd
, 0), insn
)
1966 /* The following two checks, which are also in
1967 move2add_note_store, are intended to reduce the
1968 number of calls to gen_rtx_SET to avoid memory
1969 allocation if possible. */
1970 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
1971 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
1972 && CONST_INT_P (XEXP (cnd
, 1)))
1975 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
1976 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
1980 /* If this is a CALL_INSN, all call used registers are stored with
1984 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1986 if (call_used_regs
[i
])
1987 /* Reset the information about this register. */
1988 reg_set_luid
[i
] = 0;
1995 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
1997 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
1998 Called from reload_cse_move2add via note_stores. */
2001 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2003 rtx insn
= (rtx
) data
;
2004 unsigned int regno
= 0;
2005 unsigned int nregs
= 0;
2007 enum machine_mode mode
= GET_MODE (dst
);
2009 if (GET_CODE (dst
) == SUBREG
)
2011 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
2012 GET_MODE (SUBREG_REG (dst
)),
2015 nregs
= subreg_nregs (dst
);
2016 dst
= SUBREG_REG (dst
);
2019 /* Some targets do argument pushes without adding REG_INC notes. */
2023 dst
= XEXP (dst
, 0);
2024 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2025 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2026 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
2032 regno
+= REGNO (dst
);
2034 nregs
= hard_regno_nregs
[regno
][mode
];
2036 if (SCALAR_INT_MODE_P (GET_MODE (dst
))
2037 && nregs
== 1 && GET_CODE (set
) == SET
)
2039 rtx note
, sym
= NULL_RTX
;
2042 note
= find_reg_equal_equiv_note (insn
);
2043 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2045 sym
= XEXP (note
, 0);
2048 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2049 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2050 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2051 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2053 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2054 off
= INTVAL (XEXP (XEXP (XEXP (note
, 0), 0), 1));
2057 if (sym
!= NULL_RTX
)
2059 reg_base_reg
[regno
] = -1;
2060 reg_symbol_ref
[regno
] = sym
;
2061 reg_offset
[regno
] = off
;
2062 reg_mode
[regno
] = mode
;
2063 reg_set_luid
[regno
] = move2add_luid
;
2068 if (SCALAR_INT_MODE_P (GET_MODE (dst
))
2069 && nregs
== 1 && GET_CODE (set
) == SET
2070 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2071 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2073 rtx src
= SET_SRC (set
);
2075 HOST_WIDE_INT offset
;
2077 /* This may be different from mode, if SET_DEST (set) is a
2079 enum machine_mode dst_mode
= GET_MODE (dst
);
2081 switch (GET_CODE (src
))
2084 if (REG_P (XEXP (src
, 0)))
2086 base_reg
= XEXP (src
, 0);
2088 if (CONST_INT_P (XEXP (src
, 1)))
2089 offset
= INTVAL (XEXP (src
, 1));
2090 else if (REG_P (XEXP (src
, 1))
2091 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
2092 > move2add_last_label_luid
)
2093 && (MODES_OK_FOR_MOVE2ADD
2094 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
2096 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
2097 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2098 /* Maybe the first register is known to be a
2100 else if (reg_set_luid
[REGNO (base_reg
)]
2101 > move2add_last_label_luid
2102 && (MODES_OK_FOR_MOVE2ADD
2103 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
2104 && reg_base_reg
[REGNO (base_reg
)] < 0)
2106 offset
= reg_offset
[REGNO (base_reg
)];
2107 base_reg
= XEXP (src
, 1);
2126 /* Start tracking the register as a constant. */
2127 reg_base_reg
[regno
] = -1;
2128 reg_symbol_ref
[regno
] = NULL_RTX
;
2129 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2130 /* We assign the same luid to all registers set to constants. */
2131 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2132 reg_mode
[regno
] = mode
;
2137 /* Invalidate the contents of the register. */
2138 reg_set_luid
[regno
] = 0;
2142 base_regno
= REGNO (base_reg
);
2143 /* If information about the base register is not valid, set it
2144 up as a new base register, pretending its value is known
2145 starting from the current insn. */
2146 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
2148 reg_base_reg
[base_regno
] = base_regno
;
2149 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2150 reg_offset
[base_regno
] = 0;
2151 reg_set_luid
[base_regno
] = move2add_luid
;
2152 reg_mode
[base_regno
] = mode
;
2154 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
2155 reg_mode
[base_regno
]))
2158 reg_mode
[regno
] = mode
;
2160 /* Copy base information from our base register. */
2161 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2162 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2163 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2165 /* Compute the sum of the offsets or constants. */
2166 reg_offset
[regno
] = trunc_int_for_mode (offset
2167 + reg_offset
[base_regno
],
2172 unsigned int endregno
= regno
+ nregs
;
2174 for (i
= regno
; i
< endregno
; i
++)
2175 /* Reset the information about this register. */
2176 reg_set_luid
[i
] = 0;
2181 gate_handle_postreload (void)
2183 return (optimize
> 0 && reload_completed
);
2188 rest_of_handle_postreload (void)
2190 if (!dbg_cnt (postreload_cse
))
2193 /* Do a very simple CSE pass over just the hard registers. */
2194 reload_cse_regs (get_insns ());
2195 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2196 Remove any EH edges associated with them. */
2197 if (cfun
->can_throw_non_call_exceptions
)
2198 purge_all_dead_edges ();
2203 struct rtl_opt_pass pass_postreload_cse
=
2207 "postreload", /* name */
2208 gate_handle_postreload
, /* gate */
2209 rest_of_handle_postreload
, /* execute */
2212 0, /* static_pass_number */
2213 TV_RELOAD_CSE_REGS
, /* tv_id */
2214 0, /* properties_required */
2215 0, /* properties_provided */
2216 0, /* properties_destroyed */
2217 0, /* todo_flags_start */
2218 TODO_df_finish
| TODO_verify_rtl_sharing
|
2219 TODO_dump_func
/* todo_flags_finish */