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2019-05-01	Andrew Waterman	RISC-V: Update last ChangeLog entry to mention Andrew... ...last ChangeLog entry to mention Andrew Waterman.	commit \| commitdiff \| tree
2019-04-30	Andrew Waterman	RISC-V: Short-forward-branch opt for SiFive 7 series...	commit \| commitdiff \| tree
2019-03-26	Andrew Waterman	RISC-V: Add sifive-7 pipeline description.	commit \| commitdiff \| tree
2018-10-05	Andrew Waterman	RISC-V: Fix -fsignaling-nans for glibc testsuite.	commit \| commitdiff \| tree
2018-01-23	Andrew Waterman	RISC-V: Add -mpreferred-stack-boundary option. 2018-01-23 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2018-01-17	Andrew Waterman	RISC-V: Mark fsX as call clobbered when soft-float. 2018-01-17 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2018-01-16	Andrew Waterman	RISC-V: Increase mult/div cost if not implemented in... 2018-01-15 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2018-01-02	Andrew Waterman	RISC-V: Fix for icache flush issue on multicore processors.	commit \| commitdiff \| tree
2017-12-08	Andrew Waterman	Add srodata section support to riscv port. 2017-12-07 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-11-07	Andrew Waterman	RISC-V: Implement movmemsi 2017-11-07 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-11-05	Andrew Waterman	RISC-V: If -m[no-]strict-align is not passed, assume... 2017-11-04 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-11-05	Andrew Waterman	RISC-V: Set SLOW_BYTE_ACCESS=1 2017-11-04 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-05-05	Andrew Waterman	RISC-V: Add -mstrict-align option 2017-05-04 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2015-01-21	Andrew Waterman	Avoid misaligned atomic operations Andrew Waterman <waterman@cs.berkeley.edu>	commit \| commitdiff \| tree
2014-11-14	Andrew Waterman	* cas_n.c (libat_compare_exchange): Add missing cast.	commit \| commitdiff \| tree

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