From fe5309c50d6b18379d7bc51a02553fb66b8fade5 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Thu, 21 Jun 2018 22:16:20 +0000 Subject: [PATCH] rs6000.md (extendtfif2): Add missing 128-bit conversion insn that shows up when... 2018-06-21 Michael Meissner * config/rs6000/rs6000.md (extendtfif2): Add missing 128-bit conversion insn that shows up when pr85657-3.c is compiled using IEEE 128-bit long double. From-SVN: r261867 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.md | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 902f8df8b58..ff854f851e6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-06-21 Michael Meissner + + * config/rs6000/rs6000.md (extendtfif2): Add missing 128-bit + conversion insn that shows up when pr85657-3.c is compiled using + IEEE 128-bit long double. + 2018-06-21 Eric Botcazou * cfgrtl.c (fixup_reorder_chain): Do not emit NOPs in DECL_IGNORED_P diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e5c4cf176ea..3044e6eb475 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8158,6 +8158,15 @@ DONE; }) +(define_expand "extendtfif2" + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))] + "TARGET_FLOAT128_TYPE" +{ + rs6000_expand_float128_convert (operands[0], operands[1], false); + DONE; +}) + (define_expand "trunciftf2" [(set (match_operand:TF 0 "gpc_reg_operand") (float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))] -- 2.11.4.GIT