From fd28e4adbec762bfc5f8283586f90c576e7b14ee Mon Sep 17 00:00:00 2001 From: jgreenhalgh Date: Tue, 17 Dec 2013 12:26:10 +0000 Subject: [PATCH] [ARM 2/5 big.LITTLE] Allow tuning parameters without unique tuning targets. gcc/ * config/arm/arm-cores.def: Add new column for TUNE_IDENT. * config/arm/genopt.sh: Improve layout. * config/arm/arm-tune.md: Regenerate. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-opts.h (ARM_CORE): Modify macro for TUNE_IDENT. * config/arm/arm.c (ARM_CORE): Modify macro for TUNE_IDENT. (arm_option_override): When a CPU is chosen, that should also form the tune target. * config/arm/arm.h (ARM_CORE): Modify macro for TUNE_IDENT. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206046 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 12 ++ gcc/config/arm/arm-cores.def | 295 ++++++++++++++++++++++-------------------- gcc/config/arm/arm-opts.h | 5 +- gcc/config/arm/arm-tables.opt | 22 ++-- gcc/config/arm/arm-tune.md | 38 +++++- gcc/config/arm/arm.c | 7 +- gcc/config/arm/arm.h | 4 +- gcc/config/arm/gentune.sh | 2 +- 8 files changed, 219 insertions(+), 166 deletions(-) rewrite gcc/config/arm/arm-cores.def (78%) rewrite gcc/config/arm/arm-tune.md (81%) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 841cd85f90b..5170f2da217 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2013-12-17 James Greenhalgh + * config/arm/arm-cores.def: Add new column for TUNE_IDENT. + * config/arm/genopt.sh: Improve layout. + * config/arm/arm-tune.md: Regenerate. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-opts.h (ARM_CORE): Modify macro for TUNE_IDENT. + * config/arm/arm.c (ARM_CORE): Modify macro for TUNE_IDENT. + (arm_option_override): When a CPU is chosen, that should also + form the tune target. + * config/arm/arm.h (ARM_CORE): Modify macro for TUNE_IDENT. + +2013-12-17 James Greenhalgh + * common/config/arm/arm-common.c (arm_rewrite_selected_cpu): New. (arm_rewrite_mcpu): Likewise. * config/arm/arm-protos.h (arm_rewrite_selected_cpu): New. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def dissimilarity index 78% index e7cea63beae..3264eedd57c 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -1,143 +1,152 @@ -/* ARM CPU Cores - Copyright (C) 2003-2013 Free Software Foundation, Inc. - Written by CodeSourcery, LLC - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -/* Before using #include to read this file, define a macro: - - ARM_CORE(CORE_NAME, CORE_IDENT, ARCH, FLAGS, COSTS) - - The CORE_NAME is the name of the core, represented as a string constant. - The CORE_IDENT is the name of the core, represented as an identifier. - ARCH is the architecture revision implemented by the chip. - FLAGS are the bitwise-or of the traits that apply to that core. - This need not include flags implied by the architecture. - COSTS is the name of the rtx_costs routine to use. - - If you update this table, you must update the "tune" attribute in - arm.md. - - Some tools assume no whitespace up to the first "," in each entry. */ - -/* V2/V2A Architecture Processors */ -ARM_CORE("arm2", arm2, 2, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm250", arm250, 2, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm3", arm3, 2, FL_CO_PROC | FL_MODE26, slowmul) - -/* V3 Architecture Processors */ -ARM_CORE("arm6", arm6, 3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm60", arm60, 3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm600", arm600, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm610", arm610, 3, FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm620", arm620, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm7", arm7, 3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm7d", arm7d, 3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm7di", arm7di, 3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm70", arm70, 3, FL_CO_PROC | FL_MODE26, slowmul) -ARM_CORE("arm700", arm700, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm700i", arm700i, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm710", arm710, 3, FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm720", arm720, 3, FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm710c", arm710c, 3, FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm7100", arm7100, 3, FL_MODE26 | FL_WBUF, slowmul) -ARM_CORE("arm7500", arm7500, 3, FL_MODE26 | FL_WBUF, slowmul) -/* Doesn't have an external co-proc, but does have embedded fpa. */ -ARM_CORE("arm7500fe", arm7500fe, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) - -/* V3M Architecture Processors */ -/* arm7m doesn't exist on its own, but only with D, ("and", and I), but - those don't alter the code, so arm7m is sometimes used. */ -ARM_CORE("arm7m", arm7m, 3M, FL_CO_PROC | FL_MODE26, fastmul) -ARM_CORE("arm7dm", arm7dm, 3M, FL_CO_PROC | FL_MODE26, fastmul) -ARM_CORE("arm7dmi", arm7dmi, 3M, FL_CO_PROC | FL_MODE26, fastmul) - -/* V4 Architecture Processors */ -ARM_CORE("arm8", arm8, 4, FL_MODE26 | FL_LDSCHED, fastmul) -ARM_CORE("arm810", arm810, 4, FL_MODE26 | FL_LDSCHED, fastmul) -ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) -ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) -ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) -ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) -ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul) -ARM_CORE("fa626", fa626, 4, FL_LDSCHED, fastmul) - -/* V4T Architecture Processors */ -ARM_CORE("arm7tdmi", arm7tdmi, 4T, FL_CO_PROC , fastmul) -ARM_CORE("arm7tdmi-s", arm7tdmis, 4T, FL_CO_PROC , fastmul) -ARM_CORE("arm710t", arm710t, 4T, FL_WBUF, fastmul) -ARM_CORE("arm720t", arm720t, 4T, FL_WBUF, fastmul) -ARM_CORE("arm740t", arm740t, 4T, FL_WBUF, fastmul) -ARM_CORE("arm9", arm9, 4T, FL_LDSCHED, fastmul) -ARM_CORE("arm9tdmi", arm9tdmi, 4T, FL_LDSCHED, fastmul) -ARM_CORE("arm920", arm920, 4T, FL_LDSCHED, fastmul) -ARM_CORE("arm920t", arm920t, 4T, FL_LDSCHED, fastmul) -ARM_CORE("arm922t", arm922t, 4T, FL_LDSCHED, fastmul) -ARM_CORE("arm940t", arm940t, 4T, FL_LDSCHED, fastmul) -ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED, fastmul) - -/* V5T Architecture Processors */ -ARM_CORE("arm10tdmi", arm10tdmi, 5T, FL_LDSCHED, fastmul) -ARM_CORE("arm1020t", arm1020t, 5T, FL_LDSCHED, fastmul) - -/* V5TE Architecture Processors */ -ARM_CORE("arm9e", arm9e, 5TE, FL_LDSCHED, 9e) -ARM_CORE("arm946e-s", arm946es, 5TE, FL_LDSCHED, 9e) -ARM_CORE("arm966e-s", arm966es, 5TE, FL_LDSCHED, 9e) -ARM_CORE("arm968e-s", arm968es, 5TE, FL_LDSCHED, 9e) -ARM_CORE("arm10e", arm10e, 5TE, FL_LDSCHED, fastmul) -ARM_CORE("arm1020e", arm1020e, 5TE, FL_LDSCHED, fastmul) -ARM_CORE("arm1022e", arm1022e, 5TE, FL_LDSCHED, fastmul) -ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) -ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) -ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale) -ARM_CORE("fa606te", fa606te, 5TE, FL_LDSCHED, 9e) -ARM_CORE("fa626te", fa626te, 5TE, FL_LDSCHED, 9e) -ARM_CORE("fmp626", fmp626, 5TE, FL_LDSCHED, 9e) -ARM_CORE("fa726te", fa726te, 5TE, FL_LDSCHED, fa726te) - -/* V5TEJ Architecture Processors */ -ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, FL_LDSCHED, 9e) -ARM_CORE("arm1026ej-s", arm1026ejs, 5TEJ, FL_LDSCHED, 9e) - -/* V6 Architecture Processors */ -ARM_CORE("arm1136j-s", arm1136js, 6J, FL_LDSCHED, 9e) -ARM_CORE("arm1136jf-s", arm1136jfs, 6J, FL_LDSCHED | FL_VFPV2, 9e) -ARM_CORE("arm1176jz-s", arm1176jzs, 6ZK, FL_LDSCHED, 9e) -ARM_CORE("arm1176jzf-s", arm1176jzfs, 6ZK, FL_LDSCHED | FL_VFPV2, 9e) -ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e) -ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) -ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2) -ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2) -ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex) -ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5) -ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7) -ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) -ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) -ARM_CORE("cortex-a12", cortexa12, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12) -ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) -ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex_a53) -ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) -ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) -ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) -ARM_CORE("cortex-r7", cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) -ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, v7m) -ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, v7m) -ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m) -ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, v6m) -ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, v6m) -ARM_CORE("marvell-pj4", marvell_pj4, 7A, FL_LDSCHED, 9e) +/* ARM CPU Cores + Copyright (C) 2003-2013 Free Software Foundation, Inc. + Written by CodeSourcery, LLC + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +/* Before using #include to read this file, define a macro: + + ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, ARCH, FLAGS, COSTS) + + The CORE_NAME is the name of the core, represented as a string constant. + The INTERNAL_IDENT is the name of the core represented as an identifier. + This must be unique for each entry in this table. + The TUNE_IDENT is the name of the core for which scheduling decisions + should be made, represented as an identifier. + ARCH is the architecture revision implemented by the chip. + FLAGS are the bitwise-or of the traits that apply to that core. + This need not include flags implied by the architecture. + COSTS is the name of the rtx_costs routine to use. + + If you update this table, you must update the "tune" attribute in + arm.md. + + Some tools assume no whitespace up to the first "," in each entry. */ + +/* V2/V2A Architecture Processors */ +ARM_CORE("arm2", arm2, arm2, 2, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm250", arm250, arm250, 2, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm3", arm3, arm3, 2, FL_CO_PROC | FL_MODE26, slowmul) + +/* V3 Architecture Processors */ +ARM_CORE("arm6", arm6, arm6, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm60", arm60, arm60, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm600", arm600, arm600, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm610", arm610, arm610, 3, FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm620", arm620, arm620, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm7", arm7, arm7, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm7d", arm7d, arm7d, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm7di", arm7di, arm7di, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm70", arm70, arm70, 3, FL_CO_PROC | FL_MODE26, slowmul) +ARM_CORE("arm700", arm700, arm700, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm700i", arm700i, arm700i, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm710", arm710, arm710, 3, FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm720", arm720, arm720, 3, FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm710c", arm710c, arm710c, 3, FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm7100", arm7100, arm7100, 3, FL_MODE26 | FL_WBUF, slowmul) +ARM_CORE("arm7500", arm7500, arm7500, 3, FL_MODE26 | FL_WBUF, slowmul) +/* Doesn't have an external co-proc, but does have embedded fpa. */ +ARM_CORE("arm7500fe", arm7500fe, arm7500fe, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul) + +/* V3M Architecture Processors */ +/* arm7m doesn't exist on its own, but only with D, ("and", and I), but + those don't alter the code, so arm7m is sometimes used. */ +ARM_CORE("arm7m", arm7m, arm7m, 3M, FL_CO_PROC | FL_MODE26, fastmul) +ARM_CORE("arm7dm", arm7dm, arm7dm, 3M, FL_CO_PROC | FL_MODE26, fastmul) +ARM_CORE("arm7dmi", arm7dmi, arm7dmi, 3M, FL_CO_PROC | FL_MODE26, fastmul) + +/* V4 Architecture Processors */ +ARM_CORE("arm8", arm8, arm8, 4, FL_MODE26 | FL_LDSCHED, fastmul) +ARM_CORE("arm810", arm810, arm810, 4, FL_MODE26 | FL_LDSCHED, fastmul) +ARM_CORE("strongarm", strongarm, strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("strongarm110", strongarm110, strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm) +ARM_CORE("fa526", fa526, fa526, 4, FL_LDSCHED, fastmul) +ARM_CORE("fa626", fa626, fa626, 4, FL_LDSCHED, fastmul) + +/* V4T Architecture Processors */ +ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, 4T, FL_CO_PROC, fastmul) +ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, 4T, FL_CO_PROC, fastmul) +ARM_CORE("arm710t", arm710t, arm710t, 4T, FL_WBUF, fastmul) +ARM_CORE("arm720t", arm720t, arm720t, 4T, FL_WBUF, fastmul) +ARM_CORE("arm740t", arm740t, arm740t, 4T, FL_WBUF, fastmul) +ARM_CORE("arm9", arm9, arm9, 4T, FL_LDSCHED, fastmul) +ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, 4T, FL_LDSCHED, fastmul) +ARM_CORE("arm920", arm920, arm920, 4T, FL_LDSCHED, fastmul) +ARM_CORE("arm920t", arm920t, arm920t, 4T, FL_LDSCHED, fastmul) +ARM_CORE("arm922t", arm922t, arm922t, 4T, FL_LDSCHED, fastmul) +ARM_CORE("arm940t", arm940t, arm940t, 4T, FL_LDSCHED, fastmul) +ARM_CORE("ep9312", ep9312, ep9312, 4T, FL_LDSCHED, fastmul) + +/* V5T Architecture Processors */ +ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, 5T, FL_LDSCHED, fastmul) +ARM_CORE("arm1020t", arm1020t, arm1020t, 5T, FL_LDSCHED, fastmul) + +/* V5TE Architecture Processors */ +ARM_CORE("arm9e", arm9e, arm9e, 5TE, FL_LDSCHED, 9e) +ARM_CORE("arm946e-s", arm946es, arm946es, 5TE, FL_LDSCHED, 9e) +ARM_CORE("arm966e-s", arm966es, arm966es, 5TE, FL_LDSCHED, 9e) +ARM_CORE("arm968e-s", arm968es, arm968es, 5TE, FL_LDSCHED, 9e) +ARM_CORE("arm10e", arm10e, arm10e, 5TE, FL_LDSCHED, fastmul) +ARM_CORE("arm1020e", arm1020e, arm1020e, 5TE, FL_LDSCHED, fastmul) +ARM_CORE("arm1022e", arm1022e, arm1022e, 5TE, FL_LDSCHED, fastmul) +ARM_CORE("xscale", xscale, xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale) +ARM_CORE("iwmmxt", iwmmxt, iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale) +ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale) +ARM_CORE("fa606te", fa606te, fa606te, 5TE, FL_LDSCHED, 9e) +ARM_CORE("fa626te", fa626te, fa626te, 5TE, FL_LDSCHED, 9e) +ARM_CORE("fmp626", fmp626, fmp626, 5TE, FL_LDSCHED, 9e) +ARM_CORE("fa726te", fa726te, fa726te, 5TE, FL_LDSCHED, fa726te) + +/* V5TEJ Architecture Processors */ +ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, 5TEJ, FL_LDSCHED, 9e) +ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, 5TEJ, FL_LDSCHED, 9e) + +/* V6 Architecture Processors */ +ARM_CORE("arm1136j-s", arm1136js, arm1136js, 6J, FL_LDSCHED, 9e) +ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, 6J, FL_LDSCHED | FL_VFPV2, 9e) +ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, 6ZK, FL_LDSCHED, 9e) +ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, 6ZK, FL_LDSCHED | FL_VFPV2, 9e) +ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, 6K, FL_LDSCHED, 9e) +ARM_CORE("mpcore", mpcore, mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) +ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, 6T2, FL_LDSCHED, v6t2) +ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2) + +/* V6M Architecture Processors */ +ARM_CORE("cortex-m1", cortexm1, cortexm1, 6M, FL_LDSCHED, v6m) +ARM_CORE("cortex-m0", cortexm0, cortexm0, 6M, FL_LDSCHED, v6m) +ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, FL_LDSCHED, v6m) + +/* V7 Architecture Processors */ +ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, FL_LDSCHED, cortex) +ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, FL_LDSCHED, cortex_a5) +ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7) +ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, FL_LDSCHED, cortex) +ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, FL_LDSCHED, cortex_a9) +ARM_CORE("cortex-a12", cortexa12, cortexa12, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12) +ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) +ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, FL_LDSCHED, cortex) +ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, FL_LDSCHED, cortex) +ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) +ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) +ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m) +ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m) +ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e) + +/* V8 Architecture Processors */ +ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED, cortex_a53) diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index a3ef36453c0..dab308ee3c3 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -23,8 +23,9 @@ /* The various ARM cores. */ enum processor_type { -#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ - IDENT, +#undef ARM_CORE +#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ + INTERNAL_IDENT, #include "arm-cores.def" #undef ARM_CORE /* Used to indicate that no processor has been specified. */ diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index b3e7a7c62d7..7da7cc8e910 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -232,6 +232,15 @@ EnumValue Enum(processor_type) String(arm1156t2f-s) Value(arm1156t2fs) EnumValue +Enum(processor_type) String(cortex-m1) Value(cortexm1) + +EnumValue +Enum(processor_type) String(cortex-m0) Value(cortexm0) + +EnumValue +Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus) + +EnumValue Enum(processor_type) String(generic-armv7-a) Value(genericv7a) EnumValue @@ -253,9 +262,6 @@ EnumValue Enum(processor_type) String(cortex-a15) Value(cortexa15) EnumValue -Enum(processor_type) String(cortex-a53) Value(cortexa53) - -EnumValue Enum(processor_type) String(cortex-r4) Value(cortexr4) EnumValue @@ -274,16 +280,10 @@ EnumValue Enum(processor_type) String(cortex-m3) Value(cortexm3) EnumValue -Enum(processor_type) String(cortex-m1) Value(cortexm1) - -EnumValue -Enum(processor_type) String(cortex-m0) Value(cortexm0) - -EnumValue -Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus) +Enum(processor_type) String(marvell-pj4) Value(marvell_pj4) EnumValue -Enum(processor_type) String(marvell-pj4) Value(marvell_pj4) +Enum(processor_type) String(cortex-a53) Value(cortexa53) Enum Name(arm_arch) Type(int) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md dissimilarity index 81% index e10d0aa9544..0386afff742 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -1,5 +1,33 @@ -;; -*- buffer-read-only: t -*- -;; Generated automatically by gentune.sh from arm-cores.def -(define_attr "tune" - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa12,cortexa15,cortexa53,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" - (const (symbol_ref "((enum attr_tune) arm_tune)"))) +;; -*- buffer-read-only: t -*- +;; Generated automatically by gentune.sh from arm-cores.def +(define_attr "tune" + "arm2,arm250,arm3, + arm6,arm60,arm600, + arm610,arm620,arm7, + arm7d,arm7di,arm70, + arm700,arm700i,arm710, + arm720,arm710c,arm7100, + arm7500,arm7500fe,arm7m, + arm7dm,arm7dmi,arm8, + arm810,strongarm,strongarm110, + strongarm1100,strongarm1110,fa526, + fa626,arm7tdmi,arm7tdmis, + arm710t,arm720t,arm740t, + arm9,arm9tdmi,arm920, + arm920t,arm922t,arm940t, + ep9312,arm10tdmi,arm1020t, + arm9e,arm946es,arm966es, + arm968es,arm10e,arm1020e, + arm1022e,xscale,iwmmxt, + iwmmxt2,fa606te,fa626te, + fmp626,fa726te,arm926ejs, + arm1026ejs,arm1136js,arm1136jfs, + arm1176jzs,arm1176jzfs,mpcorenovfp, + mpcore,arm1156t2s,arm1156t2fs, + cortexm1,cortexm0,cortexm0plus, + genericv7a,cortexa5,cortexa7, + cortexa8,cortexa9,cortexa12, + cortexa15,cortexr4,cortexr4f, + cortexr5,cortexr7,cortexm4, + cortexm3,marvell_pj4,cortexa53" + (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a4ab6be5e8b..2bc9bf10d9c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1742,7 +1742,7 @@ const struct tune_params arm_fa726te_tune = static const struct processors all_cores[] = { /* ARM Cores */ -#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ +#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \ {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH, \ FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, #include "arm-cores.def" @@ -2251,7 +2251,10 @@ arm_option_override (void) arm_selected_arch = &all_architectures[arm_arch_option]; if (global_options_set.x_arm_cpu_option) - arm_selected_cpu = &all_cores[(int) arm_cpu_option]; + { + arm_selected_cpu = &all_cores[(int) arm_cpu_option]; + arm_selected_tune = &all_cores[(int) arm_cpu_option]; + } if (global_options_set.x_arm_tune_option) arm_selected_tune = &all_cores[(int) arm_tune_option]; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 6539ec6ffc2..7b5a7f98e31 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -162,8 +162,8 @@ extern char arm_arch_name[]; enum target_cpus { -#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ - TARGET_CPU_##IDENT, +#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ + TARGET_CPU_##INTERNAL_IDENT, #include "arm-cores.def" #undef ARM_CORE TARGET_CPU_generic diff --git a/gcc/config/arm/gentune.sh b/gcc/config/arm/gentune.sh index 725ae0fe6d1..2893ab4ef8d 100755 --- a/gcc/config/arm/gentune.sh +++ b/gcc/config/arm/gentune.sh @@ -25,5 +25,5 @@ echo ";; Generated automatically by gentune.sh from arm-cores.def" allcores=`awk -F'[(, ]+' '/^ARM_CORE/ { cores = cores$3"," } END { print cores } ' $1` echo "(define_attr \"tune\"" -echo " \"$allcores\"" | sed -e 's/,"$/"/' +echo " \"$allcores\"" | sed -e 's/,"$/"/' | sed -e 's/\([a-z0-9_]\+,[a-z0-9_]\+,[a-z0-9_]\+,\)/\1\n\t/g' echo " (const (symbol_ref \"((enum attr_tune) arm_tune)\")))" -- 2.11.4.GIT