From f8b30f6b715a7b40dbd452dbe76c5b3c4753a47a Mon Sep 17 00:00:00 2001 From: clyon Date: Thu, 6 Feb 2014 12:55:27 +0000 Subject: [PATCH] Merge from branches/gcc-4_8-branch up to rev 207411. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro@207552 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc-4_8-branch/gcc/ChangeLog | 496 +++++++++++++++++++++ gcc-4_8-branch/gcc/DATESTAMP | 2 +- gcc-4_8-branch/gcc/ada/ChangeLog | 7 + gcc-4_8-branch/gcc/ada/gcc-interface/cuintp.c | 21 +- gcc-4_8-branch/gcc/builtins.c | 35 +- gcc-4_8-branch/gcc/c/ChangeLog | 15 + gcc-4_8-branch/gcc/c/c-typeck.c | 21 +- gcc-4_8-branch/gcc/cfgcleanup.c | 18 +- gcc-4_8-branch/gcc/cfgexpand.c | 6 +- gcc-4_8-branch/gcc/cgraphbuild.c | 6 +- gcc-4_8-branch/gcc/config/aarch64/aarch64.c | 2 +- gcc-4_8-branch/gcc/config/arm/arm-ldmstm.ml | 7 +- gcc-4_8-branch/gcc/config/arm/arm.c | 9 +- gcc-4_8-branch/gcc/config/arm/arm.md | 6 +- gcc-4_8-branch/gcc/config/arm/ldmstm.md | 342 +++++++------- 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b/gcc-4_8-branch/gcc/ChangeLog index 40449e126d8..af97b9cca80 100644 --- a/gcc-4_8-branch/gcc/ChangeLog +++ b/gcc-4_8-branch/gcc/ChangeLog @@ -1,3 +1,499 @@ +2014-02-02 Uros Bizjak + + Backport from mainline + 2014-01-30 Jakub Jelinek + + * config/i386/f16cintrin.h (_cvtsh_ss): Avoid -Wnarrowing warning. + +2014-01-31 Richard Henderson + + PR middle-end/60004 + * tree-eh.c (lower_try_finally_switch): Delay lowering finally block + until after else_eh is processed. + +2014-01-30 David Holsgrove + + Backport from mainline + * config/microblaze/microblaze.md(cstoresf4, cbranchsf4): Replace + comparison_operator with ordered_comparison_operator. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and + avoid clobbering a live register. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}. + * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier + insns before bundling. + * config/tilegx/tilegx.md (tile_network_barrier): Update comment. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set + PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. + * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilepro/tilepro.md (ctzdi2): Use register_operand + predicate. + (clzdi2): Ditto. + (ffsdi2): Ditto. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New. + (TARGET_EXPAND_TO_RTL_HOOK): Define. + +2014-01-24 H.J. Lu + + Backport from mainline + 2014-01-23 H.J. Lu + + PR target/59929 + * config/i386/i386.md (pushsf splitter): Get stack adjustment + from push operand if code of push isn't PRE_DEC. + +2014-01-23 David Holsgrove + + Backport from mainline. + * config/microblaze/microblaze.md: Add trap insn and attribute + +2014-01-23 Marek Polacek + + Backport from mainline + 2013-10-21 Marek Polacek + + PR middle-end/58809 + * fold-const.c (fold_range_test): Return 0 if the type is not + an integral type. + +2014-01-22 David Holsgrove + + * config/microblaze/microblaze.md: Correct bswaphi2 insn. + +2014-01-22 Uros Bizjak + + Backport from mainline + 2014-01-20 Uros Bizjak + + * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false + for SImode_address_operand operands, having only a REG argument. + + 2014-01-20 Jakub Jelinek + + PR target/59880 + * config/i386/i386.c (ix86_avoid_lea_for_addr): Return false + if operands[1] is a REG or ZERO_EXTEND of a REG. + + 2014-01-18 Uros Bizjak + H.J. Lu + + PR target/59379 + * config/i386/i386.md (*lea): Zero-extend return register + to DImode for zero-extended addresses. + +2014-01-21 Andrew Pinski + Steve Ellcey + + PR target/59462 + * config/mips/mips.c (mips_print_operand): Check operand mode instead + of operator mode. + +2014-01-21 Andrey Belevantsev + + Backport from mainline + 2013-12-23 Andrey Belevantsev + + PR rtl-optimization/57422 + * sel-sched.c (mark_unavailable_hard_regs): Fix typo when calling + add_to_hard_reg_set. + +2014-01-20 Jakub Jelinek + + PR middle-end/59860 + * tree.h (fold_builtin_strcat): New prototype. + * builtins.c (fold_builtin_strcat): No longer static. Add len + argument, if non-NULL, don't call c_strlen. Optimize + directly into __builtin_memcpy instead of __builtin_strcpy. + (fold_builtin_2): Adjust fold_builtin_strcat caller. + * gimple-fold.c (gimple_fold_builtin): Handle BUILT_IN_STRCAT. + +2014-01-20 Richard Biener + + PR middle-end/59860 + * builtins.c (fold_builtin_strcat): Remove case better handled + by tree-ssa-strlen.c. + +2014-01-19 John David Anglin + + * config/pa/pa.c (pa_attr_length_millicode_call): Correct length of + long non-pic millicode calls. + +2014-01-17 John David Anglin + + * config/pa/pa.c (pa_attr_length_indirect_call): Don't output a short + call to $$dyncall when TARGET_LONG_CALLS is true. + +2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-14 H.J. Lu + + PR target/59794 + * config/i386/i386.c (type_natural_mode): Add a bool parameter + to indicate if type is used for function return value. Warn + ABI change if the vector mode isn't available for function + return value. + (ix86_function_arg_advance): Pass false to type_natural_mode. + (ix86_function_arg): Likewise. + (ix86_gimplify_va_arg): Likewise. + (function_arg_32): Don't warn ABI change. + (ix86_function_value): Pass true to type_natural_mode. + (ix86_return_in_memory): Likewise. + (ix86_struct_value_rtx): Removed. + (TARGET_STRUCT_VALUE_RTX): Likewise. + +2014-01-17 Charles Baylis + + Backport from mainline + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/arm-ldmstm.ml: Use low_register_operand for Thumb + patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (arm_hard_general_register_operand): + New predicate. + (arm_hard_register_operand): Remove. + * config/arm/arm-ldmstm.ml: Use arm_hard_general_register_operand + for all patterns. + * config/arm/ldmstm.md: Regenerate. + + 2013-12-19 Charles Baylis + + PR target/59142 + * config/arm/predicates.md (vfp_hard_register_operand): New predicate. + * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use + vfp_hard_register_operand. + +2014-01-17 Kugan Vivekanandarajah + + Backport from mainline + 2014-01-15 Matthew Gretton-Dann + Kugan Vivekanandarajah + + PR target/59695 + * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect + truncation. + +2014-01-17 Terry Guo + + PR target/59826 + * config/arm/arm.md (prefetch): Set insn type attribute to load1. + +2014-01-16 Jakub Jelinek + + PR target/59839 + * config/i386/i386.c (ix86_expand_builtin): If target doesn't + satisfy operand 0 predicate for gathers, use a new pseudo as + subtarget. + +2014-01-16 Richard Henderson + + PR debug/54694 + * reginfo.c (global_regs_decl): Globalize. + * rtl.h (global_regs_decl): Declare. + * ira.c (do_reload): Diagnose frame_pointer_needed and it + reserved via global_regs. + +2014-01-16 Peter Bergner + + Backport from mainline + 2014-01-15 Uros Bizjak + + * config/i386/i386.c (ix86_hard_regno_mode_ok): Use + VALID_AVX256_REG_OR_OI_MODE. + + 2013-09-05 Peter Bergner + + PR target/58139 + * reginfo.c (choose_hard_reg_mode): Scan through all mode classes + looking for widest mode. + +2014-01-16 Marek Polacek + + Backported from mainline + 2014-01-16 Marek Polacek + + PR middle-end/59827 + * gimple-low.c (gimple_check_call_args): Don't use DECL_ARG_TYPE if + it is error_mark_node. + +2014-01-15 Andreas Krebbel + + PR target/59803 + * config/s390/s390.c (s390_preferred_reload_class): Don't return + ADDR_REGS for invalid symrefs in non-PIC code. + +2014-01-14 Uros Bizjak + + Revert: + 2014-01-08 Uros Bizjak + + * config/i386/i386.c (ix86_data_alignment): Calculate max_align + from prefetch_block tune setting. + +2014-01-13 Jakub Jelinek + + Backported from mainline + 2014-01-10 Jakub Jelinek + + PR tree-optimization/59745 + * tree-predcom.c (tree_predictive_commoning_loop): Call + free_affine_expand_cache if giving up because components is NULL. + +2014-01-10 Yufeng Zhang + + * config/arm/arm.c (arm_expand_neon_args): Call expand_expr + with EXPAND_MEMORY for NEON_ARG_MEMORY; check if the returned + rtx is const0_rtx or not. + +2014-01-10 Andreas Krebbel + + * config/s390/s390.c (s390_expand_tbegin): Remove jump over CC + extraction in good case. + +2014-01-10 Huacai Chen + + * config/mips/driver-native.c (host_detect_local_cpu): Handle new + kernel strings for Loongson-2E/2F/3A. + +2014-01-10 Richard Biener + + PR tree-optimization/59715 + * tree-flow.h (split_critical_edges): Declare. + * tree-cfg.c (split_critical_edges): Export. + * tree-ssa-sink.c (execute_sink_code): Split critical edges. + +2014-01-09 Richard Sandiford + + * config/mips/mips.h (ISA_HAS_WSBH): Define. + * config/mips/mips.md (UNSPEC_WSBH, UNSPEC_DSBH, UNSPEC_DSHD): New + constants. + (bswaphi2, bswapsi2, bswapdi2, wsbh, dsbh, dshd): New patterns. + +2014-01-09 Richard Sandiford + + PR rtl-optimization/59137 + * reorg.c (steal_delay_list_from_target): Call update_block for + elided insns. + (steal_delay_list_from_fallthrough, relax_delay_slots): Likewise. + +2014-01-09 Richard Sandiford + + Revert: + 2012-10-07 Richard Sandiford + + * config/mips/mips.c (mips_truncated_op_cost): New function. + (mips_rtx_costs): Adjust test for BADDU. + * config/mips/mips.md (*baddu_di): Push truncates to operands. + + 2012-10-02 Richard Sandiford + + * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... + (*baddu_si): ...this new pattern. + +2014-01-09 Richard Biener + + Backport from mainline + 2013-11-18 Richard Biener + + PR tree-optimization/59125 + PR tree-optimization/54570 + * tree-ssa-sccvn.c (copy_reference_ops_from_ref): When inlining + is not complete do not treat component-references with offset zero + but different fields as equal. + * tree-object-size.c: Include tree-phinodes.h and ssa-iterators.h. + (compute_object_sizes): Apply TLC. Propagate the constant + results into all uses and fold their stmts. + * passes.def (pass_all_optimizations): Move pass_object_sizes + after the first pass_forwprop and before pass_fre. + + 2013-12-03 Jakub Jelinek + + PR tree-optimization/59362 + * tree-object-size.c (object_sizes): Change into array of + vec. + (compute_builtin_object_size): Check computed bitmap for + non-NULL instead of object_sizes. Call safe_grow on object_sizes + vector if new SSA_NAMEs appeared. + (init_object_sizes): Check computed bitmap for non-NULL. + Call safe_grow on object_sizes elements instead of initializing + it with XNEWVEC. + (fini_object_sizes): Call release on object_sizes elements, don't + set it to NULL. + +2014-01-09 Richard Earnshaw + + PR rtl-optimization/54300 + * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused + outputs in a single-set are killed from the value chains. + +2014-01-09 Jakub Jelinek + + PR rtl-optimization/59724 + * ifcvt.c (cond_exec_process_if_block): Don't call + flow_find_head_matching_sequence with 0 longest_match. + * cfgcleanup.c (flow_find_head_matching_sequence): Count even + non-active insns if !stop_after. + (try_head_merge_bb): Revert 2014-01-07 changes. + +2014-01-09 Hans-Peter Nilsson + + Backport from mainline + 2013-12-23 Hans-Peter Nilsson + + PR middle-end/59584 + * config/cris/predicates.md (cris_nonsp_register_operand): + New define_predicate. + * config/cris/cris.md: Replace register_operand with + cris_nonsp_register_operand for destinations in all + define_splits where a register is set more than once. + +2014-01-08 H.J. Lu + + Backport from mainline + 2013-12-25 H.J. Lu + + PR target/59587 + * config/i386/i386.c (struct ptt): Add a field for processor name. + (processor_target_table): Sync with processor_type. Add + processor names. + (cpu_names): Removed. + (ix86_option_override_internal): Default x_ix86_tune_string + to processor_target_table[TARGET_CPU_DEFAULT].name. + (ix86_function_specific_print): Assert arch and tune < + PROCESSOR_max. Use processor_target_table to print arch and + tune names. + * config/i386/i386.h (TARGET_CPU_DEFAULT): Default to + PROCESSOR_GENERIC32. + (target_cpu_default): Removed. + (processor_type): Reordered. + +2014-01-08 Uros Bizjak + + Backport from mainline + 2014-01-05 Uros Bizjak + + * config/i386/i386.c (ix86_data_alignment): Calculate max_align + from prefetch_block tune setting. + (nocona_cost): Correct size of prefetch block to 64. + +2014-01-08 Martin Jambor + + PR ipa/59610 + * ipa-prop.c (ipa_compute_jump_functions): Bail out if not optimizing. + (parm_preserved_before_stmt_p): Assume modification present when not + optimizing. + +2014-01-07 John David Anglin + + PR target/59652 + * config/pa/pa.c (pa_legitimate_address_p): Return false before reload + for 14-bit register offsets when INT14_OK_STRICT is false. + +2014-01-07 Roland Stigge + Michael Meissner + + PR 57386/target + * config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p): + Only check TFmode for SPE constants. Don't check TImode or TDmode. + +2014-01-07 Jakub Jelinek + + PR rtl-optimization/58668 + * cfgcleanup.c (flow_find_cross_jump): Don't count + any jumps if dir_p is NULL. Remove p1 variable and make USE/CLOBBER + check consistent with other places. + (flow_find_head_matching_sequence): Don't count USE or CLOBBER insns. + (try_head_merge_bb): Adjust for the flow_find_head_matching_sequence + counting change. + * ifcvt.c (count_bb_insns): Don't count USE or CLOBBER insns. + +2014-01-07 Mike Stump + Jakub Jelinek + + PR pch/59436 + * tree.h (struct tree_optimization_option): Change optabs + type from unsigned char * to void *. + * optabs.c (init_tree_optimization_optabs): Adjust + TREE_OPTIMIZATION_OPTABS initialization. + +2014-01-07 Jakub Jelinek + + Backported from mainline + 2013-12-16 Jakub Jelinek + + PR middle-end/58956 + PR middle-end/59470 + * gimple.h (walk_stmt_load_store_addr_fn): New typedef. + (walk_stmt_load_store_addr_ops, walk_stmt_load_store_ops): Use it + for callback params. + * gimple.c (walk_stmt_load_store_ops): Likewise. + (walk_stmt_load_store_addr_ops): Likewise. Adjust all callback + calls to supply the gimple operand containing the base tree + as an extra argument. + * tree-ssa-ter.c (find_ssaname, find_ssaname_in_store): New helper + functions. + (find_replaceable_in_bb): For calls or GIMPLE_ASM, only set + same_root_var if USE is used somewhere in the stores of the stmt. + * ipa-prop.c (visit_ref_for_mod_analysis): Remove name of the stmt + argument and ATTRIBUTE_UNUSED, add another unnamed tree argument. + * ipa-pure-const.c (check_load, check_store, check_ipa_load, + check_ipa_store): Likewise. + * gimple.c (gimple_ior_addresses_taken_1): Likewise. + * ipa-split.c (test_nonssa_use, mark_nonssa_use): Likewise. + (verify_non_ssa_vars, visit_bb): Adjust their callers. + * cfgexpand.c (add_scope_conflicts_1): Use + walk_stmt_load_store_addr_fn type for visit variable. + (visit_op, visit_conflict): Remove name of the stmt + argument and ATTRIBUTE_UNUSED, add another unnamed tree argument. + * tree-sra.c (asm_visit_addr): Likewise. Remove name of the data + argument and ATTRIBUTE_UNUSED. + * cgraphbuild.c (mark_address, mark_load, mark_store): Add another + unnamed tree argument. + 2014-01-03 Andreas Schwab * config/m68k/m68k.c (handle_move_double): Handle pushes with diff --git a/gcc-4_8-branch/gcc/DATESTAMP b/gcc-4_8-branch/gcc/DATESTAMP index f6c22fefd2f..6b7c04d7d87 100644 --- a/gcc-4_8-branch/gcc/DATESTAMP +++ b/gcc-4_8-branch/gcc/DATESTAMP @@ -1 +1 @@ -20140106 +20140203 diff --git a/gcc-4_8-branch/gcc/ada/ChangeLog b/gcc-4_8-branch/gcc/ada/ChangeLog index 944bcf6e345..5f62d18f315 100644 --- a/gcc-4_8-branch/gcc/ada/ChangeLog +++ b/gcc-4_8-branch/gcc/ada/ChangeLog @@ -1,3 +1,10 @@ +2014-01-12 Eric Botcazou + + PR ada/59772 + * gcc-interface/cuintp.c (build_cst_from_int): Use 32-bit integer type + as intermediate type. + (UI_To_gnu): Likewise. + 2013-12-12 Eric Botcazou Iain Sandoe diff --git a/gcc-4_8-branch/gcc/ada/gcc-interface/cuintp.c b/gcc-4_8-branch/gcc/ada/gcc-interface/cuintp.c index e077d9ce009..f4d75eca2eb 100644 --- a/gcc-4_8-branch/gcc/ada/gcc-interface/cuintp.c +++ b/gcc-4_8-branch/gcc/ada/gcc-interface/cuintp.c @@ -6,7 +6,7 @@ * * * C Implementation File * * * - * Copyright (C) 1992-2012, Free Software Foundation, Inc. * + * Copyright (C) 1992-2014, Free Software Foundation, Inc. * * * * GNAT is free software; you can redistribute it and/or modify it under * * terms of the GNU General Public License as published by the Free Soft- * @@ -59,8 +59,8 @@ static tree build_cst_from_int (tree type, HOST_WIDE_INT low) { - if (TREE_CODE (type) == REAL_TYPE) - return convert (type, build_int_cst (NULL_TREE, low)); + if (SCALAR_FLOAT_TYPE_P (type)) + return convert (type, build_int_cst (gnat_type_for_size (32, 0), low)); else return build_int_cst_type (type, low); } @@ -99,19 +99,12 @@ UI_To_gnu (Uint Input, tree type) gcc_assert (Length > 0); /* The computations we perform below always require a type at least as - large as an integer not to overflow. REAL types are always fine, but + large as an integer not to overflow. FP types are always fine, but INTEGER or ENUMERAL types we are handed may be too short. We use a base integer type node for the computations in this case and will - convert the final result back to the incoming type later on. - The base integer precision must be superior than 16. */ - - if (TREE_CODE (comp_type) != REAL_TYPE - && TYPE_PRECISION (comp_type) - < TYPE_PRECISION (long_integer_type_node)) - { - comp_type = long_integer_type_node; - gcc_assert (TYPE_PRECISION (comp_type) > 16); - } + convert the final result back to the incoming type later on. */ + if (!SCALAR_FLOAT_TYPE_P (comp_type) && TYPE_PRECISION (comp_type) < 32) + comp_type = gnat_type_for_size (32, 0); gnu_base = build_cst_from_int (comp_type, Base); diff --git a/gcc-4_8-branch/gcc/builtins.c b/gcc-4_8-branch/gcc/builtins.c index c977df0fea3..1be69686bee 100644 --- a/gcc-4_8-branch/gcc/builtins.c +++ b/gcc-4_8-branch/gcc/builtins.c @@ -180,7 +180,6 @@ static tree fold_builtin_varargs (location_t, tree, tree, bool); static tree fold_builtin_strpbrk (location_t, tree, tree, tree); static tree fold_builtin_strstr (location_t, tree, tree, tree); static tree fold_builtin_strrchr (location_t, tree, tree, tree); -static tree fold_builtin_strcat (location_t, tree, tree); static tree fold_builtin_strncat (location_t, tree, tree, tree); static tree fold_builtin_strspn (location_t, tree, tree); static tree fold_builtin_strcspn (location_t, tree, tree); @@ -10770,7 +10769,7 @@ fold_builtin_2 (location_t loc, tree fndecl, tree arg0, tree arg1, bool ignore) return fold_builtin_strstr (loc, arg0, arg1, type); case BUILT_IN_STRCAT: - return fold_builtin_strcat (loc, arg0, arg1); + return fold_builtin_strcat (loc, arg0, arg1, NULL_TREE); case BUILT_IN_STRSPN: return fold_builtin_strspn (loc, arg0, arg1); @@ -11813,8 +11812,9 @@ fold_builtin_strpbrk (location_t loc, tree s1, tree s2, tree type) COMPOUND_EXPR in the chain will contain the tree for the simplified form of the builtin function call. */ -static tree -fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) +tree +fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src, + tree len) { if (!validate_arg (dst, POINTER_TYPE) || !validate_arg (src, POINTER_TYPE)) @@ -11832,22 +11832,17 @@ fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) /* See if we can store by pieces into (dst + strlen(dst)). */ tree newdst, call; tree strlen_fn = builtin_decl_implicit (BUILT_IN_STRLEN); - tree strcpy_fn = builtin_decl_implicit (BUILT_IN_STRCPY); + tree memcpy_fn = builtin_decl_implicit (BUILT_IN_MEMCPY); - if (!strlen_fn || !strcpy_fn) + if (!strlen_fn || !memcpy_fn) return NULL_TREE; - /* If we don't have a movstr we don't want to emit an strcpy - call. We have to do that if the length of the source string - isn't computable (in that case we can use memcpy probably - later expanding to a sequence of mov instructions). If we - have movstr instructions we can emit strcpy calls. */ - if (!HAVE_movstr) - { - tree len = c_strlen (src, 1); - if (! len || TREE_SIDE_EFFECTS (len)) - return NULL_TREE; - } + /* If the length of the source string isn't computable don't + split strcat into strlen and memcpy. */ + if (! len) + len = c_strlen (src, 1); + if (! len || TREE_SIDE_EFFECTS (len)) + return NULL_TREE; /* Stabilize the argument list. */ dst = builtin_save_expr (dst); @@ -11859,7 +11854,11 @@ fold_builtin_strcat (location_t loc ATTRIBUTE_UNUSED, tree dst, tree src) newdst = fold_build_pointer_plus_loc (loc, dst, newdst); newdst = builtin_save_expr (newdst); - call = build_call_expr_loc (loc, strcpy_fn, 2, newdst, src); + len = fold_convert_loc (loc, size_type_node, len); + len = size_binop_loc (loc, PLUS_EXPR, len, + build_int_cst (size_type_node, 1)); + + call = build_call_expr_loc (loc, memcpy_fn, 3, newdst, src, len); return build2 (COMPOUND_EXPR, TREE_TYPE (dst), call, dst); } return NULL_TREE; diff --git a/gcc-4_8-branch/gcc/c/ChangeLog b/gcc-4_8-branch/gcc/c/ChangeLog index d487a6e6d67..d1502d18744 100644 --- a/gcc-4_8-branch/gcc/c/ChangeLog +++ b/gcc-4_8-branch/gcc/c/ChangeLog @@ -1,3 +1,18 @@ +2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * c-typeck.c (c_finish_omp_clause): Reject MIN_EXPR, MAX_EXPR, + BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs. + +2014-01-22 Marek Polacek + + Backport from mainline + 2014-01-22 Marek Polacek + + PR c/59891 + * c-typeck.c (build_conditional_expr): Call c_fully_fold instead + of remove_c_maybe_const_expr on op1 and op2. + 2013-12-03 Marek Polacek Backport from mainline diff --git a/gcc-4_8-branch/gcc/c/c-typeck.c b/gcc-4_8-branch/gcc/c/c-typeck.c index 428fba92da0..b0ef90a5869 100644 --- a/gcc-4_8-branch/gcc/c/c-typeck.c +++ b/gcc-4_8-branch/gcc/c/c-typeck.c @@ -4334,8 +4334,10 @@ build_conditional_expr (location_t colon_loc, tree ifexp, bool ifexp_bcp, { if (int_operands) { - op1 = remove_c_maybe_const_expr (op1); - op2 = remove_c_maybe_const_expr (op2); + /* Use c_fully_fold here, since C_MAYBE_CONST_EXPR might be + nested inside of the expression. */ + op1 = c_fully_fold (op1, false, NULL); + op2 = c_fully_fold (op2, false, NULL); } ret = build3 (COND_EXPR, result_type, ifexp, op1, op2); if (int_operands) @@ -10621,7 +10623,8 @@ c_finish_omp_clauses (tree clauses) "%qE has invalid type for %", t); remove = true; } - else if (FLOAT_TYPE_P (TREE_TYPE (t))) + else if (FLOAT_TYPE_P (TREE_TYPE (t)) + || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) { enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c); const char *r_name = NULL; @@ -10631,8 +10634,14 @@ c_finish_omp_clauses (tree clauses) case PLUS_EXPR: case MULT_EXPR: case MINUS_EXPR: + break; case MIN_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_name = "min"; + break; case MAX_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_name = "max"; break; case BIT_AND_EXPR: r_name = "&"; @@ -10644,10 +10653,12 @@ c_finish_omp_clauses (tree clauses) r_name = "|"; break; case TRUTH_ANDIF_EXPR: - r_name = "&&"; + if (FLOAT_TYPE_P (TREE_TYPE (t))) + r_name = "&&"; break; case TRUTH_ORIF_EXPR: - r_name = "||"; + if (FLOAT_TYPE_P (TREE_TYPE (t))) + r_name = "||"; break; default: gcc_unreachable (); diff --git a/gcc-4_8-branch/gcc/cfgcleanup.c b/gcc-4_8-branch/gcc/cfgcleanup.c index 8a120bf90a6..3f930b836c3 100644 --- a/gcc-4_8-branch/gcc/cfgcleanup.c +++ b/gcc-4_8-branch/gcc/cfgcleanup.c @@ -1293,7 +1293,6 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, { rtx i1, i2, last1, last2, afterlast1, afterlast2; int ninsns = 0; - rtx p1; enum replace_direction dir, last_dir, afterlast_dir; bool follow_fallthru, did_fallthru; @@ -1321,8 +1320,9 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, || (returnjump_p (i2) && !side_effects_p (PATTERN (i2)))) { last2 = i2; - /* Count everything except for unconditional jump as insn. */ - if (!simplejump_p (i2) && !returnjump_p (i2) && last1) + /* Count everything except for unconditional jump as insn. + Don't count any jumps if dir_p is NULL. */ + if (!simplejump_p (i2) && !returnjump_p (i2) && last1 && dir_p) ninsns++; i2 = PREV_INSN (i2); } @@ -1373,8 +1373,8 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, last1 = i1, last2 = i2; afterlast_dir = last_dir; last_dir = dir; - p1 = PATTERN (i1); - if (!(GET_CODE (p1) == USE || GET_CODE (p1) == CLOBBER)) + if (GET_CODE (PATTERN (i1)) != USE + && GET_CODE (PATTERN (i1)) != CLOBBER) ninsns++; } @@ -1420,7 +1420,8 @@ flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2, /* Like flow_find_cross_jump, except start looking for a matching sequence from the head of the two blocks. Do not include jumps at the end. If STOP_AFTER is nonzero, stop after finding that many matching - instructions. */ + instructions. If STOP_AFTER is zero, count all INSN_P insns, if it is + non-zero, only count active insns. */ int flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, @@ -1492,7 +1493,10 @@ flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, beforelast1 = last1, beforelast2 = last2; last1 = i1, last2 = i2; - ninsns++; + if (!stop_after + || (GET_CODE (PATTERN (i1)) != USE + && GET_CODE (PATTERN (i1)) != CLOBBER)) + ninsns++; } if (i1 == BB_END (bb1) || i2 == BB_END (bb2) diff --git a/gcc-4_8-branch/gcc/cfgexpand.c b/gcc-4_8-branch/gcc/cfgexpand.c index 5cc9c34f568..1321c214d92 100644 --- a/gcc-4_8-branch/gcc/cfgexpand.c +++ b/gcc-4_8-branch/gcc/cfgexpand.c @@ -331,7 +331,7 @@ stack_var_conflict_p (size_t x, size_t y) enter its partition number into bitmap DATA. */ static bool -visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +visit_op (gimple, tree op, tree, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); @@ -351,7 +351,7 @@ visit_op (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) from bitmap DATA. */ static bool -visit_conflict (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +visit_conflict (gimple, tree op, tree, void *data) { bitmap active = (bitmap)data; op = get_base_address (op); @@ -385,7 +385,7 @@ add_scope_conflicts_1 (basic_block bb, bitmap work, bool for_conflict) edge e; edge_iterator ei; gimple_stmt_iterator gsi; - bool (*visit)(gimple, tree, void *); + walk_stmt_load_store_addr_fn visit; bitmap_clear (work); FOR_EACH_EDGE (e, ei, bb->preds) diff --git a/gcc-4_8-branch/gcc/cgraphbuild.c b/gcc-4_8-branch/gcc/cgraphbuild.c index a74a4c043e3..8869f524db5 100644 --- a/gcc-4_8-branch/gcc/cgraphbuild.c +++ b/gcc-4_8-branch/gcc/cgraphbuild.c @@ -218,7 +218,7 @@ compute_call_stmt_bb_frequency (tree decl, basic_block bb) /* Mark address taken in STMT. */ static bool -mark_address (gimple stmt, tree addr, void *data) +mark_address (gimple stmt, tree addr, tree, void *data) { addr = get_base_address (addr); if (TREE_CODE (addr) == FUNCTION_DECL) @@ -245,7 +245,7 @@ mark_address (gimple stmt, tree addr, void *data) /* Mark load of T. */ static bool -mark_load (gimple stmt, tree t, void *data) +mark_load (gimple stmt, tree t, tree, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == FUNCTION_DECL) @@ -273,7 +273,7 @@ mark_load (gimple stmt, tree t, void *data) /* Mark store of T. */ static bool -mark_store (gimple stmt, tree t, void *data) +mark_store (gimple stmt, tree t, tree, void *data) { t = get_base_address (t); if (t && TREE_CODE (t) == VAR_DECL diff --git a/gcc-4_8-branch/gcc/config/aarch64/aarch64.c b/gcc-4_8-branch/gcc/config/aarch64/aarch64.c index 55b2d7d6b73..0e0203f8250 100644 --- a/gcc-4_8-branch/gcc/config/aarch64/aarch64.c +++ b/gcc-4_8-branch/gcc/config/aarch64/aarch64.c @@ -2437,7 +2437,7 @@ aarch64_build_constant (int regnum, HOST_WIDE_INT val) if (ncount < zcount) { emit_move_insn (gen_rtx_REG (Pmode, regnum), - GEN_INT ((~val) & 0xffff)); + GEN_INT (val | ~(HOST_WIDE_INT) 0xffff)); tval = 0xffff; } else diff --git a/gcc-4_8-branch/gcc/config/arm/arm-ldmstm.ml b/gcc-4_8-branch/gcc/config/arm/arm-ldmstm.ml index e615437b125..682aa2c8ee3 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm-ldmstm.ml +++ b/gcc-4_8-branch/gcc/config/arm/arm-ldmstm.ml @@ -67,10 +67,13 @@ let destreg nregs first op_type thumb = Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") (nregs + 1) (inout_constr op_type) (constr thumb) +let reg_predicate thumb = + if thumb then "low_register_operand" else "arm_hard_general_register_operand" + let write_ldm_set thumb nregs offset opnr first = let indent = " " in Printf.printf "%s" (if first then " [" else indent); - Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; + Printf.printf "(set (match_operand:SI %d \"%s\" \"\")\n" opnr (reg_predicate thumb); Printf.printf "%s (mem:SI " indent; begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); @@ -84,7 +87,7 @@ let write_stm_set thumb nregs offset opnr first = begin if offset != 0 then Printf.printf "(plus:SI " end; Printf.printf "%s" (destreg nregs first IN thumb); begin if offset != 0 then Printf.printf " (const_int %d))" offset end; - Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr + Printf.printf ")\n%s (match_operand:SI %d \"%s\" \"\"))" indent opnr (reg_predicate thumb) let write_ldm_peep_set extra_indent nregs opnr first = let indent = " " ^ extra_indent in diff --git a/gcc-4_8-branch/gcc/config/arm/arm.c b/gcc-4_8-branch/gcc/config/arm/arm.c index f80d43a4e43..e90df15400a 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.c +++ b/gcc-4_8-branch/gcc/config/arm/arm.c @@ -22075,7 +22075,11 @@ arm_expand_neon_args (rtx target, int icode, int have_retval, type_mode); } - op[argc] = expand_normal (arg[argc]); + /* Use EXPAND_MEMORY for NEON_ARG_MEMORY to ensure a MEM_P + be returned. */ + op[argc] = expand_expr (arg[argc], NULL_RTX, VOIDmode, + (thisarg == NEON_ARG_MEMORY + ? EXPAND_MEMORY : EXPAND_NORMAL)); switch (thisarg) { @@ -22094,6 +22098,9 @@ arm_expand_neon_args (rtx target, int icode, int have_retval, break; case NEON_ARG_MEMORY: + /* Check if expand failed. */ + if (op[argc] == const0_rtx) + return 0; gcc_assert (MEM_P (op[argc])); PUT_MODE (op[argc], mode[argc]); /* ??? arm_neon.h uses the same built-in functions for signed diff --git a/gcc-4_8-branch/gcc/config/arm/arm.md b/gcc-4_8-branch/gcc/config/arm/arm.md index fa787ef55b7..102e4e375c6 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.md +++ b/gcc-4_8-branch/gcc/config/arm/arm.md @@ -12209,7 +12209,7 @@ [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) (match_operand:SI 2 "const_int_operand" "I"))) - (set (match_operand:DF 3 "arm_hard_register_operand" "") + (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "* @@ -12443,7 +12443,9 @@ (match_operand:SI 1 "" "") (match_operand:SI 2 "" ""))] "TARGET_32BIT && arm_arch5e" - "pld\\t%a0") + "pld\\t%a0" + [(set_attr "type" "load1")] +) ;; General predication pattern diff --git a/gcc-4_8-branch/gcc/config/arm/ldmstm.md b/gcc-4_8-branch/gcc/config/arm/ldmstm.md index ad137d492e4..6e3c5d15a04 100644 --- a/gcc-4_8-branch/gcc/config/arm/ldmstm.md +++ b/gcc-4_8-branch/gcc/config/arm/ldmstm.md @@ -23,15 +23,15 @@ (define_insn "*ldm4_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -42,15 +42,15 @@ (define_insn "*thumb_ldm4_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 5 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" @@ -61,15 +61,15 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" @@ -82,15 +82,15 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 5))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "low_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" @@ -100,13 +100,13 @@ (define_insn "*stm4_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 5 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -118,13 +118,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -136,29 +136,29 @@ [(set (match_operand:SI 5 "s_register_operand" "+&l") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (match_dup 5)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "stm%(ia%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4")]) (define_insn "*ldm4_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" @@ -170,16 +170,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 12)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int 16))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" @@ -190,13 +190,13 @@ (define_insn "*stm4_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -207,13 +207,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int 16))) (set (mem:SI (plus:SI (match_dup 5) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int 16))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(ib%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -221,16 +221,16 @@ (define_insn "*ldm4_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%5, {%1, %2, %3, %4}" @@ -241,16 +241,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (match_dup 5)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "ldm%(da%)\t%5!, {%1, %2, %3, %4}" @@ -260,13 +260,13 @@ (define_insn "*stm4_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -277,13 +277,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 5)) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "stm%(da%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -291,16 +291,16 @@ (define_insn "*ldm4_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -313,16 +313,16 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -16)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -12)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -8)))) - (set (match_operand:SI 4 "arm_hard_register_operand" "") + (set (match_operand:SI 4 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 5) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" @@ -334,13 +334,13 @@ (define_insn "*stm4_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 5 "s_register_operand" "rk") (const_int -16))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -352,13 +352,13 @@ [(set (match_operand:SI 5 "s_register_operand" "+&rk") (plus:SI (match_dup 5) (const_int -16))) (set (mem:SI (plus:SI (match_dup 5) (const_int -16))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -12))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -8))) - (match_operand:SI 3 "arm_hard_register_operand" "")) + (match_operand:SI 3 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 5) (const_int -4))) - (match_operand:SI 4 "arm_hard_register_operand" ""))])] + (match_operand:SI 4 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stm%(db%)\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store4") @@ -474,12 +474,12 @@ (define_insn "*ldm3_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -490,12 +490,12 @@ (define_insn "*thumb_ldm3_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 4 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" @@ -506,12 +506,12 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -524,12 +524,12 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 4))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "low_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" @@ -539,11 +539,11 @@ (define_insn "*stm3_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 4 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -555,11 +555,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -571,24 +571,24 @@ [(set (match_operand:SI 4 "s_register_operand" "+&l") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (match_dup 4)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" "stm%(ia%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3")]) (define_insn "*ldm3_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" @@ -600,13 +600,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" @@ -617,11 +617,11 @@ (define_insn "*stm3_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -632,11 +632,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int 12))) (set (mem:SI (plus:SI (match_dup 4) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int 12))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(ib%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -644,13 +644,13 @@ (define_insn "*ldm3_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%4, {%1, %2, %3}" @@ -661,13 +661,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (match_dup 4)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%(da%)\t%4!, {%1, %2, %3}" @@ -677,11 +677,11 @@ (define_insn "*stm3_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -692,11 +692,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 4)) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "stm%(da%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -704,13 +704,13 @@ (define_insn "*ldm3_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -723,13 +723,13 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -12)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -8)))) - (set (match_operand:SI 3 "arm_hard_register_operand" "") + (set (match_operand:SI 3 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 4) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" @@ -741,11 +741,11 @@ (define_insn "*stm3_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 4 "s_register_operand" "rk") (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%4, {%1, %2, %3}" [(set_attr "type" "store3") @@ -757,11 +757,11 @@ [(set (match_operand:SI 4 "s_register_operand" "+&rk") (plus:SI (match_dup 4) (const_int -12))) (set (mem:SI (plus:SI (match_dup 4) (const_int -12))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -8))) - (match_operand:SI 2 "arm_hard_register_operand" "")) + (match_operand:SI 2 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 4) (const_int -4))) - (match_operand:SI 3 "arm_hard_register_operand" ""))])] + (match_operand:SI 3 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%(db%)\t%4!, {%1, %2, %3}" [(set_attr "type" "store3") @@ -863,9 +863,9 @@ (define_insn "*ldm2_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "rk"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" @@ -876,9 +876,9 @@ (define_insn "*thumb_ldm2_ia" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_operand:SI 3 "s_register_operand" "l"))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" @@ -889,9 +889,9 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -904,9 +904,9 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "low_register_operand" "") (mem:SI (match_dup 3))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "low_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4))))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" @@ -916,9 +916,9 @@ (define_insn "*stm2_ia" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (match_operand:SI 3 "s_register_operand" "rk")) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(ia%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -930,9 +930,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -944,19 +944,19 @@ [(set (match_operand:SI 3 "s_register_operand" "+&l") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (match_dup 3)) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "low_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "low_register_operand" ""))])] "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" "stm%(ia%)\t%3!, {%1, %2}" [(set_attr "type" "store2")]) (define_insn "*ldm2_ib" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" @@ -968,10 +968,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" @@ -982,9 +982,9 @@ (define_insn "*stm2_ib" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(ib%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -995,9 +995,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int 8))) (set (mem:SI (plus:SI (match_dup 3) (const_int 4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int 8))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(ib%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -1005,10 +1005,10 @@ (define_insn "*ldm2_da" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "ldm%(da%)\t%3, {%1, %2}" @@ -1019,10 +1019,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (match_dup 3)))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%(da%)\t%3!, {%1, %2}" @@ -1032,9 +1032,9 @@ (define_insn "*stm2_da" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "stm%(da%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -1045,9 +1045,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (match_dup 3)) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "stm%(da%)\t%3!, {%1, %2}" [(set_attr "type" "store2") @@ -1055,10 +1055,10 @@ (define_insn "*ldm2_db" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "arm_hard_register_operand" "") + [(set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" @@ -1071,10 +1071,10 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) - (set (match_operand:SI 1 "arm_hard_register_operand" "") + (set (match_operand:SI 1 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -8)))) - (set (match_operand:SI 2 "arm_hard_register_operand" "") + (set (match_operand:SI 2 "arm_hard_general_register_operand" "") (mem:SI (plus:SI (match_dup 3) (const_int -4))))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" @@ -1086,9 +1086,9 @@ (define_insn "*stm2_db" [(match_parallel 0 "store_multiple_operation" [(set (mem:SI (plus:SI (match_operand:SI 3 "s_register_operand" "rk") (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%(db%)\t%3, {%1, %2}" [(set_attr "type" "store2") @@ -1100,9 +1100,9 @@ [(set (match_operand:SI 3 "s_register_operand" "+&rk") (plus:SI (match_dup 3) (const_int -8))) (set (mem:SI (plus:SI (match_dup 3) (const_int -8))) - (match_operand:SI 1 "arm_hard_register_operand" "")) + (match_operand:SI 1 "arm_hard_general_register_operand" "")) (set (mem:SI (plus:SI (match_dup 3) (const_int -4))) - (match_operand:SI 2 "arm_hard_register_operand" ""))])] + (match_operand:SI 2 "arm_hard_general_register_operand" ""))])] "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%(db%)\t%3!, {%1, %2}" [(set_attr "type" "store2") diff --git a/gcc-4_8-branch/gcc/config/arm/predicates.md b/gcc-4_8-branch/gcc/config/arm/predicates.md index de71c6dc9c3..bedbf441e4e 100644 --- a/gcc-4_8-branch/gcc/config/arm/predicates.md +++ b/gcc-4_8-branch/gcc/config/arm/predicates.md @@ -53,11 +53,11 @@ (ior (match_operand 0 "imm_for_neon_logic_operand") (match_operand 0 "s_register_operand"))) -;; Any hard register. -(define_predicate "arm_hard_register_operand" +;; Any general register. +(define_predicate "arm_hard_general_register_operand" (match_code "reg") { - return REGNO (op) < FIRST_PSEUDO_REGISTER; + return REGNO (op) <= LAST_ARM_REGNUM; }) ;; A low register. @@ -98,6 +98,12 @@ && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); }) +(define_predicate "vfp_hard_register_operand" + (match_code "reg") +{ + return (IS_VFP_REGNUM (REGNO (op))); +}) + (define_predicate "zero_operand" (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST0_RTX (mode)"))) diff --git a/gcc-4_8-branch/gcc/config/cris/cris.md b/gcc-4_8-branch/gcc/config/cris/cris.md index 8a7f0bfdd70..b3e9f0494b8 100644 --- a/gcc-4_8-branch/gcc/config/cris/cris.md +++ b/gcc-4_8-branch/gcc/config/cris/cris.md @@ -758,7 +758,7 @@ (match_operand:SI 1 "const_int_operand" "")) (match_operand:SI 2 "register_operand" ""))]) (match_operand 3 "register_operand" "")) - (set (match_operand:SI 4 "register_operand" "") + (set (match_operand:SI 4 "cris_nonsp_register_operand" "") (plus:SI (mult:SI (match_dup 0) (match_dup 1)) (match_dup 2)))])] @@ -859,7 +859,7 @@ (match_operand:SI 0 "cris_bdap_operand" "") (match_operand:SI 1 "cris_bdap_operand" ""))]) (match_operand 2 "register_operand" "")) - (set (match_operand:SI 3 "register_operand" "") + (set (match_operand:SI 3 "cris_nonsp_register_operand" "") (plus:SI (match_dup 0) (match_dup 1)))])] "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" [(set (match_dup 4) (match_dup 2)) @@ -3960,7 +3960,7 @@ ;; up. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_operand_extend_operator" [(match_operand 1 "register_operand" "") @@ -3990,7 +3990,7 @@ ;; Call this op-extend-split-rx=rz (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operand 1 "register_operand" "") @@ -4018,7 +4018,7 @@ ;; Call this op-extend-split-swapped (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator @@ -4044,7 +4044,7 @@ ;; bound. Call this op-extend-split-swapped-rx=rz. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_plus_or_bound_operator" [(match_operator @@ -4075,7 +4075,7 @@ ;; Call this op-extend. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 1 "register_operand" "") @@ -4099,7 +4099,7 @@ ;; Call this op-split-rx=rz (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 2 "memory_operand" "") @@ -4123,7 +4123,7 @@ ;; Call this op-split-swapped. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_commutative_orth_op" [(match_operand 1 "register_operand" "") @@ -4146,7 +4146,7 @@ ;; Call this op-split-swapped-rx=rz. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 3 "cris_orthogonal_operator" [(match_operand 2 "memory_operand" "") @@ -4555,10 +4555,11 @@ ;; We're not allowed to generate copies of registers with different mode ;; until after reload; copying pseudos upsets reload. CVS as of ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in -;; cselib_invalidate_regno. +;; cselib_invalidate_regno. Also, don't do this for the stack-pointer, +;; as we don't want it set temporarily to an invalid value. (define_split ; indir_to_reg_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operand 1 "indirect_operand" ""))] "reload_completed && REG_P (operands[0]) @@ -4574,7 +4575,7 @@ ;; As the above, but MOVS and MOVU. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "cris_nonsp_register_operand" "") (match_operator 4 "cris_extend_operator" [(match_operand 1 "indirect_operand" "")]))] diff --git a/gcc-4_8-branch/gcc/config/cris/predicates.md b/gcc-4_8-branch/gcc/config/cris/predicates.md index 040482ba9d1..2acd02f8ad9 100644 --- a/gcc-4_8-branch/gcc/config/cris/predicates.md +++ b/gcc-4_8-branch/gcc/config/cris/predicates.md @@ -76,6 +76,10 @@ (match_test "cris_simple_address_operand (XEXP (op, 0), Pmode)")))) +(define_predicate "cris_nonsp_register_operand" + (and (match_operand 0 "register_operand") + (match_test "op != stack_pointer_rtx"))) + ;; The caller needs to use :SI. (define_predicate "cris_bdap_sign_extend_operand" ; Disabled until diff --git a/gcc-4_8-branch/gcc/config/i386/f16cintrin.h b/gcc-4_8-branch/gcc/config/i386/f16cintrin.h index 88903c16231..4a29fccffe7 100644 --- a/gcc-4_8-branch/gcc/config/i386/f16cintrin.h +++ b/gcc-4_8-branch/gcc/config/i386/f16cintrin.h @@ -35,7 +35,7 @@ extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _cvtsh_ss (unsigned short __S) { - __v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 }; + __v8hi __H = __extension__ (__v8hi){ (short) __S, 0, 0, 0, 0, 0, 0, 0 }; __v4sf __A = __builtin_ia32_vcvtph2ps (__H); return __builtin_ia32_vec_ext_v4sf (__A, 0); } diff --git a/gcc-4_8-branch/gcc/config/i386/i386.c b/gcc-4_8-branch/gcc/config/i386/i386.c index d28ac86b9c9..b07e22530d9 100644 --- a/gcc-4_8-branch/gcc/config/i386/i386.c +++ b/gcc-4_8-branch/gcc/config/i386/i386.c @@ -1378,7 +1378,7 @@ struct processor_costs nocona_cost = { 8, /* MMX or SSE register to integer */ 8, /* size of l1 cache. */ 1024, /* size of l2 cache. */ - 128, /* size of prefetch block */ + 64, /* size of prefetch block */ 8, /* number of parallel prefetches */ 1, /* Branch cost */ COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ @@ -2409,6 +2409,7 @@ static tree ix86_veclibabi_acml (enum built_in_function, tree, tree); /* Processor target table, indexed by processor number */ struct ptt { + const char *const name; /* processor name */ const struct processor_costs *cost; /* Processor costs */ const int align_loop; /* Default alignments. */ const int align_loop_max_skip; @@ -2417,66 +2418,31 @@ struct ptt const int align_func; }; +/* This table must be in sync with enum processor_type in i386.h. */ static const struct ptt processor_target_table[PROCESSOR_max] = { - {&i386_cost, 4, 3, 4, 3, 4}, - {&i486_cost, 16, 15, 16, 15, 16}, - {&pentium_cost, 16, 7, 16, 7, 16}, - {&pentiumpro_cost, 16, 15, 16, 10, 16}, - {&geode_cost, 0, 0, 0, 0, 0}, - {&k6_cost, 32, 7, 32, 7, 32}, - {&athlon_cost, 16, 7, 16, 7, 16}, - {&pentium4_cost, 0, 0, 0, 0, 0}, - {&k8_cost, 16, 7, 16, 7, 16}, - {&nocona_cost, 0, 0, 0, 0, 0}, - /* Core 2 */ - {&core_cost, 16, 10, 16, 10, 16}, - /* Core i7 */ - {&core_cost, 16, 10, 16, 10, 16}, - /* Core avx2 */ - {&core_cost, 16, 10, 16, 10, 16}, - {&generic32_cost, 16, 7, 16, 7, 16}, - {&generic64_cost, 16, 10, 16, 10, 16}, - {&amdfam10_cost, 32, 24, 32, 7, 32}, - {&bdver1_cost, 16, 10, 16, 7, 11}, - {&bdver2_cost, 16, 10, 16, 7, 11}, - {&bdver3_cost, 16, 10, 16, 7, 11}, - {&btver1_cost, 16, 10, 16, 7, 11}, - {&btver2_cost, 16, 10, 16, 7, 11}, - {&atom_cost, 16, 15, 16, 7, 16} -}; - -static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = -{ - "generic", - "i386", - "i486", - "pentium", - "pentium-mmx", - "pentiumpro", - "pentium2", - "pentium3", - "pentium4", - "pentium-m", - "prescott", - "nocona", - "core2", - "corei7", - "core-avx2", - "atom", - "geode", - "k6", - "k6-2", - "k6-3", - "athlon", - "athlon-4", - "k8", - "amdfam10", - "bdver1", - "bdver2", - "bdver3", - "btver1", - "btver2" + {"generic", &generic32_cost, 16, 7, 16, 7, 16}, + {"generic", &generic64_cost, 16, 10, 16, 10, 16}, + {"i386", &i386_cost, 4, 3, 4, 3, 4}, + {"i486", &i486_cost, 16, 15, 16, 15, 16}, + {"pentium", &pentium_cost, 16, 7, 16, 7, 16}, + {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16}, + {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0}, + {"nocona", &nocona_cost, 0, 0, 0, 0, 0}, + {"core2", &core_cost, 16, 10, 16, 10, 16}, + {"corei7", &core_cost, 16, 10, 16, 10, 16}, + {"core-avx2", &core_cost, 16, 10, 16, 10, 16}, + {"atom", &atom_cost, 16, 15, 16, 7, 16}, + {"geode", &geode_cost, 0, 0, 0, 0, 0}, + {"k6", &k6_cost, 32, 7, 32, 7, 32}, + {"athlon", &athlon_cost, 16, 7, 16, 7, 16}, + {"k8", &k8_cost, 16, 7, 16, 7, 16}, + {"amdfam10", &amdfam10_cost, 32, 24, 32, 7, 32}, + {"bdver1", &bdver1_cost, 16, 10, 16, 7, 11}, + {"bdver2", &bdver2_cost, 16, 10, 16, 7, 11}, + {"bdver3", &bdver3_cost, 16, 10, 16, 7, 11}, + {"btver1", &btver1_cost, 16, 10, 16, 7, 11}, + {"btver2", &btver2_cost, 16, 10, 16, 7, 11} }; static bool @@ -3125,7 +3091,8 @@ ix86_option_override_internal (bool main_args_p) ix86_tune_string = ix86_arch_string; if (!ix86_tune_string) { - ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT]; + ix86_tune_string + = processor_target_table[TARGET_CPU_DEFAULT].name; ix86_tune_defaulted = 1; } @@ -4078,19 +4045,15 @@ ix86_function_specific_print (FILE *file, int indent, = ix86_target_string (ptr->x_ix86_isa_flags, ptr->x_target_flags, NULL, NULL, ptr->x_ix86_fpmath, false); + gcc_assert (ptr->arch < PROCESSOR_max); fprintf (file, "%*sarch = %d (%s)\n", indent, "", - ptr->arch, - ((ptr->arch < TARGET_CPU_DEFAULT_max) - ? cpu_names[ptr->arch] - : "")); + ptr->arch, processor_target_table[ptr->arch].name); + gcc_assert (ptr->tune < PROCESSOR_max); fprintf (file, "%*stune = %d (%s)\n", indent, "", - ptr->tune, - ((ptr->tune < TARGET_CPU_DEFAULT_max) - ? cpu_names[ptr->tune] - : "")); + ptr->tune, processor_target_table[ptr->tune].name); fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost); @@ -5801,10 +5764,14 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ The midde-end can't deal with the vector types > 16 bytes. In this case, we return the original mode and warn ABI change if CUM isn't - NULL. */ + NULL. + + If INT_RETURN is true, warn ABI change if the vector mode isn't + available for function return value. */ static enum machine_mode -type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) +type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum, + bool in_return) { enum machine_mode mode = TYPE_MODE (type); @@ -5830,6 +5797,7 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) if (size == 32 && !TARGET_AVX) { static bool warnedavx; + static bool warnedavx_ret; if (cum && !warnedavx @@ -5839,12 +5807,20 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) warning (0, "AVX vector argument without AVX " "enabled changes the ABI"); } + else if (in_return & !warnedavx_ret) + { + warnedavx_ret = true; + warning (0, "AVX vector return without AVX " + "enabled changes the ABI"); + } + return TYPE_MODE (type); } else if (((size == 8 && TARGET_64BIT) || size == 16) && !TARGET_SSE) { static bool warnedsse; + static bool warnedsse_ret; if (cum && !warnedsse @@ -5854,10 +5830,19 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) warning (0, "SSE vector argument without SSE " "enabled changes the ABI"); } + else if (!TARGET_64BIT + && in_return + & !warnedsse_ret) + { + warnedsse_ret = true; + warning (0, "SSE vector return without SSE " + "enabled changes the ABI"); + } } else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX) { static bool warnedmmx; + static bool warnedmmx_ret; if (cum && !warnedmmx @@ -5867,6 +5852,12 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum) warning (0, "MMX vector argument without MMX " "enabled changes the ABI"); } + else if (in_return & !warnedmmx_ret) + { + warnedmmx_ret = true; + warning (0, "MMX vector return without MMX " + "enabled changes the ABI"); + } } return mode; } @@ -6748,7 +6739,7 @@ ix86_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (type) - mode = type_natural_mode (type, NULL); + mode = type_natural_mode (type, NULL, false); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) function_arg_advance_ms_64 (cum, bytes, words); @@ -6776,8 +6767,6 @@ function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, enum machine_mode orig_mode, const_tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words) { - static bool warnedsse, warnedmmx; - /* Avoid the AL settings for the Unix64 ABI. */ if (mode == VOIDmode) return constm1_rtx; @@ -6834,12 +6823,6 @@ function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, case V2DFmode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_SSE && !warnedsse && cum->warn_sse) - { - warnedsse = true; - warning (0, "SSE vector argument without SSE enabled " - "changes the ABI"); - } if (cum->sse_nregs) return gen_reg_or_parallel (mode, orig_mode, cum->sse_regno + FIRST_SSE_REG); @@ -6872,12 +6855,6 @@ function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode, case V1DImode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_MMX && !warnedmmx && cum->warn_mmx) - { - warnedmmx = true; - warning (0, "MMX vector argument without MMX enabled " - "changes the ABI"); - } if (cum->mmx_nregs) return gen_reg_or_parallel (mode, orig_mode, cum->mmx_regno + FIRST_MMX_REG); @@ -7000,7 +6977,7 @@ ix86_function_arg (cumulative_args_t cum_v, enum machine_mode omode, /* To simplify the code below, represent vector types with a vector mode even if MMX/SSE are not active. */ if (type && TREE_CODE (type) == VECTOR_TYPE) - mode = type_natural_mode (type, cum); + mode = type_natural_mode (type, cum, false); if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) arg = function_arg_ms_64 (cum, mode, omode, named, bytes); @@ -7451,7 +7428,7 @@ ix86_function_value (const_tree valtype, const_tree fntype_or_decl, enum machine_mode mode, orig_mode; orig_mode = TYPE_MODE (valtype); - mode = type_natural_mode (valtype, NULL); + mode = type_natural_mode (valtype, NULL, true); return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode); } @@ -7566,7 +7543,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) #ifdef SUBTARGET_RETURN_IN_MEMORY return SUBTARGET_RETURN_IN_MEMORY (type, fntype); #else - const enum machine_mode mode = type_natural_mode (type, NULL); + const enum machine_mode mode = type_natural_mode (type, NULL, true); if (TARGET_64BIT) { @@ -7580,52 +7557,6 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) #endif } -/* When returning SSE vector types, we have a choice of either - (1) being abi incompatible with a -march switch, or - (2) generating an error. - Given no good solution, I think the safest thing is one warning. - The user won't be able to use -Werror, but.... - - Choose the STRUCT_VALUE_RTX hook because that's (at present) only - called in response to actually generating a caller or callee that - uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called - via aggregate_value_p for general type probing from tree-ssa. */ - -static rtx -ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED) -{ - static bool warnedsse, warnedmmx; - - if (!TARGET_64BIT && type) - { - /* Look at the return type of the function, not the function type. */ - enum machine_mode mode = TYPE_MODE (TREE_TYPE (type)); - - if (!TARGET_SSE && !warnedsse) - { - if (mode == TImode - || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16)) - { - warnedsse = true; - warning (0, "SSE vector return without SSE enabled " - "changes the ABI"); - } - } - - if (!TARGET_MMX && !warnedmmx) - { - if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8) - { - warnedmmx = true; - warning (0, "MMX vector return without MMX enabled " - "changes the ABI"); - } - } - } - - return NULL; -} - /* Create the va_list data type. */ @@ -8050,7 +7981,7 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, size = int_size_in_bytes (type); rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - nat_mode = type_natural_mode (type, NULL); + nat_mode = type_natural_mode (type, NULL, false); switch (nat_mode) { case V8SFmode: @@ -17380,8 +17311,18 @@ ix86_avoid_lea_for_addr (rtx insn, rtx operands[]) if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun)) return false; - /* Check it is correct to split here. */ - if (!ix86_ok_to_clobber_flags(insn)) + /* The "at least two components" test below might not catch simple + move or zero extension insns if parts.base is non-NULL and parts.disp + is const0_rtx as the only components in the address, e.g. if the + register is %rbp or %r13. As this test is much cheaper and moves or + zero extensions are the common case, do this check first. */ + if (REG_P (operands[1]) + || (SImode_address_operand (operands[1], VOIDmode) + && REG_P (XEXP (operands[1], 0)))) + return false; + + /* Check if it is OK to split here. */ + if (!ix86_ok_to_clobber_flags (insn)) return false; ok = ix86_decompose_address (operands[1], &parts); @@ -25028,7 +24969,8 @@ ix86_constant_alignment (tree exp, int align) int ix86_data_alignment (tree type, int align) { - int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT); + int max_align + = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT); if (AGGREGATE_TYPE_P (type) && TYPE_SIZE (type) @@ -32298,7 +32240,9 @@ addcarryx: mode4 = insn_data[icode].operand[5].mode; if (target == NULL_RTX - || GET_MODE (target) != insn_data[icode].operand[0].mode) + || GET_MODE (target) != insn_data[icode].operand[0].mode + || !insn_data[icode].operand[0].predicate (target, + GET_MODE (target))) subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); else subtarget = target; @@ -33969,10 +33913,10 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) { /* We implement the move patterns for all vector modes into and out of SSE registers, even when no operation instructions - are available. OImode move is available only when AVX is - enabled. */ - return ((TARGET_AVX && mode == OImode) - || VALID_AVX256_REG_MODE (mode) + are available. OImode and AVX modes are available only when + AVX is enabled. */ + return ((TARGET_AVX + && VALID_AVX256_REG_OR_OI_MODE (mode)) || VALID_SSE_REG_MODE (mode) || VALID_SSE2_REG_MODE (mode) || VALID_MMX_REG_MODE (mode) @@ -42569,8 +42513,6 @@ ix86_memmodel_check (unsigned HOST_WIDE_INT val) #undef TARGET_PROMOTE_PROTOTYPES #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true -#undef TARGET_STRUCT_VALUE_RTX -#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs #undef TARGET_MUST_PASS_IN_STACK diff --git a/gcc-4_8-branch/gcc/config/i386/i386.h b/gcc-4_8-branch/gcc/config/i386/i386.h index a69862c549f..335cf611d79 100644 --- a/gcc-4_8-branch/gcc/config/i386/i386.h +++ b/gcc-4_8-branch/gcc/config/i386/i386.h @@ -197,10 +197,10 @@ extern const struct processor_costs ix86_size_cost; /* Macros used in the machine description to test the flags. */ -/* configure can arrange to make this 2, to force a 486. */ +/* configure can arrange to change it. */ #ifndef TARGET_CPU_DEFAULT -#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic +#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32 #endif #ifndef TARGET_FPMATH_DEFAULT @@ -591,43 +591,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* Target Pragmas. */ #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () -enum target_cpu_default -{ - TARGET_CPU_DEFAULT_generic = 0, - - TARGET_CPU_DEFAULT_i386, - TARGET_CPU_DEFAULT_i486, - TARGET_CPU_DEFAULT_pentium, - TARGET_CPU_DEFAULT_pentium_mmx, - TARGET_CPU_DEFAULT_pentiumpro, - TARGET_CPU_DEFAULT_pentium2, - TARGET_CPU_DEFAULT_pentium3, - TARGET_CPU_DEFAULT_pentium4, - TARGET_CPU_DEFAULT_pentium_m, - TARGET_CPU_DEFAULT_prescott, - TARGET_CPU_DEFAULT_nocona, - TARGET_CPU_DEFAULT_core2, - TARGET_CPU_DEFAULT_corei7, - TARGET_CPU_DEFAULT_haswell, - TARGET_CPU_DEFAULT_atom, - - TARGET_CPU_DEFAULT_geode, - TARGET_CPU_DEFAULT_k6, - TARGET_CPU_DEFAULT_k6_2, - TARGET_CPU_DEFAULT_k6_3, - TARGET_CPU_DEFAULT_athlon, - TARGET_CPU_DEFAULT_athlon_sse, - TARGET_CPU_DEFAULT_k8, - TARGET_CPU_DEFAULT_amdfam10, - TARGET_CPU_DEFAULT_bdver1, - TARGET_CPU_DEFAULT_bdver2, - TARGET_CPU_DEFAULT_bdver3, - TARGET_CPU_DEFAULT_btver1, - TARGET_CPU_DEFAULT_btver2, - - TARGET_CPU_DEFAULT_max -}; - #ifndef CC1_SPEC #define CC1_SPEC "%(cc1_cpu) " #endif @@ -2089,32 +2052,33 @@ do { \ with x86-64 medium memory model */ #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 -/* Which processor to tune code generation for. */ +/* Which processor to tune code generation for. These must be in sync + with processor_target_table in i386.c. */ enum processor_type { - PROCESSOR_I386 = 0, /* 80386 */ + PROCESSOR_GENERIC32 = 0, + PROCESSOR_GENERIC64, + PROCESSOR_I386, /* 80386 */ PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, - PROCESSOR_GEODE, - PROCESSOR_K6, - PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, - PROCESSOR_K8, PROCESSOR_NOCONA, PROCESSOR_CORE2, PROCESSOR_COREI7, PROCESSOR_HASWELL, - PROCESSOR_GENERIC32, - PROCESSOR_GENERIC64, + PROCESSOR_ATOM, + PROCESSOR_GEODE, + PROCESSOR_K6, + PROCESSOR_ATHLON, + PROCESSOR_K8, PROCESSOR_AMDFAM10, PROCESSOR_BDVER1, PROCESSOR_BDVER2, PROCESSOR_BDVER3, PROCESSOR_BTVER1, PROCESSOR_BTVER2, - PROCESSOR_ATOM, PROCESSOR_max }; diff --git a/gcc-4_8-branch/gcc/config/i386/i386.md b/gcc-4_8-branch/gcc/config/i386/i386.md index ebfa0bbccff..5f1921c106c 100644 --- a/gcc-4_8-branch/gcc/config/i386/i386.md +++ b/gcc-4_8-branch/gcc/config/i386/i386.md @@ -2722,7 +2722,20 @@ "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:SF (reg:P SP_REG)) (match_dup 1))] - "operands[2] = GEN_INT (-GET_MODE_SIZE (mode));") +{ + rtx op = XEXP (operands[0], 0); + if (GET_CODE (op) == PRE_DEC) + { + gcc_assert (!TARGET_64BIT); + op = GEN_INT (-4); + } + else + { + op = XEXP (XEXP (op, 1), 1); + gcc_assert (CONST_INT_P (op)); + } + operands[2] = op; +}) (define_split [(set (match_operand:SF 0 "push_operand") @@ -5450,6 +5463,12 @@ mode = SImode; ix86_split_lea_for_addr (curr_insn, operands, mode); + + /* Zero-extend return register to DImode for zero-extended addresses. */ + if (mode != mode) + emit_insn (gen_zero_extendsidi2 + (operands[0], gen_lowpart (mode, operands[0]))); + DONE; } [(set_attr "type" "lea") diff --git a/gcc-4_8-branch/gcc/config/microblaze/microblaze.md b/gcc-4_8-branch/gcc/config/microblaze/microblaze.md index 3618cad524b..25f074876aa 100644 --- a/gcc-4_8-branch/gcc/config/microblaze/microblaze.md +++ b/gcc-4_8-branch/gcc/config/microblaze/microblaze.md @@ -74,7 +74,7 @@ ;; bshift Shift operations (define_attr "type" - "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt" + "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" (const_string "unknown")) ;; Main data type used by the insn @@ -365,7 +365,8 @@ [(set (match_operand:HI 0 "register_operand" "=r") (bswap:HI (match_operand:HI 1 "register_operand" "r")))] "TARGET_REORDER" - "swaph %0, %1" + "swapb %0, %1 + swaph %0, %0" ) ;;---------------------------------------------------------------- @@ -1649,7 +1650,7 @@ ;;---------------------------------------------------------------- (define_insn "cstoresf4" [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator 1 "comparison_operator" + (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:SF 2 "register_operand" "r") (match_operand:SF 3 "register_operand" "r")]))] "TARGET_HARD_FLOAT" @@ -1678,7 +1679,7 @@ (define_expand "cbranchsf4" [(set (pc) - (if_then_else (match_operator 0 "comparison_operator" + (if_then_else (match_operator 0 "ordered_comparison_operator" [(match_operand:SF 1 "register_operand") (match_operand:SF 2 "register_operand")]) (label_ref (match_operand 3 "")) @@ -2201,6 +2202,14 @@ (set_attr "mode" "none") (set_attr "length" "4")]) +;; Trap instruction pattern for __builtin_trap. Same as the glibc ABORT_INSTRUCTION +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "brki\tr0,-1" + [(set_attr "type" "trap")] +) + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference ;; between "mfs" and "addik" instructions. (define_insn "set_got" diff --git a/gcc-4_8-branch/gcc/config/mips/driver-native.c b/gcc-4_8-branch/gcc/config/mips/driver-native.c index 8b7ed5b5530..758efa9a4a6 100644 --- a/gcc-4_8-branch/gcc/config/mips/driver-native.c +++ b/gcc-4_8-branch/gcc/config/mips/driver-native.c @@ -58,11 +58,17 @@ host_detect_local_cpu (int argc, const char **argv) if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0) { if (strstr (buf, "Godson2 V0.2") != NULL - || strstr (buf, "Loongson-2 V0.2") != NULL) + || strstr (buf, "Loongson-2 V0.2") != NULL + || strstr (buf, "Loongson-2E") != NULL) cpu = "loongson2e"; else if (strstr (buf, "Godson2 V0.3") != NULL - || strstr (buf, "Loongson-2 V0.3") != NULL) + || strstr (buf, "Loongson-2 V0.3") != NULL + || strstr (buf, "Loongson-2F") != NULL) cpu = "loongson2f"; + else if (strstr (buf, "Godson3 V0.5") != NULL + || strstr (buf, "Loongson-3 V0.5") != NULL + || strstr (buf, "Loongson-3A") != NULL) + cpu = "loongson3a"; else if (strstr (buf, "SiByte SB1") != NULL) cpu = "sb1"; else if (strstr (buf, "R5000") != NULL) diff --git a/gcc-4_8-branch/gcc/config/mips/mips.c b/gcc-4_8-branch/gcc/config/mips/mips.c index 252e828480e..41c5d6b6b1f 100644 --- a/gcc-4_8-branch/gcc/config/mips/mips.c +++ b/gcc-4_8-branch/gcc/config/mips/mips.c @@ -3560,17 +3560,6 @@ mips_set_reg_reg_cost (enum machine_mode mode) } } -/* Return the cost of an operand X that can be trucated for free. - SPEED says whether we're optimizing for size or speed. */ - -static int -mips_truncated_op_cost (rtx x, bool speed) -{ - if (GET_CODE (x) == TRUNCATE) - x = XEXP (x, 0); - return set_src_cost (x, speed); -} - /* Implement TARGET_RTX_COSTS. */ static bool @@ -3951,13 +3940,12 @@ mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, case ZERO_EXTEND: if (outer_code == SET && ISA_HAS_BADDU + && (GET_CODE (XEXP (x, 0)) == TRUNCATE + || GET_CODE (XEXP (x, 0)) == SUBREG) && GET_MODE (XEXP (x, 0)) == QImode - && GET_CODE (XEXP (x, 0)) == PLUS) + && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) { - rtx plus = XEXP (x, 0); - *total = (COSTS_N_INSNS (1) - + mips_truncated_op_cost (XEXP (plus, 0), speed) - + mips_truncated_op_cost (XEXP (plus, 1), speed)); + *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); return true; } *total = mips_zero_extend_cost (mode, XEXP (x, 0)); @@ -8057,7 +8045,7 @@ mips_print_operand (FILE *file, rtx op, int letter) case 't': { int truth = (code == NE) == (letter == 'T'); - fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); + fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file); } break; diff --git a/gcc-4_8-branch/gcc/config/mips/mips.h b/gcc-4_8-branch/gcc/config/mips/mips.h index 0acce14bd8c..d6e721d30f5 100644 --- a/gcc-4_8-branch/gcc/config/mips/mips.h +++ b/gcc-4_8-branch/gcc/config/mips/mips.h @@ -949,6 +949,11 @@ struct mips_cpu_info { || TARGET_SMARTMIPS) \ && !TARGET_MIPS16) +/* ISA has the WSBH (word swap bytes within halfwords) instruction. + 64-bit targets also provide DSBH and DSHD. */ +#define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \ + && !TARGET_MIPS16) + /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || TARGET_LOONGSON_2EF \ diff --git a/gcc-4_8-branch/gcc/config/mips/mips.md b/gcc-4_8-branch/gcc/config/mips/mips.md index 7aa461dbd69..2a0c695c807 100644 --- a/gcc-4_8-branch/gcc/config/mips/mips.md +++ b/gcc-4_8-branch/gcc/config/mips/mips.md @@ -73,6 +73,11 @@ UNSPEC_STORE_LEFT UNSPEC_STORE_RIGHT + ;; Integer operations that are too cumbersome to describe directly. + UNSPEC_WSBH + UNSPEC_DSBH + UNSPEC_DSHD + ;; Floating-point moves. UNSPEC_LOAD_LOW UNSPEC_LOAD_HIGH @@ -1294,20 +1299,32 @@ ;; Combiner patterns for unsigned byte-add. -(define_insn "*baddu_si" +(define_insn "*baddu_si_eb" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 3)))] + "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" + "baddu\\t%0,%1,%2" + [(set_attr "alu_type" "add")]) + +(define_insn "*baddu_si_el" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI - (plus:QI (match_operand:QI 1 "register_operand" "d") - (match_operand:QI 2 "register_operand" "d"))))] - "ISA_HAS_BADDU" + (subreg:QI + (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) 0)))] + "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) (define_insn "*baddu_di" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR - (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d")) - (truncate:QI (match_operand:DI 2 "register_operand" "d")))))] + (truncate:QI + (plus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) @@ -5367,6 +5384,56 @@ } [(set_attr "type" "shift") (set_attr "mode" "")]) + +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "register_operand" "d")))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn_and_split "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "ISA_HAS_WSBH && ISA_HAS_ROR" + "#" + "" + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) + (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] + "" + [(set_attr "length" "8")]) + +(define_insn_and_split "bswapdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (bswap:DI (match_operand:DI 1 "register_operand" "d")))] + "TARGET_64BIT && ISA_HAS_WSBH" + "#" + "" + [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) + (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] + "" + [(set_attr "length" "8")]) + +(define_insn "wsbh" + [(set (match_operand:SI 0 "register_operand" "=d") + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] + "ISA_HAS_WSBH" + "wsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dsbh" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dsbh\t%0,%1" + [(set_attr "type" "shift")]) + +(define_insn "dshd" + [(set (match_operand:DI 0 "register_operand" "=d") + (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] + "TARGET_64BIT && ISA_HAS_WSBH" + "dshd\t%0,%1" + [(set_attr "type" "shift")]) ;; ;; .................... diff --git a/gcc-4_8-branch/gcc/config/pa/pa.c b/gcc-4_8-branch/gcc/config/pa/pa.c index 87ef8fbbcb7..e9460db9d17 100644 --- a/gcc-4_8-branch/gcc/config/pa/pa.c +++ b/gcc-4_8-branch/gcc/config/pa/pa.c @@ -7539,7 +7539,7 @@ pa_attr_length_millicode_call (rtx insn) if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET) return 8; - if (TARGET_LONG_ABS_CALL && !flag_pic) + if (!flag_pic) return 12; return 24; @@ -8104,7 +8104,8 @@ pa_attr_length_indirect_call (rtx insn) return 12; if (TARGET_FAST_INDIRECT_CALLS - || (!TARGET_PORTABLE_RUNTIME + || (!TARGET_LONG_CALLS + && !TARGET_PORTABLE_RUNTIME && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) || distance < MAX_PCREL17F_OFFSET))) return 8; @@ -10522,13 +10523,13 @@ pa_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) /* When INT14_OK_STRICT is false, a secondary reload is needed to adjust the displacement of SImode and DImode floating point - instructions. So, we return false when STRICT is true. We + instructions but this may fail when the register also needs + reloading. So, we return false when STRICT is true. We also reject long displacements for float mode addresses since the majority of accesses will use floating point instructions that don't support 14-bit offsets. */ if (!INT14_OK_STRICT - && reload_in_progress - && strict + && (strict || !(reload_in_progress || reload_completed)) && mode != QImode && mode != HImode) return false; @@ -10588,8 +10589,7 @@ pa_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) return true; if (!INT14_OK_STRICT - && reload_in_progress - && strict + && (strict || !(reload_in_progress || reload_completed)) && mode != QImode && mode != HImode) return false; diff --git a/gcc-4_8-branch/gcc/config/rs6000/rs6000.c b/gcc-4_8-branch/gcc/config/rs6000/rs6000.c index f8579fd984b..0325870af97 100644 --- a/gcc-4_8-branch/gcc/config/rs6000/rs6000.c +++ b/gcc-4_8-branch/gcc/config/rs6000/rs6000.c @@ -5428,12 +5428,13 @@ rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, break; case TFmode: - case TDmode: - case TImode: if (TARGET_E500_DOUBLE) return (SPE_CONST_OFFSET_OK (offset) && SPE_CONST_OFFSET_OK (offset + 8)); + /* fall through */ + case TDmode: + case TImode: extra = 8; if (!worst_case) break; diff --git a/gcc-4_8-branch/gcc/config/s390/s390.c b/gcc-4_8-branch/gcc/config/s390/s390.c index 2ba1d8a1164..257e33c8469 100644 --- a/gcc-4_8-branch/gcc/config/s390/s390.c +++ b/gcc-4_8-branch/gcc/config/s390/s390.c @@ -3115,15 +3115,22 @@ s390_preferred_reload_class (rtx op, reg_class_t rclass) prefer ADDR_REGS. If 'class' is not a superset of ADDR_REGS, e.g. FP_REGS, reject this reload. */ case CONST: - /* A larl operand with odd addend will get fixed via secondary - reload. So don't request it to be pushed into literal - pool. */ + /* Symrefs cannot be pushed into the literal pool with -fPIC + so we *MUST NOT* return NO_REGS for these cases + (s390_cannot_force_const_mem will return true). + + On the other hand we MUST return NO_REGS for symrefs with + invalid addend which might have been pushed to the literal + pool (no -fPIC). Usually we would expect them to be + handled via secondary reload but this does not happen if + they are used as literal pool slot replacement in reload + inheritance (see emit_input_reload_insns). */ if (TARGET_CPU_ZARCH && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT) { - if (reg_class_subset_p (ADDR_REGS, rclass)) + if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass)) return ADDR_REGS; else return NO_REGS; @@ -9770,16 +9777,9 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, void s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) { - const int CC0 = 1 << 3; - const int CC1 = 1 << 2; - const int CC3 = 1 << 0; - rtx abort_label = gen_label_rtx (); - rtx leave_label = gen_label_rtx (); rtx retry_plus_two = gen_reg_rtx (SImode); rtx retry_reg = gen_reg_rtx (SImode); rtx retry_label = NULL_RTX; - rtx jump; - rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); if (retry != NULL_RTX) { @@ -9796,38 +9796,25 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb)); - jump = s390_emit_jump (abort_label, - gen_rtx_NE (VOIDmode, - gen_rtx_REG (CCRAWmode, CC_REGNUM), - gen_rtx_CONST_INT (VOIDmode, CC0))); - - JUMP_LABEL (jump) = abort_label; - LABEL_NUSES (abort_label) = 1; - add_reg_note (jump, REG_BR_PROB, very_unlikely); - - /* Initialize CC return value. */ - emit_move_insn (dest, const0_rtx); - - s390_emit_jump (leave_label, NULL_RTX); - LABEL_NUSES (leave_label) = 1; - emit_barrier (); - - /* Abort handler code. */ - - emit_label (abort_label); emit_move_insn (dest, gen_rtx_UNSPEC (SImode, gen_rtvec (1, gen_rtx_REG (CCRAWmode, CC_REGNUM)), UNSPEC_CC_TO_INT)); if (retry != NULL_RTX) { + const int CC0 = 1 << 3; + const int CC1 = 1 << 2; + const int CC3 = 1 << 0; + rtx jump; rtx count = gen_reg_rtx (SImode); + rtx leave_label = gen_label_rtx (); + + /* Exit for success and permanent failures. */ jump = s390_emit_jump (leave_label, gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCRAWmode, CC_REGNUM), - gen_rtx_CONST_INT (VOIDmode, CC1 | CC3))); - LABEL_NUSES (leave_label) = 2; - add_reg_note (jump, REG_BR_PROB, very_unlikely); + gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3))); + LABEL_NUSES (leave_label) = 1; /* CC2 - transient failure. Perform retry with ppa. */ emit_move_insn (count, retry_plus_two); @@ -9838,9 +9825,8 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) retry_reg)); JUMP_LABEL (jump) = retry_label; LABEL_NUSES (retry_label) = 1; + emit_label (leave_label); } - - emit_label (leave_label); } /* Builtins. */ diff --git a/gcc-4_8-branch/gcc/config/tilegx/sync.md b/gcc-4_8-branch/gcc/config/tilegx/sync.md index a4bea6b6889..16f18922f64 100644 --- a/gcc-4_8-branch/gcc/config/tilegx/sync.md +++ b/gcc-4_8-branch/gcc/config/tilegx/sync.md @@ -150,15 +150,22 @@ (match_operand:SI 3 "const_int_operand" "")] ;; model "" { + rtx addend; enum memmodel model = (enum memmodel) INTVAL (operands[3]); if (operands[2] != const0_rtx) - emit_move_insn (operands[2], gen_rtx_NEG (mode, operands[2])); + { + addend = gen_reg_rtx (mode); + emit_move_insn (addend, + gen_rtx_MINUS (mode, const0_rtx, operands[2])); + } + else + addend = operands[2]; tilegx_pre_atomic_barrier (model); emit_insn (gen_atomic_fetch_add_bare (operands[0], operands[1], - operands[2])); + addend)); tilegx_post_atomic_barrier (model); DONE; }) diff --git a/gcc-4_8-branch/gcc/config/tilegx/tilegx-c.c b/gcc-4_8-branch/gcc/config/tilegx/tilegx-c.c index 3ecec6e0445..8d19d20f7c9 100644 --- a/gcc-4_8-branch/gcc/config/tilegx/tilegx-c.c +++ b/gcc-4_8-branch/gcc/config/tilegx/tilegx-c.c @@ -47,6 +47,9 @@ tilegx_cpu_cpp_builtins (struct cpp_reader *pfile) if (TARGET_32BIT) builtin_define ("__tilegx32__"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + TILEGX_CPU_CPP_ENDIAN_BUILTINS (); GNU_USER_TARGET_OS_CPP_BUILTINS (); } diff --git a/gcc-4_8-branch/gcc/config/tilegx/tilegx.c b/gcc-4_8-branch/gcc/config/tilegx/tilegx.c index beb1012cf2c..502b953cf85 100644 --- a/gcc-4_8-branch/gcc/config/tilegx/tilegx.c +++ b/gcc-4_8-branch/gcc/config/tilegx/tilegx.c @@ -702,6 +702,16 @@ tilegx_init_expanders (void) } +/* Implement TARGET_EXPAND_TO_RTL_HOOK. */ +static void +tilegx_expand_to_rtl_hook (void) +{ + /* Exclude earlier sets of crtl->uses_pic_offset_table, because we + only care about uses actually emitted. */ + crtl->uses_pic_offset_table = 0; +} + + /* Implement TARGET_SHIFT_TRUNCATION_MASK. DImode shifts use the mode matching insns and therefore guarantee that the shift count is modulo 64. SImode shifts sometimes use the 64 bit version so do @@ -3543,6 +3553,12 @@ tilegx_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) + PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid) @@ -4368,10 +4384,12 @@ tilegx_gen_bundles (void) basic_block bb; FOR_EACH_BB (bb) { - rtx insn, next; + rtx insn, next, prev; rtx end = NEXT_INSN (BB_END (bb)); - for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next) + prev = NULL_RTX; + for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; + prev = insn, insn = next) { next = next_insn_to_bundle (NEXT_INSN (insn), end); @@ -4396,6 +4414,18 @@ tilegx_gen_bundles (void) PUT_MODE (insn, SImode); } } + + /* Delete barrier insns, because they can mess up the + emitting of bundle braces. If it is end-of-bundle, then + the previous insn must be marked end-of-bundle. */ + if (get_attr_type (insn) == TYPE_NOTHING) { + if (GET_MODE (insn) == QImode && prev != NULL + && GET_MODE (prev) == SImode) + { + PUT_MODE (prev, QImode); + } + delete_insn (insn); + } } } } @@ -5498,6 +5528,9 @@ tilegx_file_end (void) #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS tilegx_rtx_costs +#undef TARGET_EXPAND_TO_RTL_HOOK +#define TARGET_EXPAND_TO_RTL_HOOK tilegx_expand_to_rtl_hook + #undef TARGET_SHIFT_TRUNCATION_MASK #define TARGET_SHIFT_TRUNCATION_MASK tilegx_shift_truncation_mask diff --git a/gcc-4_8-branch/gcc/config/tilegx/tilegx.md b/gcc-4_8-branch/gcc/config/tilegx/tilegx.md index 8dfcff603cc..5fe17761999 100644 --- a/gcc-4_8-branch/gcc/config/tilegx/tilegx.md +++ b/gcc-4_8-branch/gcc/config/tilegx/tilegx.md @@ -5076,10 +5076,8 @@ ;; Network intrinsics -;; Note the "pseudo" text is handled specially by the -;; asm_output_opcode routine. If the output is an empty string, the -;; instruction would bypass the asm_output_opcode routine, bypassing -;; the bundle handling code. +;; Note the this barrier is of type "nothing," which is deleted after +;; the final scheduling pass so that nothing is emitted for it. (define_insn "tilegx_network_barrier" [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)] "" diff --git a/gcc-4_8-branch/gcc/config/tilepro/tilepro-c.c b/gcc-4_8-branch/gcc/config/tilepro/tilepro-c.c index 8f7aa00d7ba..b9bf24ab2a0 100644 --- a/gcc-4_8-branch/gcc/config/tilepro/tilepro-c.c +++ b/gcc-4_8-branch/gcc/config/tilepro/tilepro-c.c @@ -44,6 +44,11 @@ tilepro_cpu_cpp_builtins (struct cpp_reader *pfile) builtin_define ("__tile_chip__=1"); builtin_define ("__tile_chip_rev__=0"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + TILEPRO_CPU_CPP_ENDIAN_BUILTINS (); GNU_USER_TARGET_OS_CPP_BUILTINS (); } diff --git a/gcc-4_8-branch/gcc/config/tilepro/tilepro.c b/gcc-4_8-branch/gcc/config/tilepro/tilepro.c index 59618e4384b..957146dd52c 100644 --- a/gcc-4_8-branch/gcc/config/tilepro/tilepro.c +++ b/gcc-4_8-branch/gcc/config/tilepro/tilepro.c @@ -3167,6 +3167,12 @@ tilepro_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) + PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid) diff --git a/gcc-4_8-branch/gcc/config/tilepro/tilepro.md b/gcc-4_8-branch/gcc/config/tilepro/tilepro.md index ca8cf80ca18..ba9bc76d491 100644 --- a/gcc-4_8-branch/gcc/config/tilepro/tilepro.md +++ b/gcc-4_8-branch/gcc/config/tilepro/tilepro.md @@ -795,7 +795,7 @@ (define_expand "ctzdi2" [(set (match_operand:DI 0 "register_operand" "") - (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))] + (ctz:DI (match_operand:DI 1 "register_operand" "")))] "" { rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result; @@ -823,7 +823,7 @@ (define_expand "clzdi2" [(set (match_operand:DI 0 "register_operand" "") - (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))] + (clz:DI (match_operand:DI 1 "register_operand" "")))] "" { rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result; @@ -851,7 +851,7 @@ (define_expand "ffsdi2" [(set (match_operand:DI 0 "register_operand" "") - (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))] + (ffs:DI (match_operand:DI 1 "register_operand" "")))] "" { rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond; diff --git a/gcc-4_8-branch/gcc/cp/ChangeLog b/gcc-4_8-branch/gcc/cp/ChangeLog index 145c1b1fff7..6785033416e 100644 --- a/gcc-4_8-branch/gcc/cp/ChangeLog +++ b/gcc-4_8-branch/gcc/cp/ChangeLog @@ -1,3 +1,102 @@ +2014-01-31 Jason Merrill + + PR c++/58672 + * decl2.c (handle_tls_init): Handle null init fn. + + PR c++/55800 + * decl2.c (get_tls_init_fn): Copy DECL_EXTERNAL from the variable. + + PR c++/59646 + * call.c (convert_like_real) [ck_aggr]: Set TARGET_EXPR_LIST_INIT_P. + [ck_list]: Check for error_mark_node. + + PR c++/57043 + * pt.c (fn_type_unification): Don't do DEDUCE_EXACT check + during partial ordering. + +2014-01-30 Jason Merrill + + PR c++/57899 + * pt.c (instantiate_template_1): Save/restore local_specializations. + +2014-01-29 Jason Merrill + + PR c++/59989 + * pt.c (expand_template_argument_pack): Correct + non_default_args_count calculation. + + PR c++/58466 + * pt.c (unify_pack_expansion): Call expand_template_argument_pack. + +2014-01-28 Jason Merrill + + PR c++/58632 + * decl.c (lookup_and_check_tag): Ignore template parameters if + scope == ts_current. + * pt.c (check_template_shadow): Don't complain about the injected + class name. + +2014-01-27 Jason Merrill + + PR c++/54652 + * decl.c (duplicate_decls): Always use oldtype for TYPE_DECL. + + PR c++/58504 + * pt.c (tsubst_copy_and_build) [TRAIT_EXPR]: Use tsubst for + types. + + PR c++/58606 + * pt.c (template_parm_to_arg): Call convert_from_reference. + (tsubst_template_arg): Don't strip reference refs. + + PR c++/58639 + * call.c (build_aggr_conv): Reject value-initialization of reference. + + PR c++/58812 + * call.c (convert_like_real): Give helpful error about excess braces + for reference binding, too. + + PR c++/58814 + * typeck.c (cp_build_modify_expr): Make the RHS an rvalue before + stabilizing. + + PR c++/58837 + * typeck.c (cp_truthvalue_conversion): Use explicit comparison for + FUNCTION_DECL. + + PR c++/59097 + * decl.c (compute_array_index_type): Don't call + maybe_constant_value for a non-integral expression. + + PR c++/58965 + * mangle.c (write_guarded_var_name): Handle null DECL_NAME. + +2014-01-24 Paolo Carlini + + PR c++/57524 + * name-lookup.c (push_using_directive): Use timevar_cond_start. + +2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * semantics.c (finish_omp_clauses): Reject MIN_EXPR, MAX_EXPR, + BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs. + +2014-01-20 Marek Polacek + + Backported from mainline + 2014-01-17 Marek Polacek + + PR c++/59838 + * cvt.c (ocp_convert): Don't segfault on non-existing + ENUM_UNDERLYING_TYPE. + +2014-01-10 Paolo Carlini + + PR c++/56060 + PR c++/59730 + * pt.c (type_dependent_expression_p): Handle EXPR_PACK_EXPANSION. + 2013-12-12 Jason Merrill PR c++/58954 diff --git a/gcc-4_8-branch/gcc/cp/call.c b/gcc-4_8-branch/gcc/cp/call.c index a9c64981361..ca7d3edebdc 100644 --- a/gcc-4_8-branch/gcc/cp/call.c +++ b/gcc-4_8-branch/gcc/cp/call.c @@ -892,6 +892,9 @@ build_aggr_conv (tree type, tree ctor, int flags, tsubst_flags_t complain) if (i < CONSTRUCTOR_NELTS (ctor)) val = CONSTRUCTOR_ELT (ctor, i)->value; + else if (TREE_CODE (ftype) == REFERENCE_TYPE) + /* Value-initialization of reference is ill-formed. */ + return NULL; else { if (empty_ctor == NULL_TREE) @@ -5806,9 +5809,11 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, && convs->kind != ck_ambig && (convs->kind != ck_ref_bind || convs->user_conv_p) - && convs->kind != ck_rvalue + && (convs->kind != ck_rvalue + || SCALAR_TYPE_P (totype)) && convs->kind != ck_base) { + bool complained = false; conversion *t = convs; /* Give a helpful error if this is bad because of excess braces. */ @@ -5816,7 +5821,14 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, && SCALAR_TYPE_P (totype) && CONSTRUCTOR_NELTS (expr) > 0 && BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT (expr, 0)->value)) - permerror (loc, "too many braces around initializer for %qT", totype); + { + complained = true; + permerror (loc, "too many braces around initializer " + "for %qT", totype); + while (BRACE_ENCLOSED_INITIALIZER_P (expr) + && CONSTRUCTOR_NELTS (expr) == 1) + expr = CONSTRUCTOR_ELT (expr, 0)->value; + } for (; t ; t = next_conversion (t)) { @@ -5853,8 +5865,9 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, break; } - permerror (loc, "invalid conversion from %qT to %qT", - TREE_TYPE (expr), totype); + if (!complained) + permerror (loc, "invalid conversion from %qT to %qT", + TREE_TYPE (expr), totype); if (fn) permerror (DECL_SOURCE_LOCATION (fn), " initializing argument %P of %qD", argnum, fn); @@ -5999,6 +6012,8 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, to avoid the error about taking the address of a temporary. */ array = cp_build_addr_expr (array, complain); array = cp_convert (build_pointer_type (elttype), array, complain); + if (array == error_mark_node) + return error_mark_node; /* Build up the initializer_list object. */ totype = complete_type (totype); @@ -6023,8 +6038,11 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, return fold_if_not_in_template (expr); } expr = reshape_init (totype, expr, complain); - return get_target_expr_sfinae (digest_init (totype, expr, complain), + expr = get_target_expr_sfinae (digest_init (totype, expr, complain), complain); + if (expr != error_mark_node) + TARGET_EXPR_LIST_INIT_P (expr) = true; + return expr; default: break; diff --git a/gcc-4_8-branch/gcc/cp/cvt.c b/gcc-4_8-branch/gcc/cp/cvt.c index 340fececce2..17965071133 100644 --- a/gcc-4_8-branch/gcc/cp/cvt.c +++ b/gcc-4_8-branch/gcc/cp/cvt.c @@ -743,6 +743,7 @@ ocp_convert (tree type, tree expr, int convtype, int flags, unspecified. */ if ((complain & tf_warning) && TREE_CODE (e) == INTEGER_CST + && ENUM_UNDERLYING_TYPE (type) && !int_fits_type_p (e, ENUM_UNDERLYING_TYPE (type))) warning_at (loc, OPT_Wconversion, "the result of the conversion is unspecified because " diff --git a/gcc-4_8-branch/gcc/cp/decl.c b/gcc-4_8-branch/gcc/cp/decl.c index 893fbd161c5..9b2afdc3ceb 100644 --- a/gcc-4_8-branch/gcc/cp/decl.c +++ b/gcc-4_8-branch/gcc/cp/decl.c @@ -1867,9 +1867,9 @@ duplicate_decls (tree newdecl, tree olddecl, bool newdecl_is_friend) /* Merge the data types specified in the two decls. */ newtype = merge_types (TREE_TYPE (newdecl), TREE_TYPE (olddecl)); - /* If merge_types produces a non-typedef type, just use the old type. */ - if (TREE_CODE (newdecl) == TYPE_DECL - && newtype == DECL_ORIGINAL_TYPE (newdecl)) + /* For typedefs use the old type, as the new type's DECL_NAME points + at newdecl, which will be ggc_freed. */ + if (TREE_CODE (newdecl) == TYPE_DECL) newtype = oldtype; if (TREE_CODE (newdecl) == VAR_DECL) @@ -8193,7 +8193,9 @@ compute_array_index_type (tree name, tree size, tsubst_flags_t complain) abi_1_itype = error_mark_node; } - size = maybe_constant_value (size); + if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (type)) + size = maybe_constant_value (size); + if (!TREE_CONSTANT (size)) size = osize; } @@ -11891,7 +11893,10 @@ lookup_and_check_tag (enum tag_types tag_code, tree name, if (decl && (DECL_CLASS_TEMPLATE_P (decl) - || DECL_TEMPLATE_TEMPLATE_PARM_P (decl))) + /* If scope is ts_current we're defining a class, so ignore a + template template parameter. */ + || (scope != ts_current + && DECL_TEMPLATE_TEMPLATE_PARM_P (decl)))) decl = DECL_TEMPLATE_RESULT (decl); if (decl && TREE_CODE (decl) == TYPE_DECL) diff --git a/gcc-4_8-branch/gcc/cp/decl2.c b/gcc-4_8-branch/gcc/cp/decl2.c index 9252233fe82..7dd98c07e0e 100644 --- a/gcc-4_8-branch/gcc/cp/decl2.c +++ b/gcc-4_8-branch/gcc/cp/decl2.c @@ -2884,7 +2884,7 @@ get_tls_init_fn (tree var) TREE_PUBLIC (fn) = TREE_PUBLIC (var); DECL_ARTIFICIAL (fn) = true; DECL_COMDAT (fn) = DECL_COMDAT (var); - DECL_EXTERNAL (fn) = true; + DECL_EXTERNAL (fn) = DECL_EXTERNAL (var); if (DECL_ONE_ONLY (var)) make_decl_one_only (fn, cxx_comdat_group (fn)); if (TREE_PUBLIC (var)) @@ -3946,6 +3946,8 @@ handle_tls_init (void) if (TREE_PUBLIC (var)) { tree single_init_fn = get_tls_init_fn (var); + if (single_init_fn == NULL_TREE) + continue; cgraph_node *alias = cgraph_same_body_alias (cgraph_get_create_node (fn), single_init_fn, fn); diff --git a/gcc-4_8-branch/gcc/cp/mangle.c b/gcc-4_8-branch/gcc/cp/mangle.c index 10c2e2beb0c..4d3799480f9 100644 --- a/gcc-4_8-branch/gcc/cp/mangle.c +++ b/gcc-4_8-branch/gcc/cp/mangle.c @@ -3773,7 +3773,8 @@ mangle_conv_op_name_for_type (const tree type) static void write_guarded_var_name (const tree variable) { - if (strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0) + if (DECL_NAME (variable) + && strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0) /* The name of a guard variable for a reference temporary should refer to the reference, not the temporary. */ write_string (IDENTIFIER_POINTER (DECL_NAME (variable)) + 4); diff --git a/gcc-4_8-branch/gcc/cp/name-lookup.c b/gcc-4_8-branch/gcc/cp/name-lookup.c index c121a4163a9..5763b9b4257 100644 --- a/gcc-4_8-branch/gcc/cp/name-lookup.c +++ b/gcc-4_8-branch/gcc/cp/name-lookup.c @@ -5605,9 +5605,9 @@ static tree push_using_directive (tree used) { tree ret; - timevar_start (TV_NAME_LOOKUP); + bool subtime = timevar_cond_start (TV_NAME_LOOKUP); ret = push_using_directive_1 (used); - timevar_stop (TV_NAME_LOOKUP); + timevar_cond_stop (TV_NAME_LOOKUP, subtime); return ret; } diff --git a/gcc-4_8-branch/gcc/cp/pt.c b/gcc-4_8-branch/gcc/cp/pt.c index 38c494c8a95..2ac1e66a5c7 100644 --- a/gcc-4_8-branch/gcc/cp/pt.c +++ b/gcc-4_8-branch/gcc/cp/pt.c @@ -3436,7 +3436,7 @@ expand_template_argument_pack (tree args) for (i = 0; i < num_packed; ++i, ++out_arg) TREE_VEC_ELT (result_args, out_arg) = TREE_VEC_ELT(packed, i); if (non_default_args_count > 0) - non_default_args_count += num_packed; + non_default_args_count += num_packed - 1; } else { @@ -3491,6 +3491,11 @@ check_template_shadow (tree decl) || TEMPLATE_PARMS_FOR_INLINE (current_template_parms)) return true; + /* Don't complain about the injected class name, as we've already + complained about the class itself. */ + if (DECL_SELF_REFERENCE_P (decl)) + return false; + error ("declaration of %q+#D", decl); error (" shadows template parm %q+#D", olddecl); return false; @@ -3818,6 +3823,7 @@ template_parm_to_arg (tree t) SET_NON_DEFAULT_TEMPLATE_ARGS_COUNT (vec, TREE_VEC_LENGTH (vec)); #endif + t = convert_from_reference (t); TREE_VEC_ELT (vec, 0) = make_pack_expansion (t); t = make_node (NONTYPE_ARGUMENT_PACK); @@ -9107,10 +9113,6 @@ tsubst_template_arg (tree t, tree args, tsubst_flags_t complain, tree in_decl) /*integral_constant_expression_p=*/true); if (!(complain & tf_warning)) --c_inhibit_evaluation_warnings; - /* Preserve the raw-reference nature of T. */ - if (TREE_TYPE (t) && TREE_CODE (TREE_TYPE (t)) == REFERENCE_TYPE - && REFERENCE_REF_P (r)) - r = TREE_OPERAND (r, 0); } return r; } @@ -14475,12 +14477,12 @@ tsubst_copy_and_build (tree t, case TRAIT_EXPR: { - tree type1 = tsubst_copy (TRAIT_EXPR_TYPE1 (t), args, - complain, in_decl); + tree type1 = tsubst (TRAIT_EXPR_TYPE1 (t), args, + complain, in_decl); tree type2 = TRAIT_EXPR_TYPE2 (t); if (type2) - type2 = tsubst_copy (type2, args, complain, in_decl); + type2 = tsubst (type2, args, complain, in_decl); RETURN (finish_trait_expr (TRAIT_EXPR_KIND (t), type1, type2)); } @@ -14782,6 +14784,8 @@ instantiate_template_1 (tree tmpl, tree orig_args, tsubst_flags_t complain) /* Instantiation of the function happens in the context of the function template, not the context of the overload resolution we're doing. */ push_to_top_level (); + struct pointer_map_t *saved_local_specializations = local_specializations; + local_specializations = NULL; /* If there are dependent arguments, e.g. because we're doing partial ordering, make sure processing_template_decl stays set. */ if (uses_template_parms (targ_ptr)) @@ -14797,6 +14801,7 @@ instantiate_template_1 (tree tmpl, tree orig_args, tsubst_flags_t complain) targ_ptr, complain, gen_tmpl); if (DECL_CLASS_SCOPE_P (gen_tmpl)) pop_nested_class (); + local_specializations = saved_local_specializations; pop_from_top_level (); if (fndecl == error_mark_node) @@ -15196,8 +15201,11 @@ fn_type_unification (tree fn, /* If we're looking for an exact match, check that what we got is indeed an exact match. It might not be if some template - parameters are used in non-deduced contexts. */ - if (strict == DEDUCE_EXACT) + parameters are used in non-deduced contexts. But don't check + for an exact match if we have dependent template arguments; + in that case we're doing partial ordering, and we already know + that we have two candidates that will provide the actual type. */ + if (strict == DEDUCE_EXACT && !any_dependent_template_arguments_p (targs)) { tree substed = TREE_TYPE (decl); unsigned int i; @@ -16211,6 +16219,9 @@ unify_pack_expansion (tree tparms, tree targs, tree packed_parms, tree pattern = PACK_EXPANSION_PATTERN (parm); tree pack, packs = NULL_TREE; int i, start = TREE_VEC_LENGTH (packed_parms) - 1; + + packed_args = expand_template_argument_pack (packed_args); + int len = TREE_VEC_LENGTH (packed_args); /* Determine the parameter packs we will be deducing from the @@ -19958,6 +19969,10 @@ type_dependent_expression_p (tree expression) if (TREE_CODE (expression) == SCOPE_REF) return false; + /* Always dependent, on the number of arguments if nothing else. */ + if (TREE_CODE (expression) == EXPR_PACK_EXPANSION) + return true; + if (BASELINK_P (expression)) expression = BASELINK_FUNCTIONS (expression); diff --git a/gcc-4_8-branch/gcc/cp/semantics.c b/gcc-4_8-branch/gcc/cp/semantics.c index c2b9b4af245..16b50e09698 100644 --- a/gcc-4_8-branch/gcc/cp/semantics.c +++ b/gcc-4_8-branch/gcc/cp/semantics.c @@ -4291,7 +4291,8 @@ finish_omp_clauses (tree clauses) error ("%qE has invalid type for %", t); remove = true; } - else if (FLOAT_TYPE_P (TREE_TYPE (t))) + else if (FLOAT_TYPE_P (TREE_TYPE (t)) + || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) { enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c); switch (r_code) @@ -4299,10 +4300,26 @@ finish_omp_clauses (tree clauses) case PLUS_EXPR: case MULT_EXPR: case MINUS_EXPR: + break; case MIN_EXPR: case MAX_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_code = ERROR_MARK; break; + case BIT_AND_EXPR: + case BIT_XOR_EXPR: + case BIT_IOR_EXPR: default: + r_code = ERROR_MARK; + break; + case TRUTH_ANDIF_EXPR: + case TRUTH_ORIF_EXPR: + if (FLOAT_TYPE_P (TREE_TYPE (t))) + r_code = ERROR_MARK; + break; + } + if (r_code == ERROR_MARK) + { error ("%qE has invalid type for %", t, operator_name_info[r_code].name); remove = true; diff --git a/gcc-4_8-branch/gcc/cp/typeck.c b/gcc-4_8-branch/gcc/cp/typeck.c index cec6c452ade..299e1f45352 100644 --- a/gcc-4_8-branch/gcc/cp/typeck.c +++ b/gcc-4_8-branch/gcc/cp/typeck.c @@ -5010,7 +5010,10 @@ tree cp_truthvalue_conversion (tree expr) { tree type = TREE_TYPE (expr); - if (TYPE_PTRDATAMEM_P (type)) + if (TYPE_PTRDATAMEM_P (type) + /* Avoid ICE on invalid use of non-static member function. */ + || (TREE_CODE (expr) == FUNCTION_DECL + && DECL_NONSTATIC_MEMBER_FUNCTION_P (expr))) return build_binary_op (EXPR_LOCATION (expr), NE_EXPR, expr, nullptr_node, 1); else if (TYPE_PTR_P (type) || TYPE_PTRMEMFUNC_P (type)) @@ -7196,8 +7199,7 @@ cp_build_modify_expr (tree lhs, enum tree_code modifycode, tree rhs, side effect associated with any single compound assignment operator. -- end note ] */ lhs = stabilize_reference (lhs); - if (TREE_SIDE_EFFECTS (rhs)) - rhs = mark_rvalue_use (rhs); + rhs = rvalue (rhs); rhs = stabilize_expr (rhs, &init); newrhs = cp_build_binary_op (input_location, modifycode, lhs, rhs, diff --git a/gcc-4_8-branch/gcc/fold-const.c b/gcc-4_8-branch/gcc/fold-const.c index b1e957caa2a..0ae3229509a 100644 --- a/gcc-4_8-branch/gcc/fold-const.c +++ b/gcc-4_8-branch/gcc/fold-const.c @@ -4925,12 +4925,16 @@ fold_range_test (location_t loc, enum tree_code code, tree type, int in0_p, in1_p, in_p; tree low0, low1, low, high0, high1, high; bool strict_overflow_p = false; - tree lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p); - tree rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p); - tree tem; + tree tem, lhs, rhs; const char * const warnmsg = G_("assuming signed overflow does not occur " "when simplifying range test"); + if (!INTEGRAL_TYPE_P (type)) + return 0; + + lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p); + rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p); + /* If this is an OR operation, invert both sides; we will invert again at the end. */ if (or_op) diff --git a/gcc-4_8-branch/gcc/fortran/ChangeLog b/gcc-4_8-branch/gcc/fortran/ChangeLog index 0c1004629b5..2ec8e7fa5e3 100644 --- a/gcc-4_8-branch/gcc/fortran/ChangeLog +++ b/gcc-4_8-branch/gcc/fortran/ChangeLog @@ -1,3 +1,56 @@ +2014-02-01 Paul Thomas + + PR fortran/59414 + * trans-stmt.c (gfc_trans_allocate): Before the pointer + assignment to transfer the source _vptr to a class allocate + expression, the final class reference should be exposed. The + tail that includes the _data and array references is stored. + This reduced expression is transferred to 'lhs' and the _vptr + added. Then the tail is restored to the allocate expression. + +2014-01-26 Mikael Morin + + PR fortran/58007 + * module.c + (fp2, find_pointer2): Remove. + (mio_component_ref): Don't forcedfully set the containing derived type + symbol for loading. Remove unused argument. + (mio_ref): Update caller + (skip_list): New argument nest_level. Initialize level with the new + argument. + (read_module): Add forced pointer components association for derived + type symbols. + +2014-01-19 Paul Thomas + + Backport from mainline + 2013-12-01 Paul Thomas + + PR fortran/58410 + * trans-array.c (gfc_alloc_allocatable_for_assignment): Do not + use the array bounds of an unallocated array but set its size + to zero instead. + +2014-01-19 Paul Thomas + + Backport from mainline + 2013-12-01 Paul Thomas + + PR fortran/34547 + * resolve.c (resolve_transfer): EXPR_NULL is always in an + invalid context in a transfer statement. + +2014-01-11 Janus Weil + + Backport from mainline + 2013-12-29 Janus Weil + + PR fortran/59612 + PR fortran/57042 + * dump-parse-tree.c (show_typespec): Check for charlen. + * invoke.texi: Fix documentation of -fdump-fortran-optimized and + -fdump-parse-tree. + 2014-01-04 Janus Weil Backport from mainline diff --git a/gcc-4_8-branch/gcc/fortran/dump-parse-tree.c b/gcc-4_8-branch/gcc/fortran/dump-parse-tree.c index 14ff0041219..501a4ebb566 100644 --- a/gcc-4_8-branch/gcc/fortran/dump-parse-tree.c +++ b/gcc-4_8-branch/gcc/fortran/dump-parse-tree.c @@ -110,7 +110,8 @@ show_typespec (gfc_typespec *ts) break; case BT_CHARACTER: - show_expr (ts->u.cl->length); + if (ts->u.cl) + show_expr (ts->u.cl->length); fprintf(dumpfile, " %d", ts->kind); break; diff --git a/gcc-4_8-branch/gcc/fortran/invoke.texi b/gcc-4_8-branch/gcc/fortran/invoke.texi index db958f9b37f..b0b43d8478b 100644 --- a/gcc-4_8-branch/gcc/fortran/invoke.texi +++ b/gcc-4_8-branch/gcc/fortran/invoke.texi @@ -982,11 +982,12 @@ Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the GNU Fortran compiler itself. -@item -fdump-optimized-tree +@item -fdump-fortran-optimized @opindex @code{fdump-fortran-optimized} Output the parse tree after front-end optimization. Only really useful for debugging the GNU Fortran compiler itself. +@item -fdump-parse-tree @opindex @code{fdump-parse-tree} Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the diff --git a/gcc-4_8-branch/gcc/fortran/module.c b/gcc-4_8-branch/gcc/fortran/module.c index f0f8f971ed8..c267ee7d610 100644 --- a/gcc-4_8-branch/gcc/fortran/module.c +++ b/gcc-4_8-branch/gcc/fortran/module.c @@ -386,37 +386,6 @@ get_integer (int integer) } -/* Recursive function to find a pointer within a tree by brute force. */ - -static pointer_info * -fp2 (pointer_info *p, const void *target) -{ - pointer_info *q; - - if (p == NULL) - return NULL; - - if (p->u.pointer == target) - return p; - - q = fp2 (p->left, target); - if (q != NULL) - return q; - - return fp2 (p->right, target); -} - - -/* During reading, find a pointer_info node from the pointer value. - This amounts to a brute-force search. */ - -static pointer_info * -find_pointer2 (void *p) -{ - return fp2 (pi_root, p); -} - - /* Resolve any fixups using a known pointer. */ static void @@ -2522,45 +2491,13 @@ mio_pointer_ref (void *gp) the namespace and is not loaded again. */ static void -mio_component_ref (gfc_component **cp, gfc_symbol *sym) +mio_component_ref (gfc_component **cp) { - char name[GFC_MAX_SYMBOL_LEN + 1]; - gfc_component *q; pointer_info *p; p = mio_pointer_ref (cp); if (p->type == P_UNKNOWN) p->type = P_COMPONENT; - - if (iomode == IO_OUTPUT) - mio_pool_string (&(*cp)->name); - else - { - mio_internal_string (name); - - if (sym && sym->attr.is_class) - sym = sym->components->ts.u.derived; - - /* It can happen that a component reference can be read before the - associated derived type symbol has been loaded. Return now and - wait for a later iteration of load_needed. */ - if (sym == NULL) - return; - - if (sym->components != NULL && p->u.pointer == NULL) - { - /* Symbol already loaded, so search by name. */ - q = gfc_find_component (sym, name, true, true); - - if (q) - associate_integer_pointer (p, q); - } - - /* Make sure this symbol will eventually be loaded. */ - p = find_pointer2 (sym); - if (p->u.rsym.state == UNUSED) - p->u.rsym.state = NEEDED; - } } @@ -2917,7 +2854,7 @@ mio_ref (gfc_ref **rp) case REF_COMPONENT: mio_symbol_ref (&r->u.c.sym); - mio_component_ref (&r->u.c.component, r->u.c.sym); + mio_component_ref (&r->u.c.component); break; case REF_SUBSTRING: @@ -3772,7 +3709,9 @@ mio_full_f2k_derived (gfc_symbol *sym) /* Unlike most other routines, the address of the symbol node is already - fixed on input and the name/module has already been filled in. */ + fixed on input and the name/module has already been filled in. + If you update the symbol format here, don't forget to update read_module + as well (look for "seek to the symbol's component list"). */ static void mio_symbol (gfc_symbol *sym) @@ -3782,6 +3721,7 @@ mio_symbol (gfc_symbol *sym) mio_lparen (); mio_symbol_attribute (&sym->attr); + mio_typespec (&sym->ts); if (sym->ts.type == BT_CLASS) sym->attr.class_ok = 1; @@ -3812,7 +3752,6 @@ mio_symbol (gfc_symbol *sym) /* Note that components are always saved, even if they are supposed to be private. Component access is checked during searching. */ - mio_component_list (&sym->components, sym->attr.vtype); if (sym->components != NULL) @@ -3914,14 +3853,17 @@ find_symbol (gfc_symtree *st, const char *name, } -/* Skip a list between balanced left and right parens. */ +/* Skip a list between balanced left and right parens. + By setting NEST_LEVEL one assumes that a number of NEST_LEVEL opening parens + have been already parsed by hand, and the remaining of the content is to be + skipped here. The default value is 0 (balanced parens). */ static void -skip_list (void) +skip_list (int nest_level = 0) { int level; - level = 0; + level = nest_level; do { switch (parse_atom ()) @@ -4555,7 +4497,6 @@ read_module (void) info->u.rsym.ns = atom_int; get_module_locus (&info->u.rsym.where); - skip_list (); /* See if the symbol has already been loaded by a previous module. If so, we reference the existing symbol and prevent it from @@ -4566,10 +4507,56 @@ read_module (void) if (sym == NULL || (sym->attr.flavor == FL_VARIABLE && info->u.rsym.ns !=1)) - continue; + { + skip_list (); + continue; + } info->u.rsym.state = USED; info->u.rsym.sym = sym; + /* The current symbol has already been loaded, so we can avoid loading + it again. However, if it is a derived type, some of its components + can be used in expressions in the module. To avoid the module loading + failing, we need to associate the module's component pointer indexes + with the existing symbol's component pointers. */ + if (sym->attr.flavor == FL_DERIVED) + { + gfc_component *c; + + /* First seek to the symbol's component list. */ + mio_lparen (); /* symbol opening. */ + skip_list (); /* skip symbol attribute. */ + skip_list (); /* typespec. */ + require_atom (ATOM_INTEGER); /* namespace ref. */ + require_atom (ATOM_INTEGER); /* common ref. */ + skip_list (); /* formal args. */ + /* no value. */ + skip_list (); /* array_spec. */ + require_atom (ATOM_INTEGER); /* result. */ + /* not a cray pointer. */ + + mio_lparen (); /* component list opening. */ + for (c = sym->components; c; c = c->next) + { + pointer_info *p; + const char *comp_name; + int n; + + mio_lparen (); /* component opening. */ + mio_integer (&n); + p = get_integer (n); + if (p->u.pointer == NULL) + associate_integer_pointer (p, c); + mio_pool_string (&comp_name); + gcc_assert (comp_name == c->name); + skip_list (1); /* component end. */ + } + mio_rparen (); /* component list closing. */ + + skip_list (1); /* symbol end. */ + } + else + skip_list (); /* Some symbols do not have a namespace (eg. formal arguments), so the automatic "unique symtree" mechanism must be suppressed diff --git a/gcc-4_8-branch/gcc/fortran/resolve.c b/gcc-4_8-branch/gcc/fortran/resolve.c index 5a06498a19b..bdca5300f71 100644 --- a/gcc-4_8-branch/gcc/fortran/resolve.c +++ b/gcc-4_8-branch/gcc/fortran/resolve.c @@ -1,5 +1,5 @@ /* Perform type resolution on the various structures. - Copyright (C) 2001-2013 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. Contributed by Andy Vaught This file is part of GCC. @@ -8705,10 +8705,11 @@ resolve_transfer (gfc_code *code) && exp->value.op.op == INTRINSIC_PARENTHESES) exp = exp->value.op.op1; - if (exp && exp->expr_type == EXPR_NULL && exp->ts.type == BT_UNKNOWN) + if (exp && exp->expr_type == EXPR_NULL + && code->ext.dt) { - gfc_error ("NULL intrinsic at %L in data transfer statement requires " - "MOLD=", &exp->where); + gfc_error ("Invalid context for NULL () intrinsic at %L", + &exp->where); return; } diff --git a/gcc-4_8-branch/gcc/fortran/trans-array.c b/gcc-4_8-branch/gcc/fortran/trans-array.c index b34f6fb19a6..2927b80d444 100644 --- a/gcc-4_8-branch/gcc/fortran/trans-array.c +++ b/gcc-4_8-branch/gcc/fortran/trans-array.c @@ -1,5 +1,5 @@ /* Array translation routines - Copyright (C) 2002-2013 Free Software Foundation, Inc. + Copyright (C) 2002-2014 Free Software Foundation, Inc. Contributed by Paul Brook and Steven Bosscher @@ -7940,6 +7940,7 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, tree size1; tree size2; tree array1; + tree cond_null; tree cond; tree tmp; tree tmp2; @@ -8015,9 +8016,9 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, jump_label2 = gfc_build_label_decl (NULL_TREE); /* Allocate if data is NULL. */ - cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, + cond_null = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, array1, build_int_cst (TREE_TYPE (array1), 0)); - tmp = build3_v (COND_EXPR, cond, + tmp = build3_v (COND_EXPR, cond_null, build1_v (GOTO_EXPR, jump_label1), build_empty_stmt (input_location)); gfc_add_expr_to_block (&fblock, tmp); @@ -8069,13 +8070,25 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, tmp = build1_v (LABEL_EXPR, jump_label1); gfc_add_expr_to_block (&fblock, tmp); - size1 = gfc_conv_descriptor_size (desc, expr1->rank); + /* If the lhs has not been allocated, its bounds will not have been + initialized and so its size is set to zero. */ + size1 = gfc_create_var (gfc_array_index_type, NULL); + gfc_init_block (&alloc_block); + gfc_add_modify (&alloc_block, size1, gfc_index_zero_node); + gfc_init_block (&realloc_block); + gfc_add_modify (&realloc_block, size1, + gfc_conv_descriptor_size (desc, expr1->rank)); + tmp = build3_v (COND_EXPR, cond_null, + gfc_finish_block (&alloc_block), + gfc_finish_block (&realloc_block)); + gfc_add_expr_to_block (&fblock, tmp); - /* Get the rhs size. Fix both sizes. */ + /* Get the rhs size and fix it. */ if (expr2) desc2 = rss->info->data.array.descriptor; else desc2 = NULL_TREE; + size2 = gfc_index_one_node; for (n = 0; n < expr2->rank; n++) { @@ -8089,8 +8102,6 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, gfc_array_index_type, tmp, size2); } - - size1 = gfc_evaluate_now (size1, &fblock); size2 = gfc_evaluate_now (size2, &fblock); cond = fold_build2_loc (input_location, NE_EXPR, boolean_type_node, diff --git a/gcc-4_8-branch/gcc/fortran/trans-stmt.c b/gcc-4_8-branch/gcc/fortran/trans-stmt.c index 430b10e3760..1d8588d6072 100644 --- a/gcc-4_8-branch/gcc/fortran/trans-stmt.c +++ b/gcc-4_8-branch/gcc/fortran/trans-stmt.c @@ -5104,10 +5104,49 @@ gfc_trans_allocate (gfc_code * code) { gfc_expr *lhs, *rhs; gfc_se lse; + gfc_ref *ref, *class_ref, *tail; + + /* Find the last class reference. */ + class_ref = NULL; + for (ref = e->ref; ref; ref = ref->next) + { + if (ref->type == REF_COMPONENT + && ref->u.c.component->ts.type == BT_CLASS) + class_ref = ref; + + if (ref->next == NULL) + break; + } + + /* Remove and store all subsequent references after the + CLASS reference. */ + if (class_ref) + { + tail = class_ref->next; + class_ref->next = NULL; + } + else + { + tail = e->ref; + e->ref = NULL; + } lhs = gfc_expr_to_initialize (e); gfc_add_vptr_component (lhs); + /* Remove the _vptr component and restore the original tail + references. */ + if (class_ref) + { + gfc_free_ref_list (class_ref->next); + class_ref->next = tail; + } + else + { + gfc_free_ref_list (e->ref); + e->ref = tail; + } + if (class_expr != NULL_TREE) { /* Polymorphic SOURCE: VPTR must be determined at run time. */ diff --git a/gcc-4_8-branch/gcc/gimple-fold.c b/gcc-4_8-branch/gcc/gimple-fold.c index 1de281a97d5..f8593501435 100644 --- a/gcc-4_8-branch/gcc/gimple-fold.c +++ b/gcc-4_8-branch/gcc/gimple-fold.c @@ -866,6 +866,7 @@ gimple_fold_builtin (gimple stmt) break; case BUILT_IN_STRCPY: case BUILT_IN_STRNCPY: + case BUILT_IN_STRCAT: arg_idx = 1; type = 0; break; @@ -941,6 +942,13 @@ gimple_fold_builtin (gimple stmt) val[1]); break; + case BUILT_IN_STRCAT: + if (val[1] && is_gimple_val (val[1]) && nargs == 2) + result = fold_builtin_strcat (loc, gimple_call_arg (stmt, 0), + gimple_call_arg (stmt, 1), + val[1]); + break; + case BUILT_IN_FPUTS: if (nargs == 2) result = fold_builtin_fputs (loc, gimple_call_arg (stmt, 0), diff --git a/gcc-4_8-branch/gcc/gimple-low.c b/gcc-4_8-branch/gcc/gimple-low.c index b06d194da65..9ac0d60e542 100644 --- a/gcc-4_8-branch/gcc/gimple-low.c +++ b/gcc-4_8-branch/gcc/gimple-low.c @@ -238,6 +238,7 @@ gimple_check_call_args (gimple stmt, tree fndecl) break; arg = gimple_call_arg (stmt, i); if (p == error_mark_node + || DECL_ARG_TYPE (p) == error_mark_node || arg == error_mark_node || (!types_compatible_p (DECL_ARG_TYPE (p), TREE_TYPE (arg)) && !fold_convertible_p (DECL_ARG_TYPE (p), arg))) diff --git a/gcc-4_8-branch/gcc/gimple.c b/gcc-4_8-branch/gcc/gimple.c index 97a37e32df7..9b5de4a25a3 100644 --- a/gcc-4_8-branch/gcc/gimple.c +++ b/gcc-4_8-branch/gcc/gimple.c @@ -3841,42 +3841,46 @@ get_base_loadstore (tree op) /* For the statement STMT call the callbacks VISIT_LOAD, VISIT_STORE and VISIT_ADDR if non-NULL on loads, store and address-taken operands - passing the STMT, the base of the operand and DATA to it. The base - will be either a decl, an indirect reference (including TARGET_MEM_REF) - or the argument of an address expression. + passing the STMT, the base of the operand, the operand itself containing + the base and DATA to it. The base will be either a decl, an indirect + reference (including TARGET_MEM_REF) or the argument of an address + expression. Returns the results of these callbacks or'ed. */ bool walk_stmt_load_store_addr_ops (gimple stmt, void *data, - bool (*visit_load)(gimple, tree, void *), - bool (*visit_store)(gimple, tree, void *), - bool (*visit_addr)(gimple, tree, void *)) + walk_stmt_load_store_addr_fn visit_load, + walk_stmt_load_store_addr_fn visit_store, + walk_stmt_load_store_addr_fn visit_addr) { bool ret = false; unsigned i; if (gimple_assign_single_p (stmt)) { - tree lhs, rhs; + tree lhs, rhs, arg; if (visit_store) { - lhs = get_base_loadstore (gimple_assign_lhs (stmt)); + arg = gimple_assign_lhs (stmt); + lhs = get_base_loadstore (arg); if (lhs) - ret |= visit_store (stmt, lhs, data); + ret |= visit_store (stmt, lhs, arg, data); } - rhs = gimple_assign_rhs1 (stmt); + arg = gimple_assign_rhs1 (stmt); + rhs = arg; while (handled_component_p (rhs)) rhs = TREE_OPERAND (rhs, 0); if (visit_addr) { if (TREE_CODE (rhs) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), arg, data); else if (TREE_CODE (rhs) == TARGET_MEM_REF && TREE_CODE (TMR_BASE (rhs)) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), arg, + data); else if (TREE_CODE (rhs) == OBJ_TYPE_REF && TREE_CODE (OBJ_TYPE_REF_OBJECT (rhs)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (rhs), - 0), data); + 0), arg, data); else if (TREE_CODE (rhs) == CONSTRUCTOR) { unsigned int ix; @@ -3884,23 +3888,23 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (rhs), ix, val) if (TREE_CODE (val) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (val, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (val, 0), arg, data); else if (TREE_CODE (val) == OBJ_TYPE_REF && TREE_CODE (OBJ_TYPE_REF_OBJECT (val)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (val), - 0), data); + 0), arg, data); } lhs = gimple_assign_lhs (stmt); if (TREE_CODE (lhs) == TARGET_MEM_REF && TREE_CODE (TMR_BASE (lhs)) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), lhs, data); } if (visit_load) { rhs = get_base_loadstore (rhs); if (rhs) - ret |= visit_load (stmt, rhs, data); + ret |= visit_load (stmt, rhs, arg, data); } } else if (visit_addr @@ -3913,17 +3917,17 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, if (op == NULL_TREE) ; else if (TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); /* COND_EXPR and VCOND_EXPR rhs1 argument is a comparison tree with two operands. */ else if (i == 1 && COMPARISON_CLASS_P (op)) { if (TREE_CODE (TREE_OPERAND (op, 0)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 0), - 0), data); + 0), op, data); if (TREE_CODE (TREE_OPERAND (op, 1)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 1), - 0), data); + 0), op, data); } } } @@ -3931,38 +3935,39 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { if (visit_store) { - tree lhs = gimple_call_lhs (stmt); - if (lhs) + tree arg = gimple_call_lhs (stmt); + if (arg) { - lhs = get_base_loadstore (lhs); + tree lhs = get_base_loadstore (arg); if (lhs) - ret |= visit_store (stmt, lhs, data); + ret |= visit_store (stmt, lhs, arg, data); } } if (visit_load || visit_addr) for (i = 0; i < gimple_call_num_args (stmt); ++i) { - tree rhs = gimple_call_arg (stmt, i); + tree arg = gimple_call_arg (stmt, i); if (visit_addr - && TREE_CODE (rhs) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data); + && TREE_CODE (arg) == ADDR_EXPR) + ret |= visit_addr (stmt, TREE_OPERAND (arg, 0), arg, data); else if (visit_load) { - rhs = get_base_loadstore (rhs); + tree rhs = get_base_loadstore (arg); if (rhs) - ret |= visit_load (stmt, rhs, data); + ret |= visit_load (stmt, rhs, arg, data); } } if (visit_addr && gimple_call_chain (stmt) && TREE_CODE (gimple_call_chain (stmt)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (gimple_call_chain (stmt), 0), - data); + gimple_call_chain (stmt), data); if (visit_addr && gimple_call_return_slot_opt_p (stmt) && gimple_call_lhs (stmt) != NULL_TREE && TREE_ADDRESSABLE (TREE_TYPE (gimple_call_lhs (stmt)))) - ret |= visit_addr (stmt, gimple_call_lhs (stmt), data); + ret |= visit_addr (stmt, gimple_call_lhs (stmt), + gimple_call_lhs (stmt), data); } else if (gimple_code (stmt) == GIMPLE_ASM) { @@ -3978,7 +3983,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, tree link = gimple_asm_output_op (stmt, i); tree op = get_base_loadstore (TREE_VALUE (link)); if (op && visit_store) - ret |= visit_store (stmt, op, data); + ret |= visit_store (stmt, op, TREE_VALUE (link), data); if (visit_addr) { constraint = TREE_STRING_POINTER @@ -3987,7 +3992,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, parse_output_constraint (&constraint, i, 0, 0, &allows_mem, &allows_reg, &is_inout); if (op && !allows_reg && allows_mem) - ret |= visit_addr (stmt, op, data); + ret |= visit_addr (stmt, op, TREE_VALUE (link), data); } } if (visit_load || visit_addr) @@ -3997,14 +4002,14 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, tree op = TREE_VALUE (link); if (visit_addr && TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); else if (visit_load || visit_addr) { op = get_base_loadstore (op); if (op) { if (visit_load) - ret |= visit_load (stmt, op, data); + ret |= visit_load (stmt, op, TREE_VALUE (link), data); if (visit_addr) { constraint = TREE_STRING_POINTER @@ -4013,7 +4018,8 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, 0, oconstraints, &allows_mem, &allows_reg); if (!allows_reg && allows_mem) - ret |= visit_addr (stmt, op, data); + ret |= visit_addr (stmt, op, TREE_VALUE (link), + data); } } } @@ -4026,12 +4032,12 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { if (visit_addr && TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); else if (visit_load) { - op = get_base_loadstore (op); - if (op) - ret |= visit_load (stmt, op, data); + tree base = get_base_loadstore (op); + if (base) + ret |= visit_load (stmt, base, op, data); } } } @@ -4042,7 +4048,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { tree op = PHI_ARG_DEF (stmt, i); if (TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); } } else if (visit_addr @@ -4050,7 +4056,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { tree op = gimple_goto_dest (stmt); if (TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); } return ret; @@ -4061,8 +4067,8 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, bool walk_stmt_load_store_ops (gimple stmt, void *data, - bool (*visit_load)(gimple, tree, void *), - bool (*visit_store)(gimple, tree, void *)) + walk_stmt_load_store_addr_fn visit_load, + walk_stmt_load_store_addr_fn visit_store) { return walk_stmt_load_store_addr_ops (stmt, data, visit_load, visit_store, NULL); @@ -4071,8 +4077,7 @@ walk_stmt_load_store_ops (gimple stmt, void *data, /* Helper for gimple_ior_addresses_taken_1. */ static bool -gimple_ior_addresses_taken_1 (gimple stmt ATTRIBUTE_UNUSED, - tree addr, void *data) +gimple_ior_addresses_taken_1 (gimple, tree addr, tree, void *data) { bitmap addresses_taken = (bitmap)data; addr = get_base_address (addr); diff --git a/gcc-4_8-branch/gcc/gimple.h b/gcc-4_8-branch/gcc/gimple.h index 227e56a4817..86b13451f23 100644 --- a/gcc-4_8-branch/gcc/gimple.h +++ b/gcc-4_8-branch/gcc/gimple.h @@ -887,13 +887,14 @@ extern tree gimple_signed_type (tree); extern alias_set_type gimple_get_alias_set (tree); extern void count_uses_and_derefs (tree, gimple, unsigned *, unsigned *, unsigned *); +typedef bool (*walk_stmt_load_store_addr_fn) (gimple, tree, tree, void *); extern bool walk_stmt_load_store_addr_ops (gimple, void *, - bool (*)(gimple, tree, void *), - bool (*)(gimple, tree, void *), - bool (*)(gimple, tree, void *)); + walk_stmt_load_store_addr_fn, + walk_stmt_load_store_addr_fn, + walk_stmt_load_store_addr_fn); extern bool walk_stmt_load_store_ops (gimple, void *, - bool (*)(gimple, tree, void *), - bool (*)(gimple, tree, void *)); + walk_stmt_load_store_addr_fn, + walk_stmt_load_store_addr_fn); extern bool gimple_ior_addresses_taken (bitmap, gimple); extern bool gimple_call_builtin_p (gimple, enum built_in_class); extern bool gimple_call_builtin_p (gimple, enum built_in_function); diff --git a/gcc-4_8-branch/gcc/ifcvt.c b/gcc-4_8-branch/gcc/ifcvt.c index 88967a6c248..e3353a5f26b 100644 --- a/gcc-4_8-branch/gcc/ifcvt.c +++ b/gcc-4_8-branch/gcc/ifcvt.c @@ -115,7 +115,11 @@ count_bb_insns (const_basic_block bb) while (1) { - if (CALL_P (insn) || NONJUMP_INSN_P (insn)) + if ((CALL_P (insn) || NONJUMP_INSN_P (insn)) + /* Don't count USE/CLOBBER insns, flow_find_cross_jump etc. + don't count them either and we need consistency. */ + && GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER) count++; if (insn == BB_END (bb)) @@ -505,7 +509,10 @@ cond_exec_process_if_block (ce_if_block_t * ce_info, n_insns -= 2 * n_matching; } - if (then_start && else_start) + if (then_start + && else_start + && then_n_insns > n_matching + && else_n_insns > n_matching) { int longest_match = MIN (then_n_insns - n_matching, else_n_insns - n_matching); diff --git a/gcc-4_8-branch/gcc/ipa-prop.c b/gcc-4_8-branch/gcc/ipa-prop.c index 47d487d158e..3053aa058b7 100644 --- a/gcc-4_8-branch/gcc/ipa-prop.c +++ b/gcc-4_8-branch/gcc/ipa-prop.c @@ -623,16 +623,22 @@ parm_preserved_before_stmt_p (struct param_analysis_info *parm_ainfo, if (parm_ainfo && parm_ainfo->parm_modified) return false; - gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE); - ao_ref_init (&refd, parm_load); - /* We can cache visited statements only when parm_ainfo is available and when - we are looking at a naked load of the whole parameter. */ - if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL) - visited_stmts = NULL; + if (optimize) + { + gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE); + ao_ref_init (&refd, parm_load); + /* We can cache visited statements only when parm_ainfo is available and + when we are looking at a naked load of the whole parameter. */ + if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL) + visited_stmts = NULL; + else + visited_stmts = &parm_ainfo->parm_visited_statements; + walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified, + visited_stmts); + } else - visited_stmts = &parm_ainfo->parm_visited_statements; - walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified, - visited_stmts); + modified = true; + if (parm_ainfo && modified) parm_ainfo->parm_modified = true; return !modified; @@ -1466,6 +1472,9 @@ ipa_compute_jump_functions (struct cgraph_node *node, { struct cgraph_edge *cs; + if (!optimize) + return; + for (cs = node->callees; cs; cs = cs->next_callee) { struct cgraph_node *callee = cgraph_function_or_thunk_node (cs->callee, @@ -1851,8 +1860,7 @@ ipa_analyze_stmt_uses (struct cgraph_node *node, struct ipa_node_params *info, passed in DATA. */ static bool -visit_ref_for_mod_analysis (gimple stmt ATTRIBUTE_UNUSED, - tree op, void *data) +visit_ref_for_mod_analysis (gimple, tree op, tree, void *data) { struct ipa_node_params *info = (struct ipa_node_params *) data; diff --git a/gcc-4_8-branch/gcc/ipa-pure-const.c b/gcc-4_8-branch/gcc/ipa-pure-const.c index 94c7315c124..bedc28a8c39 100644 --- a/gcc-4_8-branch/gcc/ipa-pure-const.c +++ b/gcc-4_8-branch/gcc/ipa-pure-const.c @@ -588,7 +588,7 @@ check_call (funct_state local, gimple call, bool ipa) /* Wrapper around check_decl for loads in local more. */ static bool -check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_load (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, false, false); @@ -600,7 +600,7 @@ check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) /* Wrapper around check_decl for stores in local more. */ static bool -check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_store (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, true, false); @@ -612,7 +612,7 @@ check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) /* Wrapper around check_decl for loads in ipa mode. */ static bool -check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_ipa_load (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, false, true); @@ -624,7 +624,7 @@ check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) /* Wrapper around check_decl for stores in ipa mode. */ static bool -check_ipa_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_ipa_store (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, true, true); diff --git a/gcc-4_8-branch/gcc/ipa-split.c b/gcc-4_8-branch/gcc/ipa-split.c index e7d469d7442..f18ce82fef7 100644 --- a/gcc-4_8-branch/gcc/ipa-split.c +++ b/gcc-4_8-branch/gcc/ipa-split.c @@ -136,7 +136,7 @@ static tree find_retval (basic_block return_bb); variable, check it if it is present in bitmap passed via DATA. */ static bool -test_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data) +test_nonssa_use (gimple, tree t, tree, void *data) { t = get_base_address (t); @@ -229,7 +229,7 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, } if (gimple_code (stmt) == GIMPLE_LABEL && test_nonssa_use (stmt, gimple_label_label (stmt), - non_ssa_vars)) + NULL_TREE, non_ssa_vars)) { ok = false; goto done; @@ -258,7 +258,7 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, if (virtual_operand_p (gimple_phi_result (stmt))) continue; if (TREE_CODE (op) != SSA_NAME - && test_nonssa_use (stmt, op, non_ssa_vars)) + && test_nonssa_use (stmt, op, op, non_ssa_vars)) { ok = false; goto done; @@ -670,7 +670,7 @@ find_retval (basic_block return_bb) Return true when access to T prevents splitting the function. */ static bool -mark_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data) +mark_nonssa_use (gimple, tree t, tree, void *data) { t = get_base_address (t); @@ -830,7 +830,7 @@ visit_bb (basic_block bb, basic_block return_bb, if (TREE_CODE (op) == SSA_NAME) bitmap_set_bit (used_ssa_names, SSA_NAME_VERSION (op)); else - can_split &= !mark_nonssa_use (stmt, op, non_ssa_vars); + can_split &= !mark_nonssa_use (stmt, op, op, non_ssa_vars); } } return can_split; diff --git a/gcc-4_8-branch/gcc/ira.c b/gcc-4_8-branch/gcc/ira.c index 9e16465e44a..87e72f067c8 100644 --- a/gcc-4_8-branch/gcc/ira.c +++ b/gcc-4_8-branch/gcc/ira.c @@ -4742,6 +4742,18 @@ do_reload (void) if (need_dce && optimize) run_fast_dce (); + /* Diagnose uses of the hard frame pointer when it is used as a global + register. Often we can get away with letting the user appropriate + the frame pointer, but we should let them know when code generation + makes that impossible. */ + if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) + { + tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; + error_at (DECL_SOURCE_LOCATION (current_function_decl), + "frame pointer required, but reserved"); + inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); + } + timevar_pop (TV_IRA); } diff --git a/gcc-4_8-branch/gcc/optabs.c b/gcc-4_8-branch/gcc/optabs.c index 77d131ffa96..afb9b5f6971 100644 --- a/gcc-4_8-branch/gcc/optabs.c +++ b/gcc-4_8-branch/gcc/optabs.c @@ -6238,7 +6238,7 @@ init_tree_optimization_optabs (tree optnode) /* If the optabs changed, record it. */ if (memcmp (tmp_optabs, this_target_optabs, sizeof (struct target_optabs))) - TREE_OPTIMIZATION_OPTABS (optnode) = (unsigned char *) tmp_optabs; + TREE_OPTIMIZATION_OPTABS (optnode) = tmp_optabs; else { TREE_OPTIMIZATION_OPTABS (optnode) = NULL; diff --git a/gcc-4_8-branch/gcc/passes.c b/gcc-4_8-branch/gcc/passes.c index 61f8a118a82..22d843aa5e8 100644 --- a/gcc-4_8-branch/gcc/passes.c +++ b/gcc-4_8-branch/gcc/passes.c @@ -1398,6 +1398,7 @@ init_optimization_passes (void) /* After CCP we rewrite no longer addressed locals into SSA form if possible. */ NEXT_PASS (pass_forwprop); + NEXT_PASS (pass_object_sizes); /* pass_build_alias is a dummy pass that ensures that we execute TODO_rebuild_alias at this point. */ NEXT_PASS (pass_build_alias); @@ -1435,7 +1436,6 @@ init_optimization_passes (void) NEXT_PASS (pass_dce); NEXT_PASS (pass_forwprop); NEXT_PASS (pass_phiopt); - NEXT_PASS (pass_object_sizes); NEXT_PASS (pass_strlen); NEXT_PASS (pass_ccp); /* After CCP we rewrite no longer addressed locals into SSA diff --git a/gcc-4_8-branch/gcc/regcprop.c b/gcc-4_8-branch/gcc/regcprop.c index 896902f3012..8bfb64e40cb 100644 --- a/gcc-4_8-branch/gcc/regcprop.c +++ b/gcc-4_8-branch/gcc/regcprop.c @@ -747,6 +747,7 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) int n_ops, i, alt, predicated; bool is_asm, any_replacements; rtx set; + rtx link; bool replaced[MAX_RECOG_OPERANDS]; bool changed = false; struct kill_set_value_data ksvd; @@ -815,6 +816,23 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) if (recog_op_alt[i][alt].earlyclobber) kill_value (recog_data.operand[i], vd); + /* If we have dead sets in the insn, then we need to note these as we + would clobbers. */ + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + { + if (REG_NOTE_KIND (link) == REG_UNUSED) + { + kill_value (XEXP (link, 0), vd); + /* Furthermore, if the insn looked like a single-set, + but the dead store kills the source value of that + set, then we can no-longer use the plain move + special case below. */ + if (set + && reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set))) + set = NULL; + } + } + /* Special-case plain move instructions, since we may well be able to do the move from a different register class. */ if (set && REG_P (SET_SRC (set))) diff --git a/gcc-4_8-branch/gcc/reginfo.c b/gcc-4_8-branch/gcc/reginfo.c index 0153cd9d8ec..3d08a9a7080 100644 --- a/gcc-4_8-branch/gcc/reginfo.c +++ b/gcc-4_8-branch/gcc/reginfo.c @@ -85,7 +85,7 @@ static const char initial_call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; char global_regs[FIRST_PSEUDO_REGISTER]; /* Declaration for the global register. */ -static tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER]; +tree global_regs_decl[FIRST_PSEUDO_REGISTER]; /* Same information as REGS_INVALIDATED_BY_CALL but in regset form to be used in dataflow more conveniently. */ @@ -620,40 +620,35 @@ choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; - if (found_mode != VOIDmode) - return found_mode; - for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; - if (found_mode != VOIDmode) - return found_mode; - for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; - if (found_mode != VOIDmode) - return found_mode; - for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; if (found_mode != VOIDmode) diff --git a/gcc-4_8-branch/gcc/reorg.c b/gcc-4_8-branch/gcc/reorg.c index c19fb4c4262..e7cb112b483 100644 --- a/gcc-4_8-branch/gcc/reorg.c +++ b/gcc-4_8-branch/gcc/reorg.c @@ -1105,6 +1105,7 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, int used_annul = 0; int i; struct resources cc_set; + bool *redundant; /* We can't do anything if there are more delay slots in SEQ than we can handle, or if we don't know that it will be a taken branch. @@ -1145,6 +1146,7 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, return delay_list; #endif + redundant = XALLOCAVEC (bool, XVECLEN (seq, 0)); for (i = 1; i < XVECLEN (seq, 0); i++) { rtx trial = XVECEXP (seq, 0, i); @@ -1166,7 +1168,8 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, /* If this insn was already done (usually in a previous delay slot), pretend we put it in our delay slot. */ - if (redundant_insn (trial, insn, new_delay_list)) + redundant[i] = redundant_insn (trial, insn, new_delay_list); + if (redundant[i]) continue; /* We will end up re-vectoring this branch, so compute flags @@ -1199,6 +1202,12 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, return delay_list; } + /* Record the effect of the instructions that were redundant and which + we therefore decided not to copy. */ + for (i = 1; i < XVECLEN (seq, 0); i++) + if (redundant[i]) + update_block (XVECEXP (seq, 0, i), insn); + /* Show the place to which we will be branching. */ *pnew_thread = first_active_target_insn (JUMP_LABEL (XVECEXP (seq, 0, 0))); @@ -1262,6 +1271,7 @@ steal_delay_list_from_fallthrough (rtx insn, rtx condition, rtx seq, /* If this insn was already done, we don't need it. */ if (redundant_insn (trial, insn, delay_list)) { + update_block (trial, insn); delete_from_delay_slot (trial); continue; } @@ -3266,6 +3276,7 @@ relax_delay_slots (rtx first) to reprocess this insn. */ if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0)) { + update_block (XVECEXP (pat, 0, 1), insn); delete_from_delay_slot (XVECEXP (pat, 0, 1)); next = prev_active_insn (next); continue; @@ -3385,6 +3396,7 @@ relax_delay_slots (rtx first) && redirect_with_delay_slots_safe_p (delay_insn, target_label, insn)) { + update_block (XVECEXP (PATTERN (trial), 0, 1), insn); reorg_redirect_jump (delay_insn, target_label); next = insn; continue; diff --git a/gcc-4_8-branch/gcc/rtl.h b/gcc-4_8-branch/gcc/rtl.h index 93a64f4d832..a86034eada6 100644 --- a/gcc-4_8-branch/gcc/rtl.h +++ b/gcc-4_8-branch/gcc/rtl.h @@ -2789,6 +2789,8 @@ extern void _fatal_insn (const char *, const_rtx, const char *, int, const char #define fatal_insn_not_found(insn) \ _fatal_insn_not_found (insn, __FILE__, __LINE__, __FUNCTION__) +/* reginfo.c */ +extern tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER]; #endif /* ! GCC_RTL_H */ diff --git a/gcc-4_8-branch/gcc/sel-sched.c b/gcc-4_8-branch/gcc/sel-sched.c index 11bf2e62c31..71a01146cf6 100644 --- a/gcc-4_8-branch/gcc/sel-sched.c +++ b/gcc-4_8-branch/gcc/sel-sched.c @@ -1253,7 +1253,7 @@ mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p, if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) add_to_hard_reg_set (®_rename_p->unavailable_hard_regs, - Pmode, HARD_FRAME_POINTER_IS_FRAME_POINTER); + Pmode, HARD_FRAME_POINTER_REGNUM); } #ifdef STACK_REGS diff --git a/gcc-4_8-branch/gcc/testsuite/ChangeLog b/gcc-4_8-branch/gcc/testsuite/ChangeLog index 89642447ffa..10ada5e10d4 100644 --- a/gcc-4_8-branch/gcc/testsuite/ChangeLog +++ b/gcc-4_8-branch/gcc/testsuite/ChangeLog @@ -1,3 +1,237 @@ +2014-02-01 Paul Thomas + + PR fortran/59414 + * gfortran.dg/allocate_class_3.f90 : New test + +2014-01-30 David Holsgrove + + Backport from mainline. + * gcc.target/microblaze/isa/fcmp4.c: New. + +2014-01-26 Mikael Morin + + PR fortran/58007 + * gfortran.dg/unresolved_fixup_1.f90: New test. + * gfortran.dg/unresolved_fixup_2.f90: New test. + +2014-01-24 H.J. Lu + + Backport from mainline. + 2014-01-23 H.J. Lu + + PR target/59929 + * gcc.target/i386/pr59929.c: New test. + +2014-01-24 Paolo Carlini + + PR c++/57524 + * g++.dg/ext/timevar2.C: New. + +2014-01-23 David Holsgrove + + Backport from mainline. + * gcc.target/microblaze/others/builtin-trap.c: New test. + +2014-01-23 Marek Polacek + + Backport from mainline + 2013-10-21 Marek Polacek + + PR middle-end/58809 + * gcc.dg/gomp/pr58809.c: New test. + +2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * c-c++-common/gomp/pr58809.c: New test. + +2014-01-22 Marek Polacek + + Backport from mainline + 2014-01-22 Marek Polacek + + PR c/59891 + * gcc.dg/torture/pr59891.c: New test. + +2014-01-21 Jakub Jelinek + + PR middle-end/59860 + * gcc.dg/strlenopt-4.c: Expect the same counts on s390*-* as on all + other targets. + +2014-01-20 Richard Biener + + PR middle-end/59860 + * gcc.dg/pr59860.c: New testcase. + +2014-01-20 Marek Polacek + + Backported from mainline + 2014-01-17 Marek Polacek + + PR c++/59838 + * g++.dg/diagnostic/pr59838.C: New test. + +2014-01-19 Paul Thomas + + Backport from mainline + 2013-12-01 Paul Thomas + + PR fortran/34547 + * gfortran.dg/null_5.f90 : Include new error. + * gfortran.dg/null_6.f90 : Include new error. + +2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-15 H.J. Lu + + PR target/59794 + * c-c++-common/convert-vec-1.c: Also prune ABI change for + Linux/x86. + * g++.dg/cpp0x/constexpr-53094-2.C: Likewise. + * g++.dg/ext/attribute-test-1.C: Likewise. + * g++.dg/ext/attribute-test-2.C: Likewise. + * g++.dg/ext/attribute-test-3.C: Likewise. + * g++.dg/ext/attribute-test-4.C: Likewise. + * g++.dg/torture/pr38565.C: Likewise. + * gcc.dg/pr53060.c: Likewise. + * c-c++-common/scal-to-vec2.c: Add -msse2 for x86. + * c-c++-common/vector-compare-2.c: Likewise. + * gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c: Likewise. + * g++.dg/conversion/simd1.C: Add -msse2 for x86. Adjust + dg-message line number. + +2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-14 H.J. Lu + + PR target/59794 + * gcc.target/i386/pr39162.c (y): New __m256i variable. + (bar): Change return type to void. Set y to x. + * gcc.target/i386/pr59794-1.c: New testcase. + * gcc.target/i386/pr59794-2.c: Likewise. + * gcc.target/i386/pr59794-3.c: Likewise. + * gcc.target/i386/pr59794-4.c: Likewise. + * gcc.target/i386/pr59794-5.c: Likewise. + * gcc.target/i386/pr59794-6.c: Likewise. + * gcc.target/i386/pr59794-7.c: Likewise. + +2014-01-17 Matthias Klose + + Backport from the trunk: + 2014-01-09 Uros Bizjak + * go.test/go-test.exp (go-gc-tests): Don't run peano.go on systems + which don't support -fsplit-stack. Skip rotate[0123].go tests. + +2014-01-15 Kugan Vivekanandarajah + + Backport from mainline + 2014-01-15 Matthew Gretton-Dann + Kugan Vivekanandarajah + + PR target/59695 + * g++.dg/pr59695.C: New testcase. + +2014-01-17 Terry Guo + + * gcc.target/arm/pr59826.c: New test. + +2014-01-16 Jakub Jelinek + + PR target/59839 + * gcc.target/i386/pr59839.c: New test. + + PR debug/54694 + * gcc.target/i386/pr9771-1.c (main): Rename to... + (real_main): ... this. Add __asm name "main". + (ASMNAME, ASMNAME2, STRING): Define. + +2014-01-16 Marek Polacek + + Backported from mainline + 2014-01-16 Marek Polacek + + PR middle-end/59827 + * gcc.dg/pr59827.c: New test. + +2014-01-15 Andreas Krebbel + + PR target/59803 + * gcc.c-torture/compile/pr59803.c: New testcase. + +2014-01-10 Yufeng Zhang + + * gcc.target/arm/neon/vst1Q_laneu64-1.c: New test. + +2014-01-10 Hans-Peter Nilsson + + * gcc.dg/pr46309.c: Disable for cris*-*-*. + +2014-01-10 Paolo Carlini + + PR c++/56060 + PR c++/59730 + * g++.dg/cpp0x/variadic144.C: New. + * g++.dg/cpp0x/variadic145.C: Likewise. + +2014-01-10 Richard Biener + + PR tree-optimization/59715 + * gcc.dg/torture/pr59715.c: New testcase. + +2014-01-09 Richard Sandiford + + * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c, + gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c, + gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests. + +2014-01-09 Richard Sandiford + + PR rtl-optimization/59137 + * gcc.target/mips/pr59137.c: New test. + +2014-01-09 Richard Biener + + Backport from mainline + 2013-11-18 Richard Biener + + PR tree-optimization/59125 + PR tree-optimization/54570 + * gcc.dg/builtin-object-size-8.c: Un-xfail. + * gcc.dg/builtin-object-size-14.c: New testcase. + * gcc.dg/strlenopt-14gf.c: Adjust. + * gcc.dg/strlenopt-1f.c: Likewise. + * gcc.dg/strlenopt-4gf.c: Likewise. + + 2013-12-03 Jakub Jelinek + + PR tree-optimization/59362 + * gcc.c-torture/compile/pr59362.c: New test. + +2014-01-09 Richard Earnshaw + + PR rtl-optimization/54300 + * gcc.target/arm/pr54300.C: New test. + +2014-01-08 Martin Jambor + + PR ipa/59610 + * gcc.dg/ipa/pr59610.c: New test. + +2014-01-07 Jakub Jelinek + + PR rtl-optimization/58668 + * gcc.dg/pr58668.c: New test. + + Backported from mainline + 2013-12-16 Jakub Jelinek + + PR middle-end/58956 + PR middle-end/59470 + * gcc.target/i386/pr59470.c: New test. + 2014-01-04 Janus Weil Backport from mainline diff --git a/gcc-4_8-branch/gcc/testsuite/c-c++-common/convert-vec-1.c b/gcc-4_8-branch/gcc/testsuite/c-c++-common/convert-vec-1.c index 49872984073..862190d6092 100644 --- a/gcc-4_8-branch/gcc/testsuite/c-c++-common/convert-vec-1.c +++ b/gcc-4_8-branch/gcc/testsuite/c-c++-common/convert-vec-1.c @@ -1,3 +1,4 @@ /* { dg-do compile } */ +/* { dg-prune-output "changes the ABI" } */ typedef float v2sf __attribute__ ((vector_size (8))); v2sf sub (void) { return (v2sf) 0.0; } /* { dg-error "can't convert" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/c-c++-common/gomp/pr58809.c b/gcc-4_8-branch/gcc/testsuite/c-c++-common/gomp/pr58809.c new file mode 100644 index 00000000000..d1ea51b9971 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/c-c++-common/gomp/pr58809.c @@ -0,0 +1,31 @@ +/* PR middle-end/58809 */ +/* { dg-do compile } */ +/* { dg-options "-fopenmp" } */ + +_Complex int j; +_Complex double d; + +void +foo (void) +{ + #pragma omp parallel reduction (&:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (|:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (^:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (min:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (max:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (&:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (|:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (^:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (min:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (max:d) /* { dg-error "has invalid type for" } */ + ; +} diff --git a/gcc-4_8-branch/gcc/testsuite/c-c++-common/scal-to-vec2.c b/gcc-4_8-branch/gcc/testsuite/c-c++-common/scal-to-vec2.c index 2721aa00794..e2c93eedd6c 100644 --- a/gcc-4_8-branch/gcc/testsuite/c-c++-common/scal-to-vec2.c +++ b/gcc-4_8-branch/gcc/testsuite/c-c++-common/scal-to-vec2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-fno-common" { target hppa*-*-hpux* } } */ /* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */ +/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */ /* Ignore warning on some powerpc-ibm-aix configurations. */ /* { dg-prune-output "non-standard ABI extension" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/c-c++-common/vector-compare-2.c b/gcc-4_8-branch/gcc/testsuite/c-c++-common/vector-compare-2.c index d17a1b41284..5ebe9e3ca56 100644 --- a/gcc-4_8-branch/gcc/testsuite/c-c++-common/vector-compare-2.c +++ b/gcc-4_8-branch/gcc/testsuite/c-c++-common/vector-compare-2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-fno-common" { target hppa*-*-hpux* } } */ /* { dg-options "-mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */ +/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */ /* Ignore warning on some powerpc-ibm-aix configurations. */ /* { dg-prune-output "non-standard ABI extension" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/conversion/simd1.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/conversion/simd1.C index fa40b0eaad2..522d8b5470a 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/conversion/simd1.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/conversion/simd1.C @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-msse2" { target { i?86-*-* x86_64-*-* } } } */ /* Test overload resolution of vector types. From Janis Johnson and Paolo Bonzini, based on PR/16882 */ @@ -17,7 +18,7 @@ extern const vector signed short *cvssp; void foo () { vss = vld(i, vscp); /* { dg-error "no matching function for call" } */ - // { dg-message "candidate" "candidate note" { target *-*-* } 19 } + // { dg-message "candidate" "candidate note" { target *-*-* } 20 } vss = vld(i, vssp); vss = vld(i, cvssp); } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C index 3f66c4eb74b..1c5129dcb3f 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/constexpr-53094-2.C @@ -2,6 +2,7 @@ // { dg-options "-std=gnu++11" } // Ignore warning on some powerpc-ibm-aix configurations. // { dg-prune-output "non-standard ABI extension" } +// { dg-prune-output "changes the ABI" } typedef float __attribute__ ((vector_size (4 * sizeof (float)))) V4; constexpr V4 build (float x, float y, float z) { return (V4){ x, y, z, 0 };} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist76.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist76.C new file mode 100644 index 00000000000..ac419dde8cf --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist76.C @@ -0,0 +1,5 @@ +// PR c++/58812 +// { dg-require-effective-target c++11 } + +int i; +int&& j{{ i }}; // { dg-error "too many braces" } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist78.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist78.C new file mode 100644 index 00000000000..648ec5307df --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist78.C @@ -0,0 +1,12 @@ +// PR c++/58639 +// { dg-require-effective-target c++11 } + +struct node { + node &parent; +}; + +struct vector { + node n; +}; + +vector v({}); // { dg-error "" } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist79.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist79.C new file mode 100644 index 00000000000..5a1914dda67 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/initlist79.C @@ -0,0 +1,8 @@ +// PR c++/59646 +// { dg-require-effective-target c++11 } + +#include + +struct A {}; + +std::initializer_list x = {{}}; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C new file mode 100644 index 00000000000..35f6509df78 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C @@ -0,0 +1,10 @@ +// PR c++/58965 +// { dg-require-effective-target c++11 } + +void foo() +{ + static union + { + int i = i; + }; +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/static_assert9.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/static_assert9.C new file mode 100644 index 00000000000..fccaa449c17 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/static_assert9.C @@ -0,0 +1,7 @@ +// PR c++/58837 +// { dg-require-effective-target c++11 } + +void f(); +static_assert(f, ""); +struct A {}; +static_assert(A::~A, ""); // { dg-error "non-static member function" } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic144.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic144.C new file mode 100644 index 00000000000..5d05d3d52bd --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic144.C @@ -0,0 +1,15 @@ +// PR c++/56060 +// { dg-do compile { target c++11 } } + +template struct baz { }; +template T bar(); + +template +baz()(bar ...))> // { dg-error "cannot be used" } +foo(); + +int main() +{ + foo(); // { dg-error "no matching" } + return 0; +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic145.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic145.C new file mode 100644 index 00000000000..65edda59fd8 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic145.C @@ -0,0 +1,13 @@ +// PR c++/59730 +// { dg-do compile { target c++11 } } + +template void declval(); +template void forward(); +template class D; +template +class D <_Functor(_Bound_args...)> { + template )> + void operator()(...) { + 0(forward<_Args>...); + } +}; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic146.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic146.C new file mode 100644 index 00000000000..0c91db581d1 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic146.C @@ -0,0 +1,9 @@ +// PR c++/58606 +// { dg-require-effective-target c++11 } + +template struct A +{ + template struct B; + + template struct B {}; +}; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic147.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic147.C new file mode 100644 index 00000000000..7f606d84a1e --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic147.C @@ -0,0 +1,10 @@ +// PR c++/58466 +// { dg-require-effective-target c++11 } + +template struct A; + +template struct B; + +template struct B> {}; + +B> b; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic148.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic148.C new file mode 100644 index 00000000000..a4ee63533da --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/cpp0x/variadic148.C @@ -0,0 +1,6 @@ +// PR c++/59989 +// { dg-require-effective-target c++11 } + +template struct X {}; +template class D, typename ...U> int test(D*); +int n = test(0); // { dg-error "no match" } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/diagnostic/pr59838.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/diagnostic/pr59838.C new file mode 100644 index 00000000000..d1cf2c7fa58 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/diagnostic/pr59838.C @@ -0,0 +1,4 @@ +// PR c++/59838 +// { dg-do compile } + +enum E { a, b = (E) a }; // { dg-error "conversion to incomplete type" } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught1.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught1.C index afbf5af4d22..e96af334a8c 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught1.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught1.C @@ -13,7 +13,7 @@ struct Check { static Check const data[] = { { 0, 0, false }, // construct [0] - { 1, 0, true }, // [1] = [0] + { 1, 0, false }, // [1] = [0] { 0, 0, true }, // destruct [0] { 2, 1, true }, // [2] = [1] { 2, 2, true }, // destruct [2] diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught4.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught4.C new file mode 100644 index 00000000000..227d11b330b --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/eh/uncaught4.C @@ -0,0 +1,29 @@ +// PR c++/41174 +// { dg-do run } + +#include + +#define assert(E) if (!(E)) __builtin_abort(); + +struct e { + e() + { + assert( !std::uncaught_exception() ); + try { + throw 1; + } catch (int i) { + assert( !std::uncaught_exception() ); + throw; + } + } +}; + +int main() +{ + try { + throw e(); + } catch (int i) { + assert( !std::uncaught_exception() ); + } + assert( !std::uncaught_exception() ); +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attrib48.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attrib48.C new file mode 100644 index 00000000000..19a9959109d --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attrib48.C @@ -0,0 +1,6 @@ +// PR c++/54652 + +typedef unsigned L __attribute__ ((aligned)); +typedef unsigned L __attribute__ ((aligned)); + +L l; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-1.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-1.C index 7df68930fc4..93e08d7ef89 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-1.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-1.C @@ -36,3 +36,4 @@ int main() /* Ignore a warning that is irrelevant to the purpose of this test. */ /* { dg-prune-output ".*GCC vector returned by reference.*" } */ +/* { dg-prune-output "changes the ABI" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-2.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-2.C index 187067318f9..d7c417dccaa 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-2.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-2.C @@ -50,3 +50,4 @@ int main() /* Ignore a warning that is irrelevant to the purpose of this test. */ /* { dg-prune-output ".*GCC vector returned by reference.*" } */ +/* { dg-prune-output "changes the ABI" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-3.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-3.C index 050cbb4ed39..4b0939ea3a2 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-3.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-3.C @@ -52,3 +52,4 @@ int main() { /* Ignore a warning that is irrelevant to the purpose of this test. */ /* { dg-prune-output ".*GCC vector returned by reference.*" } */ +/* { dg-prune-output "changes the ABI" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-4.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-4.C index 4783ee8a406..c3e949a9bde 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-4.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/attribute-test-4.C @@ -49,3 +49,4 @@ int main() { /* Ignore a warning that is irrelevant to the purpose of this test. */ /* { dg-prune-output ".*GCC vector returned by reference.*" } */ +/* { dg-prune-output "changes the ABI" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/stmtexpr15.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/stmtexpr15.C new file mode 100644 index 00000000000..83a831cdd4c --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/stmtexpr15.C @@ -0,0 +1,7 @@ +// PR c++/59097 +// { dg-options "" } + +void foo() +{ + int x[({ return; })]; // { dg-error "non-integral" } +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/timevar2.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/timevar2.C new file mode 100644 index 00000000000..74c4fc8cfae --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/timevar2.C @@ -0,0 +1,14 @@ +// PR c++/57524 +// { dg-options "-ftime-report" } +// { dg-prune-output "wall" } +// { dg-prune-output "times" } +// { dg-prune-output "TOTAL" } +// { dg-prune-output "checks" } + +namespace detail { +namespace indirect_traits {} +using namespace indirect_traits; +void fn1() { +using namespace detail; +} +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/traits1.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/traits1.C new file mode 100644 index 00000000000..24099e53cd7 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/traits1.C @@ -0,0 +1,4 @@ +// PR c++/58504 + +template struct A {}; +A<> a; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/vector25.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/vector25.C new file mode 100644 index 00000000000..6c1f5d09878 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/ext/vector25.C @@ -0,0 +1,6 @@ +volatile int i __attribute__((vector_size(8))); + +void foo() +{ + i += i; +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/pr59695.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/pr59695.C new file mode 100644 index 00000000000..ac636d06f0a --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/pr59695.C @@ -0,0 +1,125 @@ + +/* PR target/59695 */ +/* { dg-do run } */ +/* { dg-options "-O0" } */ + +#define DEFINE_VIRTUALS_FNS(i) virtual void xxx##i () {} \ + virtual void foo1_##i () {}\ + virtual void foo2_##i () {}\ + virtual void foo3_##i () {}\ + virtual void foo4_##i () {}\ + virtual void foo5_##i () {}\ + virtual void foo6_##i () {}\ + virtual void foo7_##i () {}\ + virtual void foo8_##i () {}\ + virtual void foo9_##i () {}\ + virtual void foo10_##i () {}\ + virtual void foo11_##i () {}\ + virtual void foo12_##i () {}\ + virtual void foo13_##i () {}\ + virtual void foo14_##i () {}\ + virtual void foo15_##i () {}\ + virtual void foo16_##i () {}\ + virtual void foo17_##i () {}\ + virtual void foo18_##i () {}\ + virtual void foo19_##i () {}\ + virtual void foo20_##i () {}\ + virtual void foo21_##i () {}\ + virtual void foo22_##i () {}\ + +class base_class_2 +{ + +public: + /* Define lots of virtual functions */ + DEFINE_VIRTUALS_FNS (1) + DEFINE_VIRTUALS_FNS (2) + DEFINE_VIRTUALS_FNS (3) + DEFINE_VIRTUALS_FNS (4) + DEFINE_VIRTUALS_FNS (5) + DEFINE_VIRTUALS_FNS (6) + DEFINE_VIRTUALS_FNS (7) + DEFINE_VIRTUALS_FNS (8) + DEFINE_VIRTUALS_FNS (9) + DEFINE_VIRTUALS_FNS (10) + DEFINE_VIRTUALS_FNS (11) + DEFINE_VIRTUALS_FNS (12) + DEFINE_VIRTUALS_FNS (13) + DEFINE_VIRTUALS_FNS (14) + DEFINE_VIRTUALS_FNS (15) + DEFINE_VIRTUALS_FNS (16) + DEFINE_VIRTUALS_FNS (17) + DEFINE_VIRTUALS_FNS (18) + DEFINE_VIRTUALS_FNS (19) + DEFINE_VIRTUALS_FNS (20) + + base_class_2(); + virtual ~base_class_2 (); +}; + +base_class_2::base_class_2() +{ +} + +base_class_2::~base_class_2 () +{ +} + +class base_class_1 +{ +public: + virtual ~base_class_1(); + base_class_1(); +}; + +base_class_1::base_class_1() +{ +} + +base_class_1::~base_class_1() +{ +} + +class base_Impl_class : + virtual public base_class_2, public base_class_1 +{ +public: + base_Impl_class (); + virtual ~base_Impl_class (); +}; + +base_Impl_class::base_Impl_class () +{ +} + +base_Impl_class::~base_Impl_class () +{ +} + + +class test_cls : public base_Impl_class +{ +public: + test_cls(); + virtual ~test_cls(); +}; + +test_cls::test_cls() +{ +} + +test_cls::~test_cls() +{ +} + +int main() +{ + test_cls *test = new test_cls; + base_class_2 *p1 = test; + + /* PR59695 destructor thunk offsets are not setup + correctly resulting in crash. */ + delete p1; + return 0; +} + diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/template/partial15.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/template/partial15.C new file mode 100644 index 00000000000..357bb05fa3b --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/template/partial15.C @@ -0,0 +1,19 @@ +// PR c++/57043 +// { dg-do link } + +template struct complex { }; + +template +complex +pow(const complex& x, const complex& y) { return complex(); } + +template +struct promote_2 { typedef T type; }; + +template +complex::type> +pow(const complex& x, const complex& y); + +complex (*powcc)(const complex&, const complex&) = pow; + +int main() {} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/template/shadow1.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/template/shadow1.C new file mode 100644 index 00000000000..6eb30d0945b --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/template/shadow1.C @@ -0,0 +1,4 @@ +// PR c++/58632 + +template class A> // { dg-message "shadows" } +class A {}; // { dg-error "declaration" } diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/tls/thread_local-ice2.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/tls/thread_local-ice2.C new file mode 100644 index 00000000000..53bc2978093 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/tls/thread_local-ice2.C @@ -0,0 +1,11 @@ +// PR c++/58672 +// { dg-options "-std=c++11" } +// { dg-require-effective-target tls } + +struct A +{ + A(int); + i; // { dg-error "" } +}; + +thread_local A a(0); diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/tls/thread_local8.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/tls/thread_local8.C new file mode 100644 index 00000000000..9b91a6b9a61 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/tls/thread_local8.C @@ -0,0 +1,12 @@ +// PR c++/55800 +// { dg-options "-std=c++11" } +// { dg-require-alias "" } +// { dg-require-effective-target tls } +// { dg-final { scan-assembler "_ZTH12foo_instance" { target tls_native } } } + +struct foo +{ + foo(); +}; + +thread_local foo foo_instance; diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/tm/pr60004.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/tm/pr60004.C new file mode 100644 index 00000000000..b8c2c0e032b --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/tm/pr60004.C @@ -0,0 +1,10 @@ +// { dg-do compile } +// { dg-options "-fgnu-tm" } + +int a; +int f() { + __transaction_atomic { + if (a == 5) + return 1; + } +} diff --git a/gcc-4_8-branch/gcc/testsuite/g++.dg/torture/pr38565.C b/gcc-4_8-branch/gcc/testsuite/g++.dg/torture/pr38565.C index 8cd1e1d4b9b..7216b1c67e7 100644 --- a/gcc-4_8-branch/gcc/testsuite/g++.dg/torture/pr38565.C +++ b/gcc-4_8-branch/gcc/testsuite/g++.dg/torture/pr38565.C @@ -1,6 +1,7 @@ // { dg-do compile } // Ignore warning on some powerpc-linux configurations. // { dg-prune-output "non-standard ABI extension" } +// { dg-prune-output "changes the ABI" } #define vector __attribute__((vector_size(16) )) vector unsigned int f(int a) { diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/compile/pr59362.c b/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/compile/pr59362.c new file mode 100644 index 00000000000..3e78f76bc5f --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/compile/pr59362.c @@ -0,0 +1,21 @@ +/* PR tree-optimization/59362 */ + +char * +foo (char *r, int s) +{ + r = __builtin___stpcpy_chk (r, "abc", __builtin_object_size (r, 1)); + if (s) + r = __builtin___stpcpy_chk (r, "d", __builtin_object_size (r, 1)); + return r; +} + +char *a; +long int b; + +void +bar (void) +{ + b = __builtin_object_size (0, 0); + a = __builtin___stpcpy_chk (0, "", b); + b = __builtin_object_size (a, 0); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/compile/pr59803.c b/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/compile/pr59803.c new file mode 100644 index 00000000000..d2b5d2098f5 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.c-torture/compile/pr59803.c @@ -0,0 +1,27 @@ +/* PR target/59803 */ + +extern void baz (void) __attribute__ ((__noreturn__)); +struct A { int g, h; }; +extern struct A a; +struct B { unsigned char i, j, k, l, m; }; +int c, d, e; +static int f; + +void +foo (void) +{ + f = 1; +} + +void +bar (struct B *x) +{ + x->i = e; + x->k = c; + x->l = d; + x->j = a.h; + x->m = f; + if (x->i != e) baz (); + if (x->k != c) baz (); + if (x->j != a.h) baz (); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c index 42b393580a3..b1bee33c382 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Wall" } */ /* { dg-options "-O2 -Wall -mabi=altivec" { target { { powerpc*-*-linux* } && ilp32 } } } */ +/* { dg-options "-O2 -Wall -msse2" { target { i?86-*-* x86_64-*-* } } } */ typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-14.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-14.c new file mode 100644 index 00000000000..085011eda52 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-14.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); +extern char *strncpy(char *, const char *, __SIZE_TYPE__); + +union u { + struct { + char vi[8]; + char pi[16]; + }; + char all[8+16+4]; +}; + +void __attribute__((noinline,noclone)) +f(union u *u) +{ + char vi[8+1]; + __builtin_strncpy(vi, u->vi, sizeof(u->vi)); + if (__builtin_object_size (u->all, 1) != -1) + abort (); +} +int main() +{ + union u u; + f (&u); + return 0; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-8.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-8.c index 7af64d3ab7a..f2d88f9d591 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-8.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/builtin-object-size-8.c @@ -1,4 +1,4 @@ -/* { dg-do run { xfail *-*-* } } */ +/* { dg-do run } */ /* { dg-options "-O2" } */ typedef __SIZE_TYPE__ size_t; diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/gomp/pr58809.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/gomp/pr58809.c new file mode 100644 index 00000000000..5dc02f65aa8 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/gomp/pr58809.c @@ -0,0 +1,13 @@ +/* PR middle-end/58809 */ +/* { dg-do compile } */ +/* { dg-options "-fopenmp -O" } */ + +int i; +#pragma omp threadprivate (i) + +void foo() +{ + _Complex int j; +#pragma omp parallel copyin (i) reduction (&&:j) + ; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/ipa/pr59610.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/ipa/pr59610.c new file mode 100644 index 00000000000..fc0933441e8 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/ipa/pr59610.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct A { int a; }; +extern void *y; + +__attribute__((optimize (0))) void +foo (void *p, struct A x) +{ + foo (y, x); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr46309.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr46309.c index ee154ccd2f3..9275015049e 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr46309.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr46309.c @@ -1,5 +1,5 @@ /* PR tree-optimization/46309 */ -/* { dg-do compile } */ +/* { dg-do compile { target { ! { cris*-*-* } } } } */ /* { dg-options "-O2 -fdump-tree-reassoc-details" } */ /* The transformation depends on BRANCH_COST being greater than 1 (see the notes in the PR), so try to force that. */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr53060.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr53060.c index db5acbdb6ea..503f0540774 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr53060.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr53060.c @@ -25,3 +25,4 @@ int main() /* Ignore a warning that is irrelevant to the purpose of this test. */ /* { dg-prune-output ".*GCC vector returned by reference.*" } */ +/* { dg-prune-output "changes the ABI" } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr58668.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr58668.c new file mode 100644 index 00000000000..3e09508dc16 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr58668.c @@ -0,0 +1,25 @@ +/* PR rtl-optimization/58668 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-mthumb" { target { { arm*-*-* } && arm_thumb2_ok } } } */ + +void *fn1 (void *); +void *fn2 (void *, const char *); +void fn3 (void *); +void fn4 (void *, int); + +void * +test (void *x) +{ + void *a, *b; + if (!(a = fn1 (x))) + return (void *) 0; + if (!(b = fn2 (a, "w"))) + { + fn3 (a); + return (void *) 0; + } + fn3 (a); + fn4 (b, 1); + return b; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr59827.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr59827.c new file mode 100644 index 00000000000..77e1e9ca206 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr59827.c @@ -0,0 +1,15 @@ +/* PR middle-end/59827 */ +/* { dg-do compile } */ + +int +foo (int p[2][]) /* { dg-error "array type has incomplete element type" } */ +{ + return p[0][0]; +} + +void +bar (void) +{ + int p[2][1]; + foo (p); /* { dg-error "type of formal parameter 1 is incomplete" } */ +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr59860.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr59860.c new file mode 100644 index 00000000000..6807d9c843f --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/pr59860.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +extern __inline __attribute__ ((__always_inline__)) __attribute__ ((__gnu_inline__)) __attribute__ ((__artificial__)) char * __attribute__ ((__nothrow__ , __leaf__)) +strcat (char *__restrict __dest, const char *__restrict __src) +{ + return __builtin___strcat_chk (__dest, __src, __builtin_object_size (__dest, 2 > 1)); +} +static char raw_decode; +void foo (char **argv, char *outfilename) +{ + if (**argv == 'r') + raw_decode = 1; + strcat (outfilename, raw_decode ? ".raw" : ".wav"); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-14gf.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-14gf.c index 999759e86f6..bc7fc1f5c9c 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-14gf.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-14gf.c @@ -11,14 +11,14 @@ memcpy. */ /* { dg-final { scan-tree-dump-times "strlen \\(" 4 "strlen" } } */ /* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 2 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__mempcpy_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 3 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "mempcpy \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "memcpy \\(" 1 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "mempcpy \\(" 2 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "stpcpy \\(" 2 "strlen" } } */ /* { dg-final { cleanup-tree-dump "strlen" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-1f.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-1f.c index 4b0207fd4f7..f5d85710ed6 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-1f.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-1f.c @@ -6,13 +6,13 @@ #include "strlenopt-1.c" /* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 3 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "memcpy \\(" 3 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */ /* { dg-final { cleanup-tree-dump "strlen" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4.c index 5997d31985f..beea4959245 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4.c @@ -66,16 +66,10 @@ main () return 0; } -/* For targets providing a movstr pattern strcat is already decomposed - into strlen + strcpy by fold_builtin_strcat. */ - -/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" { target { ! s390*-*-* } } } } */ -/* { dg-final { scan-tree-dump-times "strlen \\(" 6 "strlen" { target s390*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen" } } */ /* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" { target { ! s390*-*-* } } } } */ -/* { dg-final { scan-tree-dump-times "strcpy \\(" 6 "strlen" { target s390*-*-* } } } */ -/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" { target { ! s390*-*-* } } } } */ -/* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" { target s390*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "strcpy \\(" 3 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "strcat \\(" 3 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */ /* { dg-final { cleanup-tree-dump "strlen" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4gf.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4gf.c index cf99212a152..f6088d60c89 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4gf.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/strlenopt-4gf.c @@ -7,13 +7,13 @@ #include "strlenopt-4.c" /* { dg-final { scan-tree-dump-times "strlen \\(" 1 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 4 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 1 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__memcpy_chk \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__strcpy_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "__strcat_chk \\(" 0 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 5 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "memcpy \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "__stpcpy_chk \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "memcpy \\(" 4 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "strcpy \\(" 1 "strlen" } } */ /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen" } } */ -/* { dg-final { scan-tree-dump-times "stpcpy \\(" 0 "strlen" } } */ +/* { dg-final { scan-tree-dump-times "stpcpy \\(" 5 "strlen" } } */ /* { dg-final { cleanup-tree-dump "strlen" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/torture/pr59715.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/torture/pr59715.c new file mode 100644 index 00000000000..19c09de55d7 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/torture/pr59715.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ + +extern void abort (void); + +int a = 2, b; + +int +main () +{ + int c; + if (!b) + { + b = a; + c = a == 0 ? 1 : 1 % a; + if (c) + b = 0; + } + if (b != 0) + abort (); + return 0; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.dg/torture/pr59891.c b/gcc-4_8-branch/gcc/testsuite/gcc.dg/torture/pr59891.c new file mode 100644 index 00000000000..1562acccf68 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.dg/torture/pr59891.c @@ -0,0 +1,9 @@ +/* PR c/59891 */ + +unsigned int a; + +int +main () +{ + return (0 ? a : 0) ? : 0 % 0; /* { dg-warning "division by zero" } */ +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c new file mode 100644 index 00000000000..5f4c927b6e0 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c @@ -0,0 +1,25 @@ +/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */ + +/* Detect ICE in the case of unaligned memory address. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +unsigned char dummy_store[1000]; + +void +foo (char* addr) +{ + uint8x16_t vdata = vld1q_u8 (addr); + vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0); +} + +uint64_t +bar (uint64x2_t vdata) +{ + vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0); + return vgetq_lane_u64 (vdata, 0); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr54300.C b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr54300.C new file mode 100644 index 00000000000..eb1a74e36cf --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr54300.C @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include +#include + +struct __attribute__ ((aligned(8))) _v16u8_ { + uint8x16_t val; + _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); } + operator int16x8_t () const { return vreinterpretq_s16_u8(val); } +}; +typedef struct _v16u8_ v16u8; + +struct __attribute__ ((aligned(4))) _v8u8_ { + uint8x8_t val; + _v8u8_( const uint8x8_t &src) { val = src; } + operator int16x4_t () const { return vreinterpret_s16_u8(val); } +}; +typedef struct _v8u8_ v8u8; + +typedef v16u8 v8i16; +typedef int32x4_t v4i32; +typedef const short cv1i16; +typedef const unsigned char cv1u8; +typedef const v8i16 cv8i16; + +static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); } + +static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){ + return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() ); +} +static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){ + return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) ); +} + +void __attribute__((noinline)) +test(unsigned short *_Inp, int32_t *_Out, + unsigned int s1v, unsigned int dv0, + unsigned int smask_v) +{ + int32x4_t c = vdupq_n_s32(0); + + for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v ) + { + int32x4_t s; + s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) ); + c = vaddq_s32( c, s ); + } + vst1q_s32( _Out, c ); +} + +main() +{ + unsigned short a[4] = {1, 2, 3, 4}; + int32_t b[4] = {0, 0, 0, 0}; + test(a, b, 1, 1, ~0); + if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4) + abort(); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr59826.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr59826.c new file mode 100644 index 00000000000..b7053e4268d --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr59826.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -mcpu=cortex-m4 -fprefetch-loop-arrays -O2" } */ + +typedef struct genxWriter_rec * genxWriter; +typedef unsigned char * utf8; +typedef const unsigned char * constUtf8; + +int genxScrubText(genxWriter w, constUtf8 in, utf8 out) +{ + int problems = 0; + constUtf8 last = in; + + while (*in) + { + int c = genxNextUnicodeChar(&in); + if (c == -1) + { + problems++; + last = in; + continue; + } + + if (!isXMLChar(w, c)) + { + problems++; + last = in; + continue; + } + + while (last < in) + *out++ = *last++; + } + *out = 0; + return problems; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr39162.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr39162.c index c549106adbb..94f39107db6 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr39162.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr39162.c @@ -4,8 +4,10 @@ typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__)); -__m256i +extern __m256i y; + +void bar (__m256i x) /* { dg-warning "AVX" "" } */ { - return x; + y = x; } diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr54694.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr54694.c new file mode 100644 index 00000000000..bcf82c2a16d --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr54694.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +register void *hfp __asm__("%ebp"); /* { dg-message "note: for" } */ + +extern void g(void *); + +void f(int x) /* { dg-error "frame pointer required" } */ +{ + g(__builtin_alloca(x)); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59470.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59470.c new file mode 100644 index 00000000000..0d9952fb4b0 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59470.c @@ -0,0 +1,17 @@ +/* PR middle-end/58956 */ +/* PR middle-end/59470 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +int a, b, d[1024]; + +int +main () +{ + int c = a; + asm ("{movl $6, (%2); movl $1, %0|mov dword ptr [%2], 6; mov %0, 1}" + : "=r" (d[c]) : "rm" (b), "r" (&a) : "memory"); + if (d[0] != 1 || d[6] != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59839.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59839.c new file mode 100644 index 00000000000..dfb89456f9d --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59839.c @@ -0,0 +1,12 @@ +/* PR target/59839 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx2" } */ + +#include + +void +test (const float *x) +{ + __m256i i = _mm256_set1_epi32 (1); + __m256 d = _mm256_i32gather_ps (x, i, 1); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59929.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59929.c new file mode 100644 index 00000000000..4591dc4d601 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr59929.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-O0 -mno-accumulate-outgoing-args" } */ +/* { dg-options "-O0 -mno-accumulate-outgoing-args -mx32 -maddress-mode=short" { target x32 } } */ + +void +__attribute__ ((noinline)) +test (float x1, float x2, float x3, float x4, float x5, float x6, + float x7, float x8, float x9, float x10, float x11, float x12, + float x13, float x14, float x15, float x16) +{ + if (x1 != 91 + || x2 != 92 + || x3 != 93 + || x4 != 94 + || x5 != 95 + || x6 != 96 + || x7 != 97 + || x8 != 98 + || x9 != 99 + || x10 != 100 + || x11 != 101 + || x12 != 102 + || x13 != 103 + || x14 != 104 + || x15 != 105 + || x16 != 106) + __builtin_abort (); +} + +float x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, + x14, x15, x16; + +int +main () +{ + x1 = 91; + x2 = 92; + x3 = 93; + x4 = 94; + x5 = 95; + x6 = 96; + x7 = 97; + x8 = 98; + x9 = 99; + x10 = 100; + x11 = 101; + x12 = 102; + x13 = 103; + x14 = 104; + x15 = 105; + x16 = 106; + test (x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, + x14, x15, x16); + return 0; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr9771-1.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr9771-1.c index 38586fe9725..daad319c379 100644 --- a/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr9771-1.c +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/i386/pr9771-1.c @@ -45,7 +45,17 @@ void test(void) exit(0); } -int main() +/* main usually performs dynamic realignment of the stack in case + _start would fail to properly align the stack, but for dynamic + stack realignment we need frame pointer which is incompatible + with -ffixed-ebp and the global register var. So, cheat here + and hide from the compiler that main is really main. */ +#define ASMNAME(cname) ASMNAME2 (__USER_LABEL_PREFIX__, cname) +#define ASMNAME2(prefix, cname) STRING (prefix) cname +#define STRING(x) #x +int real_main() __asm (ASMNAME ("main")); + +int real_main() { test(); return 0; diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c new file mode 100644 index 00000000000..79cc5f9dd8e --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c @@ -0,0 +1,9 @@ +/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ + +void float_func(float f1, float f2, float f3) +{ + /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if(f1==f2 && f1<=f3) + print ("f1 eq f2 && f1 le f3"); +} diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c new file mode 100644 index 00000000000..fdcde1fa7de --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ + +void trap () +{ + __builtin_trap (); +} + +/* { dg-final { scan-assembler "brki\tr0,-1" } } */ \ No newline at end of file diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-1.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-1.c new file mode 100644 index 00000000000..24016f26931 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-1.c @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return ((x << 8) & 0xff00) | ((x >> 8) & 0xff); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-2.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-2.c new file mode 100644 index 00000000000..e0ca496b6d1 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-2.c @@ -0,0 +1,9 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned short +foo (unsigned short x) +{ + return __builtin_bswap16 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-3.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-3.c new file mode 100644 index 00000000000..5d2086fd324 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-3.c @@ -0,0 +1,14 @@ +/* { dg-options "isa_rev>=2" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return (((x << 24) & 0xff000000) + | ((x << 8) & 0xff0000) + | ((x >> 8) & 0xff00) + | ((x >> 24) & 0xff)); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-4.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-4.c new file mode 100644 index 00000000000..ac37a011440 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-4.c @@ -0,0 +1,10 @@ +/* { dg-options "isa_rev>=2" } */ + +NOMIPS16 unsigned int +foo (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +/* { dg-final { scan-assembler "\twsbh\t" } } */ +/* { dg-final { scan-assembler "\tror\t" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-5.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-5.c new file mode 100644 index 00000000000..45520e4ab85 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-5.c @@ -0,0 +1,20 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ +/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return (((x << 56) & 0xff00000000000000ull) + | ((x << 40) & 0xff000000000000ull) + | ((x << 24) & 0xff0000000000ull) + | ((x << 8) & 0xff00000000ull) + | ((x >> 8) & 0xff000000) + | ((x >> 24) & 0xff0000) + | ((x >> 40) & 0xff00) + | ((x >> 56) & 0xff)); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-6.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-6.c new file mode 100644 index 00000000000..1145357fef1 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/bswap-6.c @@ -0,0 +1,12 @@ +/* { dg-options "isa_rev>=2 -mgp64" } */ + +typedef unsigned long long uint64_t; + +NOMIPS16 uint64_t +foo (uint64_t x) +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler "\tdsbh\t" } } */ +/* { dg-final { scan-assembler "\tdshd\t" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/pr59137.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/pr59137.c new file mode 100644 index 00000000000..89865065680 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/mips/pr59137.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-mno-plt" } */ + +extern void abort (void); + +struct lispstruct +{ + int e; + int t; +}; + +struct lispstruct Cnil_body; +struct lispstruct Ct_body; +int nvalues; + +struct lispstruct * __attribute__ ((noinline)) +fLlistp (struct lispstruct *x0) +{ + if (x0 == &Cnil_body + || (((unsigned long) x0 >= 0x80000000) ? 0 + : (!x0->e ? (x0 != &Cnil_body) : x0->t))) + x0 = &Ct_body; + else + x0 = &Cnil_body; + nvalues = 1; + return x0; +} + +int main () +{ + if (fLlistp ((struct lispstruct *) 0xa0000001) != &Cnil_body) + abort (); + return 0; +} diff --git a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/allocate_class_3.f90 b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/allocate_class_3.f90 new file mode 100644 index 00000000000..ddc7e23283f --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/allocate_class_3.f90 @@ -0,0 +1,107 @@ +! { dg-do run } +! Tests the fix for PR59414, comment #3, in which the allocate +! expressions were not correctly being stripped to provide the +! vpointer as an lhs to the pointer assignment of the vptr from +! the SOURCE expression. +! +! Contributed by Antony Lewis +! +module ObjectLists + implicit none + + type :: t + integer :: i + end type + + type Object_array_pointer + class(t), pointer :: p(:) + end type + +contains + + subroutine AddArray1 (P, Pt) + class(t) :: P(:) + class(Object_array_pointer) :: Pt + + select type (Pt) + class is (Object_array_pointer) + if (associated (Pt%P)) deallocate (Pt%P) + allocate(Pt%P(1:SIZE(P)), source=P) + end select + end subroutine + + subroutine AddArray2 (P, Pt) + class(t) :: P(:) + class(Object_array_pointer) :: Pt + + select type (Pt) + type is (Object_array_pointer) + if (associated (Pt%P)) deallocate (Pt%P) + allocate(Pt%P(1:SIZE(P)), source=P) + end select + end subroutine + + subroutine AddArray3 (P, Pt) + class(t) :: P + class(Object_array_pointer) :: Pt + + select type (Pt) + class is (Object_array_pointer) + if (associated (Pt%P)) deallocate (Pt%P) + allocate(Pt%P(1:4), source=P) + end select + end subroutine + + subroutine AddArray4 (P, Pt) + type(t) :: P(:) + class(Object_array_pointer) :: Pt + + select type (Pt) + class is (Object_array_pointer) + if (associated (Pt%P)) deallocate (Pt%P) + allocate(Pt%P(1:SIZE(P)), source=P) + end select + end subroutine +end module + + use ObjectLists + type(Object_array_pointer), pointer :: Pt + class(t), pointer :: P(:) + + allocate (P(2), source = [t(1),t(2)]) + allocate (Pt, source = Object_array_pointer(NULL())) + call AddArray1 (P, Pt) + select type (x => Pt%p) + type is (t) + if (any (x%i .ne. [1,2])) call abort + end select + deallocate (P) + deallocate (pt) + + allocate (P(3), source = [t(3),t(4),t(5)]) + allocate (Pt, source = Object_array_pointer(NULL())) + call AddArray2 (P, Pt) + select type (x => Pt%p) + type is (t) + if (any (x%i .ne. [3,4,5])) call abort + end select + deallocate (P) + deallocate (pt) + + allocate (Pt, source = Object_array_pointer(NULL())) + call AddArray3 (t(6), Pt) + select type (x => Pt%p) + type is (t) + if (any (x%i .ne. [6,6,6,6])) call abort + end select + deallocate (pt) + + allocate (Pt, source = Object_array_pointer(NULL())) + call AddArray4 ([t(7), t(8)], Pt) + select type (x => Pt%p) + type is (t) + if (any (x%i .ne. [7,8])) call abort + end select + deallocate (pt) + end + diff --git a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_5.f90 b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_5.f90 index 886a6a1ff8b..50b41c3e8bf 100644 --- a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_5.f90 +++ b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_5.f90 @@ -34,7 +34,7 @@ subroutine test_PR34547_1 () end subroutine test_PR34547_1 subroutine test_PR34547_2 () - print *, null () ! { dg-error "in data transfer statement requires MOLD" } + print *, null () ! { dg-error "Invalid context" } end subroutine test_PR34547_2 subroutine test_PR34547_3 () diff --git a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_6.f90 b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_6.f90 index dd517cfa3e2..6b8f21e63bc 100644 --- a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_6.f90 +++ b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/null_6.f90 @@ -30,5 +30,5 @@ end subroutine test_PR50375_2 subroutine test_PR34547_3 () integer, allocatable :: i(:) - print *, NULL(i) + print *, NULL(i) ! { dg-error "Invalid context for NULL" } end subroutine test_PR34547_3 diff --git a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 new file mode 100644 index 00000000000..07fbce3d595 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 @@ -0,0 +1,44 @@ +! { dg-do compile } +! +! PR fortran/58007 +! Unresolved fixup while loading a module. +! +! This tests that the specification expression A%MAX_DEGREE in module BSR is +! correctly loaded and resolved in program MAIN. +! +! Original testcase from Daniel Shapiro +! Reduced by Tobias Burnus and Janus Weil + +module matrix + type :: sparse_matrix + integer :: max_degree + end type +contains + subroutine init_interface (A) + class(sparse_matrix), intent(in) :: A + end subroutine + real function get_value_interface() + end function +end module + +module ellpack + use matrix +end module + +module bsr + use matrix + type, extends(sparse_matrix) :: bsr_matrix + contains + procedure :: get_neighbors + end type +contains + function get_neighbors (A) + class(bsr_matrix), intent(in) :: A + integer :: get_neighbors(A%max_degree) + end function +end module + +program main + use ellpack + use bsr +end diff --git a/gcc-4_8-branch/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 new file mode 100644 index 00000000000..ca0a05a629a --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 @@ -0,0 +1,36 @@ +! { dg-do compile } +! +! PR fortran/58007 +! Unresolved fiixup while loading a module. +! +! This tests that the specification expression A%MAX_DEGREE in module BSR is +! correctly loaded and resolved in program MAIN. +! +! Original testcase from Daniel Shapiro + +module matrix + type :: sparse_matrix + integer :: max_degree + end type +end module + +module bsr + use matrix + + type, extends(sparse_matrix) :: bsr_matrix + end type + + integer :: i1 + integer :: i2 + integer :: i3 +contains + function get_neighbors (A) + type(bsr_matrix), intent(in) :: A + integer :: get_neighbors(A%max_degree) + end function +end module + +program main + use matrix + use bsr +end diff --git a/gcc-4_8-branch/gcc/testsuite/go.test/go-test.exp b/gcc-4_8-branch/gcc/testsuite/go.test/go-test.exp index 6f397343e0f..4c8c36e3e2a 100644 --- a/gcc-4_8-branch/gcc/testsuite/go.test/go-test.exp +++ b/gcc-4_8-branch/gcc/testsuite/go.test/go-test.exp @@ -333,17 +333,16 @@ proc go-gc-tests { } { } if { ( [file tail $test] == "select2.go" \ - || [file tail $test] == "stack.go" ) \ + || [file tail $test] == "stack.go" \ + || [file tail $test] == "peano.go" ) \ && ! [check_effective_target_split_stack] } { - # chan/select2.go fails on targets without split stack, - # because they allocate a large stack segment that blows - # out the memory calculations. + # These tests fails on targets without split stack. untested $name continue } - if { [file tail $test] == "rotate.go" } { - # This test produces a temporary file that takes too long + if [string match "*go.test/test/rotate\[0123\].go" $test] { + # These tests produces a temporary file that takes too long # to compile--5 minutes on my laptop without optimization. # When compiling without optimization it tests nothing # useful, since the point of the test is to see whether diff --git a/gcc-4_8-branch/gcc/tree-cfg.c b/gcc-4_8-branch/gcc/tree-cfg.c index 7b3eab09f56..f65d8734aaa 100644 --- a/gcc-4_8-branch/gcc/tree-cfg.c +++ b/gcc-4_8-branch/gcc/tree-cfg.c @@ -104,7 +104,6 @@ static int locus_map_eq (const void *, const void *); static void assign_discriminator (location_t, basic_block); static edge gimple_redirect_edge_and_branch (edge, basic_block); static edge gimple_try_redirect_by_replacing_jump (edge, basic_block); -static unsigned int split_critical_edges (void); /* Various helpers. */ static inline bool stmt_starts_bb_p (gimple, gimple); @@ -7647,7 +7646,7 @@ struct cfg_hooks gimple_cfg_hooks = { /* Split all critical edges. */ -static unsigned int +unsigned int split_critical_edges (void) { basic_block bb; diff --git a/gcc-4_8-branch/gcc/tree-eh.c b/gcc-4_8-branch/gcc/tree-eh.c index 973782ba5a8..41b55acbc77 100644 --- a/gcc-4_8-branch/gcc/tree-eh.c +++ b/gcc-4_8-branch/gcc/tree-eh.c @@ -1357,9 +1357,6 @@ lower_try_finally_switch (struct leh_state *state, struct leh_tf_state *tf) x = gimple_seq_last_stmt (finally); finally_loc = x ? gimple_location (x) : tf_loc; - /* Lower the finally block itself. */ - lower_eh_constructs_1 (state, &finally); - /* Prepare for switch statement generation. */ nlabels = tf->dest_array.length (); return_index = nlabels; @@ -1445,6 +1442,7 @@ lower_try_finally_switch (struct leh_state *state, struct leh_tf_state *tf) x = gimple_build_label (finally_label); gimple_seq_add_stmt (&tf->top_p_seq, x); + lower_eh_constructs_1 (state, &finally); gimple_seq_add_seq (&tf->top_p_seq, finally); /* Redirect each incoming goto edge. */ diff --git a/gcc-4_8-branch/gcc/tree-flow.h b/gcc-4_8-branch/gcc/tree-flow.h index 20584b8c60f..e0aef5b9249 100644 --- a/gcc-4_8-branch/gcc/tree-flow.h +++ b/gcc-4_8-branch/gcc/tree-flow.h @@ -425,6 +425,7 @@ extern basic_block move_sese_region_to_fn (struct function *, basic_block, basic_block, tree); void remove_edge_and_dominated_blocks (edge); bool tree_node_can_be_shared (tree); +extern unsigned int split_critical_edges (void); /* In tree-cfgcleanup.c */ extern bitmap cfgcleanup_altered_bbs; diff --git a/gcc-4_8-branch/gcc/tree-object-size.c b/gcc-4_8-branch/gcc/tree-object-size.c index 2b8311a6c05..6dc971a8581 100644 --- a/gcc-4_8-branch/gcc/tree-object-size.c +++ b/gcc-4_8-branch/gcc/tree-object-size.c @@ -64,7 +64,7 @@ static void check_for_plus_in_loops_1 (struct object_size_info *, tree, the subobject (innermost array or field with address taken). object_sizes[2] is lower bound for number of bytes till the end of the object and object_sizes[3] lower bound for subobject. */ -static unsigned HOST_WIDE_INT *object_sizes[4]; +static vec object_sizes[4]; /* Bitmaps what object sizes have been computed already. */ static bitmap computed[4]; @@ -493,7 +493,7 @@ compute_builtin_object_size (tree ptr, int object_size_type) if (TREE_CODE (ptr) == SSA_NAME && POINTER_TYPE_P (TREE_TYPE (ptr)) - && object_sizes[object_size_type] != NULL) + && computed[object_size_type] != NULL) { if (!bitmap_bit_p (computed[object_size_type], SSA_NAME_VERSION (ptr))) { @@ -501,6 +501,8 @@ compute_builtin_object_size (tree ptr, int object_size_type) bitmap_iterator bi; unsigned int i; + if (num_ssa_names > object_sizes[object_size_type].length ()) + object_sizes[object_size_type].safe_grow (num_ssa_names); if (dump_file) { fprintf (dump_file, "Computing %s %sobject size for ", @@ -1162,12 +1164,12 @@ init_object_sizes (void) { int object_size_type; - if (object_sizes[0]) + if (computed[0]) return; for (object_size_type = 0; object_size_type <= 3; object_size_type++) { - object_sizes[object_size_type] = XNEWVEC (unsigned HOST_WIDE_INT, num_ssa_names); + object_sizes[object_size_type].safe_grow (num_ssa_names); computed[object_size_type] = BITMAP_ALLOC (NULL); } @@ -1184,9 +1186,8 @@ fini_object_sizes (void) for (object_size_type = 0; object_size_type <= 3; object_size_type++) { - free (object_sizes[object_size_type]); + object_sizes[object_size_type].release (); BITMAP_FREE (computed[object_size_type]); - object_sizes[object_size_type] = NULL; } } @@ -1202,16 +1203,9 @@ compute_object_sizes (void) gimple_stmt_iterator i; for (i = gsi_start_bb (bb); !gsi_end_p (i); gsi_next (&i)) { - tree callee, result; + tree result; gimple call = gsi_stmt (i); - - if (gimple_code (call) != GIMPLE_CALL) - continue; - - callee = gimple_call_fndecl (call); - if (!callee - || DECL_BUILT_IN_CLASS (callee) != BUILT_IN_NORMAL - || DECL_FUNCTION_CODE (callee) != BUILT_IN_OBJECT_SIZE) + if (!gimple_call_builtin_p (call, BUILT_IN_OBJECT_SIZE)) continue; init_object_sizes (); @@ -1240,20 +1234,32 @@ compute_object_sizes (void) continue; } + gcc_assert (TREE_CODE (result) == INTEGER_CST); + if (dump_file && (dump_flags & TDF_DETAILS)) { fprintf (dump_file, "Simplified\n "); print_gimple_stmt (dump_file, call, 0, dump_flags); + fprintf (dump_file, " to "); + print_generic_expr (dump_file, result, 0); + fprintf (dump_file, "\n"); } - if (!update_call_from_tree (&i, result)) - gcc_unreachable (); + tree lhs = gimple_call_lhs (call); + if (!lhs) + continue; - if (dump_file && (dump_flags & TDF_DETAILS)) + /* Propagate into all uses and fold those stmts. */ + gimple use_stmt; + imm_use_iterator iter; + FOR_EACH_IMM_USE_STMT (use_stmt, iter, lhs) { - fprintf (dump_file, "to\n "); - print_gimple_stmt (dump_file, gsi_stmt (i), 0, dump_flags); - fprintf (dump_file, "\n"); + use_operand_p use_p; + FOR_EACH_IMM_USE_ON_STMT (use_p, iter) + SET_USE (use_p, result); + gimple_stmt_iterator gsi = gsi_for_stmt (use_stmt); + fold_stmt (&gsi); + update_stmt (gsi_stmt (gsi)); } } } diff --git a/gcc-4_8-branch/gcc/tree-predcom.c b/gcc-4_8-branch/gcc/tree-predcom.c index c2560130dcd..73a7a26c9dd 100644 --- a/gcc-4_8-branch/gcc/tree-predcom.c +++ b/gcc-4_8-branch/gcc/tree-predcom.c @@ -2402,6 +2402,7 @@ tree_predictive_commoning_loop (struct loop *loop) if (!components) { free_data_refs (datarefs); + free_affine_expand_cache (&name_expansions); return false; } diff --git a/gcc-4_8-branch/gcc/tree-sra.c b/gcc-4_8-branch/gcc/tree-sra.c index 627fadc66a6..5142d4b11c0 100644 --- a/gcc-4_8-branch/gcc/tree-sra.c +++ b/gcc-4_8-branch/gcc/tree-sra.c @@ -1161,8 +1161,7 @@ build_accesses_from_assign (gimple stmt) GIMPLE_ASM operands with memory constrains which cannot be scalarized. */ static bool -asm_visit_addr (gimple stmt ATTRIBUTE_UNUSED, tree op, - void *data ATTRIBUTE_UNUSED) +asm_visit_addr (gimple, tree op, tree, void *) { op = get_base_address (op); if (op diff --git a/gcc-4_8-branch/gcc/tree-ssa-sccvn.c b/gcc-4_8-branch/gcc/tree-ssa-sccvn.c index 016a5d1bad3..5dce65afe85 100644 --- a/gcc-4_8-branch/gcc/tree-ssa-sccvn.c +++ b/gcc-4_8-branch/gcc/tree-ssa-sccvn.c @@ -660,7 +660,7 @@ copy_reference_ops_from_ref (tree ref, vec *result) } /* For non-calls, store the information that makes up the address. */ - + tree orig = ref; while (ref) { vn_reference_op_s temp; @@ -711,7 +711,15 @@ copy_reference_ops_from_ref (tree ref, vec *result) .arshift (BITS_PER_UNIT == 8 ? 3 : exact_log2 (BITS_PER_UNIT), HOST_BITS_PER_DOUBLE_INT); - if (off.fits_shwi ()) + if (off.fits_shwi () + /* Probibit value-numbering zero offset components + of addresses the same before the pass folding + __builtin_object_size had a chance to run + (checking cfun->after_inlining does the + trick here). */ + && (TREE_CODE (orig) != ADDR_EXPR + || !off.is_zero () + || cfun->after_inlining)) temp.off = off.low; } } diff --git a/gcc-4_8-branch/gcc/tree-ssa-sink.c b/gcc-4_8-branch/gcc/tree-ssa-sink.c index 9f091748e63..3df200ea3f5 100644 --- a/gcc-4_8-branch/gcc/tree-ssa-sink.c +++ b/gcc-4_8-branch/gcc/tree-ssa-sink.c @@ -559,7 +559,7 @@ static void execute_sink_code (void) { loop_optimizer_init (LOOPS_NORMAL); - + split_critical_edges (); connect_infinite_loops_to_exit (); memset (&sink_stats, 0, sizeof (sink_stats)); calculate_dominance_info (CDI_DOMINATORS); diff --git a/gcc-4_8-branch/gcc/tree-ssa-ter.c b/gcc-4_8-branch/gcc/tree-ssa-ter.c index d364af1b9d7..d3efd312ff1 100644 --- a/gcc-4_8-branch/gcc/tree-ssa-ter.c +++ b/gcc-4_8-branch/gcc/tree-ssa-ter.c @@ -590,6 +590,30 @@ mark_replaceable (temp_expr_table_p tab, tree var, bool more_replacing) } +/* Helper function for find_ssaname_in_stores. Called via walk_tree to + find a SSA_NAME DATA somewhere in *TP. */ + +static tree +find_ssaname (tree *tp, int *walk_subtrees, void *data) +{ + tree var = (tree) data; + if (*tp == var) + return var; + else if (IS_TYPE_OR_DECL_P (*tp)) + *walk_subtrees = 0; + return NULL_TREE; +} + +/* Helper function for find_replaceable_in_bb. Return true if SSA_NAME DATA + is used somewhere in T, which is a store in the statement. Called via + walk_stmt_load_store_addr_ops. */ + +static bool +find_ssaname_in_store (gimple, tree, tree t, void *data) +{ + return walk_tree (&t, find_ssaname, data, NULL) != NULL_TREE; +} + /* This function processes basic block BB, and looks for variables which can be replaced by their expressions. Results are stored in the table TAB. */ @@ -654,7 +678,27 @@ find_replaceable_in_bb (temp_expr_table_p tab, basic_block bb) && gimple_assign_single_p (def_stmt) && stmt_may_clobber_ref_p (stmt, gimple_assign_rhs1 (def_stmt))) - same_root_var = true; + { + /* For calls, it is not a problem if USE is among + call's arguments or say OBJ_TYPE_REF argument, + all those necessarily need to be evaluated before + the call that may clobber the memory. But if + LHS of the call refers to USE, expansion might + evaluate it after the call, prevent TER in that + case. + For inline asm, allow TER of loads into input + arguments, but disallow TER for USEs that occur + somewhere in outputs. */ + if (is_gimple_call (stmt) + || gimple_code (stmt) == GIMPLE_ASM) + { + if (walk_stmt_load_store_ops (stmt, use, NULL, + find_ssaname_in_store)) + same_root_var = true; + } + else + same_root_var = true; + } } /* Mark expression as replaceable unless stmt is volatile, or the diff --git a/gcc-4_8-branch/gcc/tree.h b/gcc-4_8-branch/gcc/tree.h index d6414faf145..fb2123e42ce 100644 --- a/gcc-4_8-branch/gcc/tree.h +++ b/gcc-4_8-branch/gcc/tree.h @@ -3589,7 +3589,7 @@ struct GTY(()) tree_optimization_option { /* Target optabs for this set of optimization options. This is of type `struct target_optabs *'. */ - unsigned char *GTY ((atomic)) optabs; + void *GTY ((atomic)) optabs; /* The value of this_target_optabs against which the optabs above were generated. */ @@ -5854,6 +5854,7 @@ extern tree fold_call_expr (location_t, tree, bool); extern tree fold_builtin_fputs (location_t, tree, tree, bool, bool, tree); extern tree fold_builtin_strcpy (location_t, tree, tree, tree, tree); extern tree fold_builtin_strncpy (location_t, tree, tree, tree, tree, tree); +extern tree fold_builtin_strcat (location_t, tree, tree, tree); extern tree fold_builtin_memory_chk (location_t, tree, tree, tree, tree, tree, tree, bool, enum built_in_function); extern tree fold_builtin_stxcpy_chk (location_t, tree, tree, tree, tree, tree, bool, diff --git a/gcc-4_8-branch/libgcc/ChangeLog b/gcc-4_8-branch/libgcc/ChangeLog index c242a13b262..960c8435569 100644 --- a/gcc-4_8-branch/libgcc/ChangeLog +++ b/gcc-4_8-branch/libgcc/ChangeLog @@ -1,3 +1,111 @@ +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilepro/atomic.c (pre_atomic_barrier): Mark inline. + (post_atomic_barrier): Ditto. + (__fetch_and_do): New macro. + (__atomic_fetch_and_do): Use __fetch_and_do. + (__sync_fetch_and_do): New macro. + (__sync_fetch_and_add_4): New function. + (__sync_fetch_and_sub_4): New function. + (__sync_fetch_and_or_4): New function. + (__sync_fetch_and_and_4): New function. + (__sync_fetch_and_xor_4): New function. + (__sync_fetch_and_nand_4): New function. + (__sync_fetch_and_add_8): New function. + (__sync_fetch_and_sub_8): New function. + (__sync_fetch_and_or_8): New function. + (__sync_fetch_and_and_8): New function. + (__sync_fetch_and_xor_8): New function. + (__sync_fetch_and_nand_8): New function. + (__do_and_fetch): New macro. + (__atomic_do_and_fetch): Use __do_and_fetch. + (__sync_do_and_fetch): New macro. + (__sync_add_and_fetch_4): New function. + (__sync_sub_and_fetch_4): New function. + (__sync_or_and_fetch_4): New function. + (__sync_and_and_fetch_4): New function. + (__sync_xor_and_fetch_4): New function. + (__sync_nand_and_fetch_4): New function. + (__sync_add_and_fetch_8): New function. + (__sync_sub_and_fetch_8): New function. + (__sync_or_and_fetch_8): New function. + (__sync_and_and_fetch_8): New function. + (__sync_xor_and_fetch_8): New function. + (__sync_nand_and_fetch_8): New function. + (__sync_exchange_methods): New macro. + (__sync_val_compare_and_swap_4): New function. + (__sync_bool_compare_and_swap_4): New function. + (__sync_lock_test_and_test_4): New function. + (__sync_val_compare_and_swap_8): New function. + (__sync_bool_compare_and_swap_8): New function. + (__sync_lock_test_and_test_8): New function. + (__subword_cmpxchg_body): New macro. + (__atomic_compare_exchange_1): Use __subword_cmpxchg_body. + (__atomic_compare_exchange_2): Ditto. + (__sync_subword_cmpxchg): New macro. + (__sync_val_compare_and_swap_1): New function. + (__sync_bool_compare_and_swap_1): New function. + (__sync_val_compare_and_swap_2): New function. + (__sync_bool_compare_and_swap_2): New function. + (__atomic_subword): Rename to ... + (__subword): ... New name. + (__atomic_subword_fetch): Use __subword. + (__sync_subword_fetch): New macro. + (__sync_fetch_and_add_1): New function. + (__sync_fetch_and_sub_1): New function. + (__sync_fetch_and_or_1): New function. + (__sync_fetch_and_and_1): New function. + (__sync_fetch_and_xor_1): New function. + (__sync_fetch_and_nand_1): New function. + (__sync_fetch_and_add_2): New function. + (__sync_fetch_and_sub_2): New function. + (__sync_fetch_and_or_2): New function. + (__sync_fetch_and_and_2): New function. + (__sync_fetch_and_xor_2): New function. + (__sync_fetch_and_nand_2): New function. + (__sync_add_and_fetch_1): New function. + (__sync_sub_and_fetch_1): New function. + (__sync_or_and_fetch_1): New function. + (__sync_and_and_fetch_1): New function. + (__sync_xor_and_fetch_1): New function. + (__sync_nand_and_fetch_1): New function. + (__sync_add_and_fetch_2): New function. + (__sync_sub_and_fetch_2): New function. + (__sync_or_and_fetch_2): New function. + (__sync_and_and_fetch_2): New function. + (__sync_xor_and_fetch_2): New function. + (__sync_nand_and_fetch_2): New function. + (__atomic_subword_lock): Use __subword. + (__sync_subword_lock): New macro. + (__sync_lock_test_and_set_1): New function. + (__sync_lock_test_and_set_2): New function. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilepro/atomic.c (BIT_OFFSET): Define. + (__atomic_subword_cmpxchg): Use BIT_OFFSET. + (__atomic_subword): Ditto. + +2014-01-25 Walter Lee + + Backport from mainline + 2014-01-25 Walter Lee + + * config/tilepro/atomic.c (__atomic_do_and_fetch): Add + a prefix op argument. + (__atomic_nand_fetch_4): Add prefix op. + (__atomic_nand_fetch_8): Ditto. + +2014-01-21 Baruch Siach + + * config.host (tmake_file): add t-slibgcc-libgcc for xtensa*-*-linux*. + 2014-01-03 Joseph Myers * config/rs6000/ibm-ldouble.c (__gcc_qdiv): Scale up arguments in diff --git a/gcc-4_8-branch/libgcc/config.host b/gcc-4_8-branch/libgcc/config.host index ee16d60e34a..302aa613521 100644 --- a/gcc-4_8-branch/libgcc/config.host +++ b/gcc-4_8-branch/libgcc/config.host @@ -1102,7 +1102,7 @@ xtensa*-*-elf*) extra_parts="$extra_parts crti.o crtn.o" ;; xtensa*-*-linux*) - tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux" + tmake_file="$tmake_file xtensa/t-xtensa xtensa/t-linux t-slibgcc-libgcc" md_unwind_header=xtensa/linux-unwind.h ;; am33_2.0-*-linux*) diff --git a/gcc-4_8-branch/libgcc/config/tilepro/atomic.c b/gcc-4_8-branch/libgcc/config/tilepro/atomic.c index 762bd6dc7f6..e7c0349ac39 100644 --- a/gcc-4_8-branch/libgcc/config/tilepro/atomic.c +++ b/gcc-4_8-branch/libgcc/config/tilepro/atomic.c @@ -28,7 +28,7 @@ /* This code should be inlined by the compiler, but for now support it as out-of-line methods in libgcc. */ -static void +static inline void pre_atomic_barrier (int model) { switch ((enum memmodel) model) @@ -44,7 +44,7 @@ pre_atomic_barrier (int model) return; } -static void +static inline void post_atomic_barrier (int model) { switch ((enum memmodel) model) @@ -62,16 +62,21 @@ post_atomic_barrier (int model) #define __unused __attribute__((unused)) -#define __atomic_fetch_and_do(type, size, opname) \ -type \ -__atomic_fetch_##opname##_##size(type* p, type i, int model) \ +#define __fetch_and_do(proto, type, size, opname, top, bottom) \ +proto \ { \ - pre_atomic_barrier(model); \ + top; \ type rv = arch_atomic_##opname(p, i); \ - post_atomic_barrier(model); \ + bottom; \ return rv; \ } +#define __atomic_fetch_and_do(type, size, opname) \ + __fetch_and_do(type __atomic_fetch_##opname##_##size(type* p, type i, int model), \ + type, size, opname, \ + pre_atomic_barrier(model), \ + post_atomic_barrier(model)) \ + __atomic_fetch_and_do (int, 4, add) __atomic_fetch_and_do (int, 4, sub) __atomic_fetch_and_do (int, 4, or) @@ -84,27 +89,73 @@ __atomic_fetch_and_do (long long, 8, or) __atomic_fetch_and_do (long long, 8, and) __atomic_fetch_and_do (long long, 8, xor) __atomic_fetch_and_do (long long, 8, nand) -#define __atomic_do_and_fetch(type, size, opname, op) \ -type \ -__atomic_##opname##_fetch_##size(type* p, type i, int model) \ -{ \ - pre_atomic_barrier(model); \ - type rv = arch_atomic_##opname(p, i) op i; \ - post_atomic_barrier(model); \ - return rv; \ + +#define __sync_fetch_and_do(type, size, opname) \ + __fetch_and_do(type __sync_fetch_and_##opname##_##size(type* p, type i), \ + type, size, opname, \ + arch_atomic_write_barrier(), \ + arch_atomic_read_barrier()) + +__sync_fetch_and_do (int, 4, add) +__sync_fetch_and_do (int, 4, sub) +__sync_fetch_and_do (int, 4, or) +__sync_fetch_and_do (int, 4, and) +__sync_fetch_and_do (int, 4, xor) +__sync_fetch_and_do (int, 4, nand) +__sync_fetch_and_do (long long, 8, add) +__sync_fetch_and_do (long long, 8, sub) +__sync_fetch_and_do (long long, 8, or) +__sync_fetch_and_do (long long, 8, and) +__sync_fetch_and_do (long long, 8, xor) +__sync_fetch_and_do (long long, 8, nand) + +#define __do_and_fetch(proto, type, size, opname, op, op2, top, bottom) \ +proto \ +{ \ + top; \ + type rv = op2 (arch_atomic_##opname(p, i) op i); \ + bottom; \ + return rv; \ } -__atomic_do_and_fetch (int, 4, add, +) -__atomic_do_and_fetch (int, 4, sub, -) -__atomic_do_and_fetch (int, 4, or, |) -__atomic_do_and_fetch (int, 4, and, &) -__atomic_do_and_fetch (int, 4, xor, |) -__atomic_do_and_fetch (int, 4, nand, &) -__atomic_do_and_fetch (long long, 8, add, +) -__atomic_do_and_fetch (long long, 8, sub, -) -__atomic_do_and_fetch (long long, 8, or, |) -__atomic_do_and_fetch (long long, 8, and, &) -__atomic_do_and_fetch (long long, 8, xor, |) -__atomic_do_and_fetch (long long, 8, nand, &) + +#define __atomic_do_and_fetch(type, size, opname, op, op2) \ + __do_and_fetch(type __atomic_##opname##_fetch_##size(type* p, type i, int model), \ + type, size, opname, op, op2, \ + pre_atomic_barrier(model), \ + post_atomic_barrier(model)) \ + +__atomic_do_and_fetch (int, 4, add, +, ) +__atomic_do_and_fetch (int, 4, sub, -, ) +__atomic_do_and_fetch (int, 4, or, |, ) +__atomic_do_and_fetch (int, 4, and, &, ) +__atomic_do_and_fetch (int, 4, xor, |, ) +__atomic_do_and_fetch (int, 4, nand, &, ~) +__atomic_do_and_fetch (long long, 8, add, +, ) +__atomic_do_and_fetch (long long, 8, sub, -, ) +__atomic_do_and_fetch (long long, 8, or, |, ) +__atomic_do_and_fetch (long long, 8, and, &, ) +__atomic_do_and_fetch (long long, 8, xor, |, ) +__atomic_do_and_fetch (long long, 8, nand, &, ~) + +#define __sync_do_and_fetch(type, size, opname, op, op2) \ + __do_and_fetch(type __sync_##opname##_and_fetch_##size(type* p, type i), \ + type, size, opname, op, op2, \ + arch_atomic_write_barrier(), \ + arch_atomic_read_barrier()) \ + +__sync_do_and_fetch (int, 4, add, +, ) +__sync_do_and_fetch (int, 4, sub, -, ) +__sync_do_and_fetch (int, 4, or, |, ) +__sync_do_and_fetch (int, 4, and, &, ) +__sync_do_and_fetch (int, 4, xor, |, ) +__sync_do_and_fetch (int, 4, nand, &, ~) +__sync_do_and_fetch (long long, 8, add, +, ) +__sync_do_and_fetch (long long, 8, sub, -, ) +__sync_do_and_fetch (long long, 8, or, |, ) +__sync_do_and_fetch (long long, 8, and, &, ) +__sync_do_and_fetch (long long, 8, xor, |, ) +__sync_do_and_fetch (long long, 8, nand, &, ~) + #define __atomic_exchange_methods(type, size) \ bool \ __atomic_compare_exchange_##size(volatile type* ptr, type* oldvalp, \ @@ -128,49 +179,117 @@ __atomic_exchange_##size(volatile type* ptr, type val, int model) \ post_atomic_barrier(model); \ return retval; \ } + __atomic_exchange_methods (int, 4) __atomic_exchange_methods (long long, 8) +#define __sync_exchange_methods(type, size) \ +type \ +__sync_val_compare_and_swap_##size(type* ptr, type oldval, type newval) \ +{ \ + arch_atomic_write_barrier(); \ + type retval = arch_atomic_val_compare_and_exchange(ptr, oldval, newval); \ + arch_atomic_read_barrier(); \ + return retval; \ +} \ + \ +bool \ +__sync_bool_compare_and_swap_##size(type* ptr, type oldval, type newval) \ +{ \ + arch_atomic_write_barrier(); \ + bool retval = arch_atomic_bool_compare_and_exchange(ptr, oldval, newval); \ + arch_atomic_read_barrier(); \ + return retval; \ +} \ + \ +type \ +__sync_lock_test_and_set_##size(type* ptr, type val) \ +{ \ + type retval = arch_atomic_exchange(ptr, val); \ + arch_atomic_acquire_barrier_value(retval); \ + return retval; \ +} + +__sync_exchange_methods (int, 4) +__sync_exchange_methods (long long, 8) + +#ifdef __LITTLE_ENDIAN__ +#define BIT_OFFSET(n, type) ((n) * 8) +#else +#define BIT_OFFSET(n, type) ((4 - sizeof(type) - (n)) * 8) +#endif + /* Subword methods require the same approach for both TILEPro and TILE-Gx. We load the background data for the word, insert the desired subword piece, then compare-and-exchange it into place. */ #define u8 unsigned char #define u16 unsigned short + +#define __subword_cmpxchg_body(type, size, ptr, guess, val) \ + ({ \ + unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \ + const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \ + const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \ + const unsigned int bgmask = ~(valmask << shift); \ + unsigned int oldword = *p; \ + type oldval = (oldword >> shift) & valmask; \ + if (__builtin_expect((oldval == guess), 1)) { \ + unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \ + oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \ + oldval = (oldword >> shift) & valmask; \ + } \ + oldval; \ + }) \ + #define __atomic_subword_cmpxchg(type, size) \ \ bool \ -__atomic_compare_exchange_##size(volatile type* ptr, type* guess, \ +__atomic_compare_exchange_##size(volatile type* ptr, type* guess_ptr, \ type val, bool weak __unused, int models, \ int modelf __unused) \ { \ pre_atomic_barrier(models); \ - unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \ - const int shift = ((unsigned long)ptr & 3UL) * 8; \ - const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \ - const unsigned int bgmask = ~(valmask << shift); \ - unsigned int oldword = *p; \ - type oldval = (oldword >> shift) & valmask; \ - if (__builtin_expect((oldval == *guess), 1)) { \ - unsigned int word = (oldword & bgmask) | ((val & valmask) << shift); \ - oldword = arch_atomic_val_compare_and_exchange(p, oldword, word); \ - oldval = (oldword >> shift) & valmask; \ - } \ + type guess = *guess_ptr; \ + type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \ post_atomic_barrier(models); \ - bool success = (oldval == *guess); \ - *guess = oldval; \ + bool success = (oldval == guess); \ + *guess_ptr = oldval; \ return success; \ } + __atomic_subword_cmpxchg (u8, 1) __atomic_subword_cmpxchg (u16, 2) + +#define __sync_subword_cmpxchg(type, size) \ + \ +type \ +__sync_val_compare_and_swap_##size(type* ptr, type guess, type val) \ +{ \ + arch_atomic_write_barrier(); \ + type oldval = __subword_cmpxchg_body(type, size, ptr, guess, val); \ + arch_atomic_read_barrier(); \ + return oldval; \ +} \ + \ +bool \ +__sync_bool_compare_and_swap_##size(type* ptr, type guess, type val) \ +{ \ + type oldval = __sync_val_compare_and_swap_##size(ptr, guess, val); \ + return oldval == guess; \ +} + +__sync_subword_cmpxchg (u8, 1) +__sync_subword_cmpxchg (u16, 2) + /* For the atomic-update subword methods, we use the same approach as above, but we retry until we succeed if the compare-and-exchange fails. */ -#define __atomic_subword(type, proto, top, expr, bottom) \ +#define __subword(type, proto, top, expr, bottom) \ proto \ { \ top \ unsigned int *p = (unsigned int *)((unsigned long)ptr & ~3UL); \ - const int shift = ((unsigned long)ptr & 3UL) * 8; \ + const int shift = BIT_OFFSET((unsigned long)ptr & 3UL, type); \ const unsigned int valmask = (1 << (sizeof(type) * 8)) - 1; \ const unsigned int bgmask = ~(valmask << shift); \ unsigned int oldword, xword = *p; \ @@ -184,42 +303,93 @@ proto \ } while (__builtin_expect(xword != oldword, 0)); \ bottom \ } + #define __atomic_subword_fetch(type, funcname, expr, retval) \ - __atomic_subword(type, \ - type __atomic_ ## funcname(volatile type *ptr, type i, int model), \ - pre_atomic_barrier(model);, \ - expr, \ - post_atomic_barrier(model); return retval;) + __subword(type, \ + type __atomic_ ## funcname(volatile type *ptr, type i, int model), \ + pre_atomic_barrier(model);, \ + expr, \ + post_atomic_barrier(model); return retval;) + __atomic_subword_fetch (u8, fetch_add_1, oldval + i, oldval) __atomic_subword_fetch (u8, fetch_sub_1, oldval - i, oldval) __atomic_subword_fetch (u8, fetch_or_1, oldval | i, oldval) __atomic_subword_fetch (u8, fetch_and_1, oldval & i, oldval) __atomic_subword_fetch (u8, fetch_xor_1, oldval ^ i, oldval) __atomic_subword_fetch (u8, fetch_nand_1, ~(oldval & i), oldval) + __atomic_subword_fetch (u16, fetch_add_2, oldval + i, oldval) __atomic_subword_fetch (u16, fetch_sub_2, oldval - i, oldval) __atomic_subword_fetch (u16, fetch_or_2, oldval | i, oldval) __atomic_subword_fetch (u16, fetch_and_2, oldval & i, oldval) __atomic_subword_fetch (u16, fetch_xor_2, oldval ^ i, oldval) __atomic_subword_fetch (u16, fetch_nand_2, ~(oldval & i), oldval) + __atomic_subword_fetch (u8, add_fetch_1, oldval + i, val) __atomic_subword_fetch (u8, sub_fetch_1, oldval - i, val) __atomic_subword_fetch (u8, or_fetch_1, oldval | i, val) __atomic_subword_fetch (u8, and_fetch_1, oldval & i, val) __atomic_subword_fetch (u8, xor_fetch_1, oldval ^ i, val) __atomic_subword_fetch (u8, nand_fetch_1, ~(oldval & i), val) + __atomic_subword_fetch (u16, add_fetch_2, oldval + i, val) __atomic_subword_fetch (u16, sub_fetch_2, oldval - i, val) __atomic_subword_fetch (u16, or_fetch_2, oldval | i, val) __atomic_subword_fetch (u16, and_fetch_2, oldval & i, val) __atomic_subword_fetch (u16, xor_fetch_2, oldval ^ i, val) __atomic_subword_fetch (u16, nand_fetch_2, ~(oldval & i), val) + +#define __sync_subword_fetch(type, funcname, expr, retval) \ + __subword(type, \ + type __sync_ ## funcname(type *ptr, type i), \ + arch_atomic_read_barrier();, \ + expr, \ + arch_atomic_write_barrier(); return retval;) + +__sync_subword_fetch (u8, fetch_and_add_1, oldval + i, oldval) +__sync_subword_fetch (u8, fetch_and_sub_1, oldval - i, oldval) +__sync_subword_fetch (u8, fetch_and_or_1, oldval | i, oldval) +__sync_subword_fetch (u8, fetch_and_and_1, oldval & i, oldval) +__sync_subword_fetch (u8, fetch_and_xor_1, oldval ^ i, oldval) +__sync_subword_fetch (u8, fetch_and_nand_1, ~(oldval & i), oldval) + +__sync_subword_fetch (u16, fetch_and_add_2, oldval + i, oldval) +__sync_subword_fetch (u16, fetch_and_sub_2, oldval - i, oldval) +__sync_subword_fetch (u16, fetch_and_or_2, oldval | i, oldval) +__sync_subword_fetch (u16, fetch_and_and_2, oldval & i, oldval) +__sync_subword_fetch (u16, fetch_and_xor_2, oldval ^ i, oldval) +__sync_subword_fetch (u16, fetch_and_nand_2, ~(oldval & i), oldval) + +__sync_subword_fetch (u8, add_and_fetch_1, oldval + i, val) +__sync_subword_fetch (u8, sub_and_fetch_1, oldval - i, val) +__sync_subword_fetch (u8, or_and_fetch_1, oldval | i, val) +__sync_subword_fetch (u8, and_and_fetch_1, oldval & i, val) +__sync_subword_fetch (u8, xor_and_fetch_1, oldval ^ i, val) +__sync_subword_fetch (u8, nand_and_fetch_1, ~(oldval & i), val) + +__sync_subword_fetch (u16, add_and_fetch_2, oldval + i, val) +__sync_subword_fetch (u16, sub_and_fetch_2, oldval - i, val) +__sync_subword_fetch (u16, or_and_fetch_2, oldval | i, val) +__sync_subword_fetch (u16, and_and_fetch_2, oldval & i, val) +__sync_subword_fetch (u16, xor_and_fetch_2, oldval ^ i, val) +__sync_subword_fetch (u16, nand_and_fetch_2, ~(oldval & i), val) + #define __atomic_subword_lock(type, size) \ - \ -__atomic_subword(type, \ - type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \ - pre_atomic_barrier(model);, \ - nval, \ - post_atomic_barrier(model); return oldval;) + __subword(type, \ + type __atomic_exchange_##size(volatile type* ptr, type nval, int model), \ + pre_atomic_barrier(model);, \ + nval, \ + post_atomic_barrier(model); return oldval;) + __atomic_subword_lock (u8, 1) __atomic_subword_lock (u16, 2) + +#define __sync_subword_lock(type, size) \ + __subword(type, \ + type __sync_lock_test_and_set_##size(type* ptr, type nval), \ + , \ + nval, \ + arch_atomic_acquire_barrier_value(oldval); return oldval;) + +__sync_subword_lock (u8, 1) +__sync_subword_lock (u16, 2) diff --git a/gcc-4_8-branch/libgo/go/go/build/build.go b/gcc-4_8-branch/libgo/go/go/build/build.go index cc89afb218d..59ddcefd741 100644 --- a/gcc-4_8-branch/libgo/go/go/build/build.go +++ b/gcc-4_8-branch/libgo/go/go/build/build.go @@ -429,7 +429,7 @@ func (ctxt *Context) Import(path string, srcDir string, mode ImportMode) (*Packa switch ctxt.Compiler { case "gccgo": dir, elem := pathpkg.Split(p.ImportPath) - pkga = "pkg/gccgo/" + dir + "lib" + elem + ".a" + pkga = "pkg/gccgo_" + ctxt.GOOS + "_" + ctxt.GOARCH + "/" + dir + "lib" + elem + ".a" case "gc": suffix := "" if ctxt.InstallSuffix != "" { diff --git a/gcc-4_8-branch/libgo/runtime/malloc.goc b/gcc-4_8-branch/libgo/runtime/malloc.goc index 8ccaa6b888c..f0871dd7eda 100644 --- a/gcc-4_8-branch/libgo/runtime/malloc.goc +++ b/gcc-4_8-branch/libgo/runtime/malloc.goc @@ -541,8 +541,7 @@ runtime_settype_flush(M *mp, bool sysalloc) // (Manually inlined copy of runtime_MHeap_Lookup) p = (uintptr)v>>PageShift; - if(sizeof(void*) == 8) - p -= (uintptr)runtime_mheap->arena_start >> PageShift; + p -= (uintptr)runtime_mheap->arena_start >> PageShift; s = runtime_mheap->map[p]; if(s->sizeclass == 0) { diff --git a/gcc-4_8-branch/libgo/runtime/mgc0.c b/gcc-4_8-branch/libgo/runtime/mgc0.c index c3b32111ca0..71dfaa0be82 100644 --- a/gcc-4_8-branch/libgo/runtime/mgc0.c +++ b/gcc-4_8-branch/libgo/runtime/mgc0.c @@ -174,7 +174,7 @@ static struct { Obj *roots; uint32 nroot; uint32 rootcap; -} work; +} work __attribute__((aligned(8))); enum { GC_DEFAULT_PTR = GC_NUM_INSTR, @@ -239,8 +239,7 @@ markonly(void *obj) // (Manually inlined copy of MHeap_LookupMaybe.) k = (uintptr)obj>>PageShift; x = k; - if(sizeof(void*) == 8) - x -= (uintptr)runtime_mheap->arena_start>>PageShift; + x -= (uintptr)runtime_mheap->arena_start>>PageShift; s = runtime_mheap->map[x]; if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse) return false; @@ -418,8 +417,7 @@ flushptrbuf(PtrTarget *ptrbuf, PtrTarget **ptrbufpos, Obj **_wp, Workbuf **_wbuf // (Manually inlined copy of MHeap_LookupMaybe.) k = (uintptr)obj>>PageShift; x = k; - if(sizeof(void*) == 8) - x -= (uintptr)arena_start>>PageShift; + x -= (uintptr)arena_start>>PageShift; s = runtime_mheap->map[x]; if(s == nil || k < s->start || k - s->start >= s->npages || s->state != MSpanInUse) continue; @@ -466,8 +464,7 @@ flushptrbuf(PtrTarget *ptrbuf, PtrTarget **ptrbufpos, Obj **_wp, Workbuf **_wbuf // Ask span about size class. // (Manually inlined copy of MHeap_Lookup.) x = (uintptr)obj >> PageShift; - if(sizeof(void*) == 8) - x -= (uintptr)arena_start>>PageShift; + x -= (uintptr)arena_start>>PageShift; s = runtime_mheap->map[x]; PREFETCH(obj); @@ -585,8 +582,7 @@ checkptr(void *obj, uintptr objti) if(t == nil) return; x = (uintptr)obj >> PageShift; - if(sizeof(void*) == 8) - x -= (uintptr)(runtime_mheap->arena_start)>>PageShift; + x -= (uintptr)(runtime_mheap->arena_start)>>PageShift; s = runtime_mheap->map[x]; objstart = (byte*)((uintptr)s->start<sizeclass != 0) { diff --git a/gcc-4_8-branch/libgo/runtime/mheap.c b/gcc-4_8-branch/libgo/runtime/mheap.c index b4d94b68559..af46bfba75c 100644 --- a/gcc-4_8-branch/libgo/runtime/mheap.c +++ b/gcc-4_8-branch/libgo/runtime/mheap.c @@ -150,8 +150,7 @@ HaveSpan: runtime_MSpan_Init(t, s->start + npage, s->npages - npage); s->npages = npage; p = t->start; - if(sizeof(void*) == 8) - p -= ((uintptr)h->arena_start>>PageShift); + p -= ((uintptr)h->arena_start>>PageShift); if(p > 0) h->map[p-1] = s; h->map[p] = t; @@ -169,8 +168,7 @@ HaveSpan: s->elemsize = (sizeclass==0 ? s->npages<types.compression = MTypes_Empty; p = s->start; - if(sizeof(void*) == 8) - p -= ((uintptr)h->arena_start>>PageShift); + p -= ((uintptr)h->arena_start>>PageShift); for(n=0; nmap[p+n] = s; return s; @@ -241,8 +239,7 @@ MHeap_Grow(MHeap *h, uintptr npage) mstats.mspan_sys = h->spanalloc.sys; runtime_MSpan_Init(s, (uintptr)v>>PageShift, ask>>PageShift); p = s->start; - if(sizeof(void*) == 8) - p -= ((uintptr)h->arena_start>>PageShift); + p -= ((uintptr)h->arena_start>>PageShift); h->map[p] = s; h->map[p + s->npages - 1] = s; s->state = MSpanInUse; @@ -259,8 +256,7 @@ runtime_MHeap_Lookup(MHeap *h, void *v) uintptr p; p = (uintptr)v; - if(sizeof(void*) == 8) - p -= (uintptr)h->arena_start; + p -= (uintptr)h->arena_start; return h->map[p >> PageShift]; } @@ -281,8 +277,7 @@ runtime_MHeap_LookupMaybe(MHeap *h, void *v) return nil; p = (uintptr)v>>PageShift; q = p; - if(sizeof(void*) == 8) - q -= (uintptr)h->arena_start >> PageShift; + q -= (uintptr)h->arena_start >> PageShift; s = h->map[q]; if(s == nil || p < s->start || p - s->start >= s->npages) return nil; @@ -332,8 +327,7 @@ MHeap_FreeLocked(MHeap *h, MSpan *s) // Coalesce with earlier, later spans. p = s->start; - if(sizeof(void*) == 8) - p -= (uintptr)h->arena_start >> PageShift; + p -= (uintptr)h->arena_start >> PageShift; if(p > 0 && (t = h->map[p-1]) != nil && t->state != MSpanInUse) { tp = (uintptr*)(t->start< + + Core DR 475 + PR c++/41174 + PR c++/59224 + * libsupc++/eh_throw.cc (__cxa_throw): Set uncaughtExceptions. + * libsupc++/eh_alloc.cc (__cxa_allocate_dependent_exception) + (__cxa_allocate_exception): Don't set it here. + 2013-12-15 H.J. Lu * config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt: Update. diff --git a/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_alloc.cc b/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_alloc.cc index 9b3fb4db1ce..2fdc068aeb0 100644 --- a/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_alloc.cc +++ b/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_alloc.cc @@ -129,12 +129,6 @@ __cxxabiv1::__cxa_allocate_exception(std::size_t thrown_size) _GLIBCXX_NOTHROW std::terminate (); } - // We have an uncaught exception as soon as we allocate memory. This - // yields uncaught_exception() true during the copy-constructor that - // initializes the exception object. See Issue 475. - __cxa_eh_globals *globals = __cxa_get_globals (); - globals->uncaughtExceptions += 1; - memset (ret, 0, sizeof (__cxa_refcounted_exception)); return (void *)((char *)ret + sizeof (__cxa_refcounted_exception)); @@ -191,12 +185,6 @@ __cxxabiv1::__cxa_allocate_dependent_exception() _GLIBCXX_NOTHROW std::terminate (); } - // We have an uncaught exception as soon as we allocate memory. This - // yields uncaught_exception() true during the copy-constructor that - // initializes the exception object. See Issue 475. - __cxa_eh_globals *globals = __cxa_get_globals (); - globals->uncaughtExceptions += 1; - memset (ret, 0, sizeof (__cxa_dependent_exception)); return ret; diff --git a/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_throw.cc b/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_throw.cc index a79a025af19..1d6a2df5007 100644 --- a/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_throw.cc +++ b/gcc-4_8-branch/libstdc++-v3/libsupc++/eh_throw.cc @@ -62,6 +62,9 @@ __cxxabiv1::__cxa_throw (void *obj, std::type_info *tinfo, { PROBE2 (throw, obj, tinfo); + __cxa_eh_globals *globals = __cxa_get_globals (); + globals->uncaughtExceptions += 1; + // Definitely a primary. __cxa_refcounted_exception *header = __get_refcounted_exception_header_from_obj (obj); diff --git a/gcc-4_8-branch/libstdc++-v3/testsuite/20_util/bind/57899.cc b/gcc-4_8-branch/libstdc++-v3/testsuite/20_util/bind/57899.cc new file mode 100644 index 00000000000..d46d53e83fa --- /dev/null +++ b/gcc-4_8-branch/libstdc++-v3/testsuite/20_util/bind/57899.cc @@ -0,0 +1,48 @@ +// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// . + +// 20.7.11 Function template bind + +// PR c++/57899 +// { dg-do compile } +// { dg-options -std=c++11 } + +#include +using std::bind; +using std::placeholders::_1; + +struct S { int i; }; + +struct P { S s; }; + +struct get_s +{ + const S& operator()(const P& p) const { return p.s; } +} gs; + +int gi(const S& s) { return s.i; } + +bool cmp(int, int) { return true; } + +int main() +{ + P p{}; + auto f1 = bind(gs, _1); + auto f2 = bind(gi, f1); + auto f3 = bind(cmp, f2, 5); + f3(p); +} diff --git a/gcc-4_8-branch/maintainer-scripts/ChangeLog b/gcc-4_8-branch/maintainer-scripts/ChangeLog index 82c25b3208f..c469a72cdfc 100644 --- a/gcc-4_8-branch/maintainer-scripts/ChangeLog +++ b/gcc-4_8-branch/maintainer-scripts/ChangeLog @@ -1,3 +1,9 @@ +2014-02-01 Dmitry Gorbachev + + PR other/56653 + * gcc_release: Avoid printing empty line to generated MD5SUMS files. + Bump copyright year. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4_8-branch/maintainer-scripts/gcc_release b/gcc-4_8-branch/maintainer-scripts/gcc_release index ee7822bf39d..c20b410bd22 100755 --- a/gcc-4_8-branch/maintainer-scripts/gcc_release +++ b/gcc-4_8-branch/maintainer-scripts/gcc_release @@ -9,7 +9,7 @@ # Contents: # Script to create a GCC release. # -# Copyright (c) 2001, 2002, 2006, 2009, 2010, 2011 Free Software Foundation. +# Copyright (c) 2001-2014 Free Software Foundation. # # This file is part of GCC. # @@ -213,7 +213,7 @@ EOF # # Suggested usage: # md5sum -c MD5SUMS | grep -v \"OK$\" -" > MD5SUMS +#" > MD5SUMS find . -type f | sed -e 's:^\./::' -e '/MD5SUMS/d' | -- 2.11.4.GIT