From f1ca65797f0eded348c3a93d697d44fc1e529f92 Mon Sep 17 00:00:00 2001 From: clyon Date: Thu, 5 Sep 2013 12:38:03 +0000 Subject: [PATCH] gcc/ 2013-09-05 Christophe Lyon Backport from trunk r199527,199792,199814. 2013-05-31 Kyrylo Tkachov PR target/56315 * config/arm/arm.c (const_ok_for_dimode_op): Handle IOR. * config/arm/arm.md (*iordi3_insn): Change to insn_and_split. * config/arm/neon.md (iordi3_neon): Remove. (neon_vorr): Generate iordi3 instead of iordi3_neon. * config/arm/predicates.md (imm_for_neon_logic_operand): Move to earlier in the file. (neon_logic_op2): Likewise. (arm_iordi_operand_neon): New predicate. 2013-06-07 Kyrylo Tkachov * config/arm/constraints.md (Df): New constraint. * config/arm/arm.md (iordi3_insn): Use Df constraint instead of De. Correct length attribute for last two alternatives. 2013-06-07 Kyrylo Tkachov PR target/56315 * config/arm/arm.md (*xordi3_insn): Change to insn_and_split. (xordi3): Change operand 2 constraint to arm_xordi_operand. * config/arm/arm.c (const_ok_for_dimode_op): Handle XOR. * config/arm/constraints.md (Dg): New constraint. * config/arm/neon.md (xordi3_neon): Remove. (neon_veor): Generate xordi3 instead of xordi3_neon. * config/arm/predicates.md (arm_xordi_operand): New predicate. gcc/testsuite/ 2013-09-05 Christophe Lyon Backport from trunk r199527,199814,201435. 2013-05-31 Kyrylo Tkachov PR target/56315 * gcc.target/arm/iordi3-opt.c: New test. 2013-06-07 Kyrylo Tkachov PR target/56315 * gcc.target/arm/xordi3-opt.c: New test. 2013-08-02 Kyrylo Tkachov * gcc.target/arm/neon-for-64bits-2.c: Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro@202280 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc-4_8-branch/gcc/ChangeLog.linaro | 32 +++++++ gcc-4_8-branch/gcc/config/arm/arm.c | 2 + gcc-4_8-branch/gcc/config/arm/arm.md | 97 ++++++++++++++++++---- gcc-4_8-branch/gcc/config/arm/constraints.md | 12 +++ gcc-4_8-branch/gcc/config/arm/neon.md | 42 +--------- gcc-4_8-branch/gcc/config/arm/predicates.md | 33 +++++--- gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro | 17 ++++ .../gcc/testsuite/gcc.target/arm/iordi3-opt.c | 9 ++ .../testsuite/gcc.target/arm/neon-for-64bits-2.c | 57 ------------- .../gcc/testsuite/gcc.target/arm/xordi3-opt.c | 9 ++ 10 files changed, 185 insertions(+), 125 deletions(-) create mode 100644 gcc-4_8-branch/gcc/testsuite/gcc.target/arm/iordi3-opt.c delete mode 100644 gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c create mode 100644 gcc-4_8-branch/gcc/testsuite/gcc.target/arm/xordi3-opt.c diff --git a/gcc-4_8-branch/gcc/ChangeLog.linaro b/gcc-4_8-branch/gcc/ChangeLog.linaro index 6c44f970937..e6d92a320d1 100644 --- a/gcc-4_8-branch/gcc/ChangeLog.linaro +++ b/gcc-4_8-branch/gcc/ChangeLog.linaro @@ -1,5 +1,37 @@ 2013-09-05 Christophe Lyon + Backport from trunk r199527,199792,199814. + 2013-05-31 Kyrylo Tkachov + + PR target/56315 + * config/arm/arm.c (const_ok_for_dimode_op): Handle IOR. + * config/arm/arm.md (*iordi3_insn): Change to insn_and_split. + * config/arm/neon.md (iordi3_neon): Remove. + (neon_vorr): Generate iordi3 instead of iordi3_neon. + * config/arm/predicates.md (imm_for_neon_logic_operand): + Move to earlier in the file. + (neon_logic_op2): Likewise. + (arm_iordi_operand_neon): New predicate. + + 2013-06-07 Kyrylo Tkachov + + * config/arm/constraints.md (Df): New constraint. + * config/arm/arm.md (iordi3_insn): Use Df constraint instead of De. + Correct length attribute for last two alternatives. + + 2013-06-07 Kyrylo Tkachov + + PR target/56315 + * config/arm/arm.md (*xordi3_insn): Change to insn_and_split. + (xordi3): Change operand 2 constraint to arm_xordi_operand. + * config/arm/arm.c (const_ok_for_dimode_op): Handle XOR. + * config/arm/constraints.md (Dg): New constraint. + * config/arm/neon.md (xordi3_neon): Remove. + (neon_veor): Generate xordi3 instead of xordi3_neon. + * config/arm/predicates.md (arm_xordi_operand): New predicate. + +2013-09-05 Christophe Lyon + Backport from trunk r201599. 2013-08-08 Richard Earnshaw diff --git a/gcc-4_8-branch/gcc/config/arm/arm.c b/gcc-4_8-branch/gcc/config/arm/arm.c index 1462dbef6c5..cdb674c925a 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.c +++ b/gcc-4_8-branch/gcc/config/arm/arm.c @@ -2685,6 +2685,8 @@ const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code) switch (code) { case AND: + case IOR: + case XOR: return (const_ok_for_op (hi_val, code) || hi_val == 0xFFFFFFFF) && (const_ok_for_op (lo_val, code) || lo_val == 0xFFFFFFFF); case PLUS: diff --git a/gcc-4_8-branch/gcc/config/arm/arm.md b/gcc-4_8-branch/gcc/config/arm/arm.md index 9773569d417..2ac83254939 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.md +++ b/gcc-4_8-branch/gcc/config/arm/arm.md @@ -3234,14 +3234,47 @@ "" ) -(define_insn "*iordi3_insn" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") - (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" - "#" - [(set_attr "length" "8") - (set_attr "predicable" "yes")] +(define_insn_and_split "*iordi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w") + (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0") + (match_operand:DI 2 "arm_iordi_operand_neon" "w ,Dl,r ,r ,Df,Df,w ,Dl")))] + "TARGET_32BIT && !TARGET_IWMMXT" + { + switch (which_alternative) + { + case 0: /* fall through */ + case 6: return "vorr\t%P0, %P1, %P2"; + case 1: /* fall through */ + case 7: return neon_output_logic_immediate ("vorr", &operands[2], + DImode, 0, VALID_NEON_QREG_MODE (DImode)); + case 2: + case 3: + case 4: + case 5: + return "#"; + default: gcc_unreachable (); + } + } + "TARGET_32BIT && !TARGET_IWMMXT && reload_completed + && !(IS_VFP_REGNUM (REGNO (operands[0])))" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 5) (match_dup 6))] + " + { + operands[3] = gen_lowpart (SImode, operands[0]); + operands[5] = gen_highpart (SImode, operands[0]); + + operands[4] = simplify_gen_binary (IOR, SImode, + gen_lowpart (SImode, operands[1]), + gen_lowpart (SImode, operands[2])); + operands[6] = simplify_gen_binary (IOR, SImode, + gen_highpart (SImode, operands[1]), + gen_highpart_mode (SImode, DImode, operands[2])); + + }" + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") + (set_attr "length" "*,*,8,8,8,8,*,*") + (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] ) (define_insn "*iordi_zesidi_di" @@ -3375,19 +3408,49 @@ (define_expand "xordi3" [(set (match_operand:DI 0 "s_register_operand" "") (xor:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "s_register_operand" "")))] + (match_operand:DI 2 "arm_xordi_operand" "")))] "TARGET_32BIT" "" ) -(define_insn "*xordi3_insn" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") - (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" - "#" - [(set_attr "length" "8") - (set_attr "predicable" "yes")] +(define_insn_and_split "*xordi3_insn" + [(set (match_operand:DI 0 "s_register_operand" "=w,&r,&r,&r,&r,?w") + (xor:DI (match_operand:DI 1 "s_register_operand" "w ,%0,r ,0 ,r ,w") + (match_operand:DI 2 "arm_xordi_operand" "w ,r ,r ,Dg,Dg,w")))] + "TARGET_32BIT && !TARGET_IWMMXT" +{ + switch (which_alternative) + { + case 1: + case 2: + case 3: + case 4: /* fall through */ + return "#"; + case 0: /* fall through */ + case 5: return "veor\t%P0, %P1, %P2"; + default: gcc_unreachable (); + } +} + "TARGET_32BIT && !TARGET_IWMMXT && reload_completed + && !(IS_VFP_REGNUM (REGNO (operands[0])))" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 5) (match_dup 6))] + " + { + operands[3] = gen_lowpart (SImode, operands[0]); + operands[5] = gen_highpart (SImode, operands[0]); + + operands[4] = simplify_gen_binary (XOR, SImode, + gen_lowpart (SImode, operands[1]), + gen_lowpart (SImode, operands[2])); + operands[6] = simplify_gen_binary (XOR, SImode, + gen_highpart (SImode, operands[1]), + gen_highpart_mode (SImode, DImode, operands[2])); + + }" + [(set_attr "length" "*,8,8,8,8,*") + (set_attr "neon_type" "neon_int_1,*,*,*,*,neon_int_1") + (set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")] ) (define_insn "*xordi_zesidi_di" diff --git a/gcc-4_8-branch/gcc/config/arm/constraints.md b/gcc-4_8-branch/gcc/config/arm/constraints.md index 676119359f2..de7f4c20d5f 100644 --- a/gcc-4_8-branch/gcc/config/arm/constraints.md +++ b/gcc-4_8-branch/gcc/config/arm/constraints.md @@ -260,6 +260,18 @@ (and (match_code "const_int") (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)"))) +(define_constraint "Df" + "@internal + In ARM/Thumb-2 state a const_int that can be used by insn iordi." + (and (match_code "const_int") + (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)"))) + +(define_constraint "Dg" + "@internal + In ARM/Thumb-2 state a const_int that can be used by insn xordi." + (and (match_code "const_int") + (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)"))) + (define_constraint "Di" "@internal In ARM/Thumb-2 state a const_int or const_double where both the high diff --git a/gcc-4_8-branch/gcc/config/arm/neon.md b/gcc-4_8-branch/gcc/config/arm/neon.md index fa82aeec92a..0e0cde2d85e 100644 --- a/gcc-4_8-branch/gcc/config/arm/neon.md +++ b/gcc-4_8-branch/gcc/config/arm/neon.md @@ -679,29 +679,6 @@ [(set_attr "neon_type" "neon_int_1")] ) -(define_insn "iordi3_neon" - [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w") - (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0") - (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r,w,Dl")))] - "TARGET_NEON" -{ - switch (which_alternative) - { - case 0: /* fall through */ - case 4: return "vorr\t%P0, %P1, %P2"; - case 1: /* fall through */ - case 5: return neon_output_logic_immediate ("vorr", &operands[2], - DImode, 0, VALID_NEON_QREG_MODE (DImode)); - case 2: return "#"; - case 3: return "#"; - default: gcc_unreachable (); - } -} - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") - (set_attr "length" "*,*,8,8,*,*") - (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] -) - ;; The concrete forms of the Neon immediate-logic instructions are vbic and ;; vorr. We support the pseudo-instruction vand instead, because that ;; corresponds to the canonical form the middle-end expects to use for @@ -805,21 +782,6 @@ [(set_attr "neon_type" "neon_int_1")] ) -(define_insn "xordi3_neon" - [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w") - (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r,w") - (match_operand:DI 2 "s_register_operand" "w,r,r,w")))] - "TARGET_NEON" - "@ - veor\t%P0, %P1, %P2 - # - # - veor\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") - (set_attr "length" "*,8,8,*") - (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] -) - (define_insn "one_cmpl2" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] @@ -5618,7 +5580,7 @@ (match_operand:SI 3 "immediate_operand" "")] "TARGET_NEON" { - emit_insn (gen_ior3 (operands[0], operands[1], operands[2])); + emit_insn (gen_ior3 (operands[0], operands[1], operands[2])); DONE; }) @@ -5629,7 +5591,7 @@ (match_operand:SI 3 "immediate_operand" "")] "TARGET_NEON" { - emit_insn (gen_xor3 (operands[0], operands[1], operands[2])); + emit_insn (gen_xor3 (operands[0], operands[1], operands[2])); DONE; }) diff --git a/gcc-4_8-branch/gcc/config/arm/predicates.md b/gcc-4_8-branch/gcc/config/arm/predicates.md index 9656e12306d..bc5cc831d5d 100644 --- a/gcc-4_8-branch/gcc/config/arm/predicates.md +++ b/gcc-4_8-branch/gcc/config/arm/predicates.md @@ -42,6 +42,17 @@ (ior (match_operand 0 "imm_for_neon_inv_logic_operand") (match_operand 0 "s_register_operand"))) +(define_predicate "imm_for_neon_logic_operand" + (match_code "const_vector") +{ + return (TARGET_NEON + && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); +}) + +(define_predicate "neon_logic_op2" + (ior (match_operand 0 "imm_for_neon_logic_operand") + (match_operand 0 "s_register_operand"))) + ;; Any hard register. (define_predicate "arm_hard_register_operand" (match_code "reg") @@ -162,6 +173,17 @@ (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) (match_operand 0 "neon_inv_logic_op2"))) +(define_predicate "arm_iordi_operand_neon" + (ior (match_operand 0 "s_register_operand") + (and (match_code "const_int") + (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")) + (match_operand 0 "neon_logic_op2"))) + +(define_predicate "arm_xordi_operand" + (ior (match_operand 0 "s_register_operand") + (and (match_code "const_int") + (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) + (define_predicate "arm_adddi_operand" (ior (match_operand 0 "s_register_operand") (and (match_code "const_int") @@ -541,17 +563,6 @@ (ior (match_operand 0 "s_register_operand") (match_operand 0 "imm_for_neon_rshift_operand"))) -(define_predicate "imm_for_neon_logic_operand" - (match_code "const_vector") -{ - return (TARGET_NEON - && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); -}) - -(define_predicate "neon_logic_op2" - (ior (match_operand 0 "imm_for_neon_logic_operand") - (match_operand 0 "s_register_operand"))) - ;; Predicates for named expanders that overlap multiple ISAs. (define_predicate "cmpdi_operand" diff --git a/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro b/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro index 296cc75c093..5b0ea61ab0d 100644 --- a/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro +++ b/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro @@ -1,5 +1,22 @@ 2013-09-05 Christophe Lyon + Backport from trunk r199527,199814,201435. + 2013-05-31 Kyrylo Tkachov + + PR target/56315 + * gcc.target/arm/iordi3-opt.c: New test. + + 2013-06-07 Kyrylo Tkachov + + PR target/56315 + * gcc.target/arm/xordi3-opt.c: New test. + + 2013-08-02 Kyrylo Tkachov + + * gcc.target/arm/neon-for-64bits-2.c: Delete. + +2013-09-05 Christophe Lyon + Backport from trunk r201730,201731. 2013-08-14 Janis Johnson diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/iordi3-opt.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/iordi3-opt.c new file mode 100644 index 00000000000..b3f465b7492 --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/iordi3-opt.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +unsigned long long or64 (unsigned long long input) +{ + return input | 0x200000004ULL; +} + +/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c deleted file mode 100644 index 035bfb77a37..00000000000 --- a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c +++ /dev/null @@ -1,57 +0,0 @@ -/* Check that Neon is used to handle 64-bits scalar operations. */ - -/* { dg-do compile } */ -/* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mneon-for-64bits" } */ -/* { dg-add-options arm_neon } */ - -typedef long long i64; -typedef unsigned long long u64; -typedef unsigned int u32; -typedef int i32; - -/* Unary operators */ -#define UNARY_OP(name, op) \ - void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } - -/* Binary operators */ -#define BINARY_OP(name, op) \ - void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } - -/* Unsigned shift */ -#define SHIFT_U(name, op, amount) \ - void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } - -/* Signed shift */ -#define SHIFT_S(name, op, amount) \ - void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } - -UNARY_OP(not, ~) - -BINARY_OP(add, +) -BINARY_OP(sub, -) -BINARY_OP(and, &) -BINARY_OP(or, |) -BINARY_OP(xor, ^) - -SHIFT_U(right1, >>, 1) -SHIFT_U(right2, >>, 2) -SHIFT_U(right5, >>, 5) -SHIFT_U(rightn, >>, c) - -SHIFT_S(right1, >>, 1) -SHIFT_S(right2, >>, 2) -SHIFT_S(right5, >>, 5) -SHIFT_S(rightn, >>, c) - -/* { dg-final {scan-assembler-times "vmvn" 1} } */ -/* Two vadd: 1 in unary_not, 1 in binary_add */ -/* { dg-final {scan-assembler-times "vadd" 2} } */ -/* { dg-final {scan-assembler-times "vsub" 1} } */ -/* { dg-final {scan-assembler-times "vand" 1} } */ -/* { dg-final {scan-assembler-times "vorr" 1} } */ -/* { dg-final {scan-assembler-times "veor" 1} } */ -/* 6 vshr for right shifts by constant, and variable right shift uses - vshl with a negative amount in register. */ -/* { dg-final {scan-assembler-times "vshr" 6} } */ -/* { dg-final {scan-assembler-times "vshl" 2} } */ diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/xordi3-opt.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/xordi3-opt.c new file mode 100644 index 00000000000..7e031c3af2c --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/xordi3-opt.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +unsigned long long xor64 (unsigned long long input) +{ + return input ^ 0x200000004ULL; +} + +/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ -- 2.11.4.GIT