From f036380a4040f920471fd0177421c254bf907074 Mon Sep 17 00:00:00 2001 From: jiwang Date: Thu, 14 May 2015 13:35:30 +0000 Subject: [PATCH] [AArch64] Use conditional negate for abs 2015-05-14 Wilco Dijkstra gcc/ * config/aarch64/aarch64.md (absdi2): Optimize abs expansion. (csneg3_insn): Enable expansion of pattern. gcc/testsuite/ * gcc.target/aarch64/abs_1.c (abs64): Update test for new abs expansion. (abs64_in_dreg): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223197 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64.md | 32 +++++++------------------------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/abs_1.c | 5 ++--- 4 files changed, 19 insertions(+), 28 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1b78ca32e5f..ba35c777c7f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-05-14 Wilco Dijkstra + + * config/aarch64/aarch64.md (absdi2): Optimize abs expansion. + (csneg3_insn): Enable expansion of pattern. + 2015-05-14 Nick Clifton * config/rl78/rl78.c (rl78_select_section): Select the correct diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1dbadc0c5a4..4817fae5d32 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2182,34 +2182,16 @@ [(set_attr "type" "alu_ext")] ) -(define_insn_and_split "absdi2" - [(set (match_operand:DI 0 "register_operand" "=&r,w") - (abs:DI (match_operand:DI 1 "register_operand" "r,w")))] +(define_expand "abs2" + [(match_operand:GPI 0 "register_operand" "") + (match_operand:GPI 1 "register_operand" "")] "" - "@ - # - abs\\t%d0, %d1" - "reload_completed - && GP_REGNUM_P (REGNO (operands[0])) - && GP_REGNUM_P (REGNO (operands[1]))" - [(const_int 0)] { - emit_insn (gen_rtx_SET (operands[0], - gen_rtx_XOR (DImode, - gen_rtx_ASHIFTRT (DImode, - operands[1], - GEN_INT (63)), - operands[1]))); - emit_insn (gen_rtx_SET (operands[0], - gen_rtx_MINUS (DImode, - operands[0], - gen_rtx_ASHIFTRT (DImode, - operands[1], - GEN_INT (63))))); + rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); + rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx); + emit_insn (gen_csneg3_insn (operands[0], x, operands[1], operands[1])); DONE; } - [(set_attr "type" "alu_sreg") - (set_attr "simd" "no,yes")] ) (define_insn "neg2" @@ -2888,7 +2870,7 @@ [(set_attr "type" "csel")] ) -(define_insn "*csneg3_insn" +(define_insn "csneg3_insn" [(set (match_operand:GPI 0 "register_operand" "=r") (if_then_else:GPI (match_operand 1 "aarch64_comparison_operation" "") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ef46d503bf5..504dc075ef1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-05-14 Wilco Dijkstra + + * gcc.target/aarch64/abs_1.c (abs64): Update test for new abs expansion. + (abs64_in_dreg): Likewise. + 2015-05-14 Marek Polacek PR c/66066 diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc/testsuite/gcc.target/aarch64/abs_1.c index 938bc84ed95..11f1095199c 100644 --- a/gcc/testsuite/gcc.target/aarch64/abs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c @@ -7,15 +7,14 @@ extern void abort (void); long long abs64 (long long a) { - /* { dg-final { scan-assembler "eor\t" } } */ - /* { dg-final { scan-assembler "sub\t" } } */ + /* { dg-final { scan-assembler "csneg\t" } } */ return llabs (a); } long long abs64_in_dreg (long long a) { - /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */ + /* { dg-final { scan-assembler "csneg\t" } } */ register long long x asm ("d8") = a; register long long y asm ("d9"); asm volatile ("" : : "w" (x)); -- 2.11.4.GIT