From efcf68d51e430dfde1562d4453721eca017e89cf Mon Sep 17 00:00:00 2001 From: meissner Date: Thu, 24 Aug 2017 19:28:07 +0000 Subject: [PATCH] [gcc] 2017-08-24 Michael Meissner * config/rs6000/rs6000.opt (-mpower9-dform-scalar): Delete undocumented switches. (-mpower9-dform-vector): Likewise. (-mpower9-dform): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Update comments to delete references to -mpower9-dform* switches. * config/rs6000/predicates.md (vsx_quad_dform_memory_operand): Delete reference to -mpower9-dform* switches, test for -mpower9-vector instead. * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise. (OTHER_P9_VECTOR_MASKS): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Change tests against -mpower9-dform* to -mpower9-vector. Delete code that checked for -mpower9-dform* consistancy with other options. Add test for -mpower9-misc to enable other power9 switches. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_emit_prologue): Likewise. (rs6000_emit_epilogue): Likewise. (rs6000_opt_masks): Delete -mpower9-dform-{scalar,vector}. (rs6000_disable_incompatiable_switches): Delete -mpower9-dform. (emit_fusion_p9_load): Change tests for -mpower9-dform-scalar -mpower9-vector. (emit_fusion_p9_store): Likewise. * config/rs6000/rs6000.h (TARGET_P9_DFORM_SCALAR): Delete resetting these macros if the assembler does not support ISA 3.0 instructions. (TARGET_P9_DFORM_VECTOR): Likewise. * config/rs6000/rs6000.md (peepholes to optimize altivec memory): Change to use -mpower9-vector instead of -mpower9-dform-scalar. [gcc/testsuite] 2017-08-24 Michael Meissner * gcc.target/powerpc/dform-1.c: Delete -mpower9-dform* options. * gcc.target/powerpc/dform-2.c: Likewise. * gcc.target/powerpc/dform-3.c: Likewise. * gcc.target/powerpc/pr71656-1.c: Likewise. * gcc.target/powerpc/pr71656-2.c: Likewise. * gcc.target/powerpc/pr80103-1.c: Likewise. * gcc.target/powerpc/pr80098-1.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@251341 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/config/rs6000/predicates.md | 2 +- gcc/config/rs6000/rs6000-c.c | 7 +- gcc/config/rs6000/rs6000-cpus.def | 6 -- gcc/config/rs6000/rs6000.c | 118 ++++----------------------- gcc/config/rs6000/rs6000.h | 4 - gcc/config/rs6000/rs6000.md | 4 +- gcc/config/rs6000/rs6000.opt | 12 --- gcc/testsuite/gcc.target/powerpc/dform-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/dform-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/dform-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71656-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/pr71656-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/pr80098-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/pr80103-1.c | 5 +- 14 files changed, 30 insertions(+), 145 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 466f9131aa0..63af03baa6f 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -827,7 +827,7 @@ (define_predicate "vsx_quad_dform_memory_operand" (match_code "mem") { - if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) + if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) return false; return quad_address_p (XEXP (op, 0), mode, false); diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 16328fcaaaa..1c9a8db7c62 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -430,8 +430,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically turned on in the following condition: - 1. TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR are enabled - and OPTION_MASK_DIRECT_MOVE is not explicitly disabled. + 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not + explicitly disabled. Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to have been turned on explicitly. Note that the OPTION_MASK_DIRECT_MOVE flag is automatically @@ -545,8 +545,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, also considered to have been turned off explicitly. Note that the OPTION_MASK_P9_VECTOR is automatically turned on in the following conditions: - 1. If TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR and - OPTION_MASK_P9_VECTOR was not turned off explicitly. + 1. If TARGET_P9_MINMAX was turned on explicitly. Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to have been turned on explicitly. */ if ((flags & OPTION_MASK_P9_VECTOR) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index cd6e93d9b8d..d4a8b94326a 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -61,8 +61,6 @@ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_FUSION \ - | OPTION_MASK_P9_DFORM_SCALAR \ - | OPTION_MASK_P9_DFORM_VECTOR \ | OPTION_MASK_P9_MINMAX \ | OPTION_MASK_P9_MISC \ | OPTION_MASK_P9_VECTOR) @@ -76,8 +74,6 @@ /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ - | OPTION_MASK_P9_DFORM_SCALAR \ - | OPTION_MASK_P9_DFORM_VECTOR \ | OPTION_MASK_P9_MINMAX) /* Flags that need to be turned off if -mno-power8-vector. */ @@ -127,8 +123,6 @@ | OPTION_MASK_NO_UPDATE \ | OPTION_MASK_P8_FUSION \ | OPTION_MASK_P8_VECTOR \ - | OPTION_MASK_P9_DFORM_SCALAR \ - | OPTION_MASK_P9_DFORM_VECTOR \ | OPTION_MASK_P9_FUSION \ | OPTION_MASK_P9_MINMAX \ | OPTION_MASK_P9_MISC \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 33581d019d8..9ff73ec4213 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2926,8 +2926,7 @@ rs6000_setup_reg_addr_masks (void) && (rc == RELOAD_REG_GPR || ((msize == 8 || m2 == SFmode) && (rc == RELOAD_REG_FPR - || (rc == RELOAD_REG_VMX - && TARGET_P9_DFORM_SCALAR))))) + || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) addr_mask |= RELOAD_REG_OFFSET; /* VSX registers can do REG+OFFSET addresssing if ISA 3.0 @@ -2935,7 +2934,7 @@ rs6000_setup_reg_addr_masks (void) only 12-bits. While GPRs can handle the full offset range, VSX registers can only handle the restricted range. */ else if ((addr_mask != 0) && !indexed_only_p - && msize == 16 && TARGET_P9_DFORM_VECTOR + && msize == 16 && TARGET_P9_VECTOR && (ALTIVEC_OR_VSX_VECTOR_MODE (m2) || (m2 == TImode && TARGET_VSX))) { @@ -3255,13 +3254,14 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */ } - /* Support for new D-form instructions. */ - if (TARGET_P9_DFORM_SCALAR) - rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; - - /* Support for ISA 3.0 (power9) vectors. */ if (TARGET_P9_VECTOR) - rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS; + { + /* Support for new D-form instructions. */ + rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; + + /* Support for ISA 3.0 (power9) vectors. */ + rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS; + } /* Support for new direct moves (ISA 3.0 + 64bit). */ if (TARGET_DIRECT_MOVE_128) @@ -3542,7 +3542,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load; reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store; - if (rtype == RELOAD_REG_FPR && TARGET_P9_DFORM_SCALAR) + if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR) { reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX] = addis_insns[i].load; @@ -4239,8 +4239,7 @@ rs6000_option_override_internal (bool global_init_p) /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-