From ee9da432b6cb3df2ba026dc66aa8a41b99512db5 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Wed, 29 Apr 2015 10:13:36 +0000 Subject: [PATCH] [ARM]Remove vec_shr and vec_shr optabs * config/arm/neon.md (vec_shl, vec_shr): Remove. From-SVN: r222568 --- gcc/ChangeLog | 4 ++++ gcc/config/arm/neon.md | 65 -------------------------------------------------- 2 files changed, 4 insertions(+), 65 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1e05574df9b..9afd56eed7b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2015-04-29 Alan Lawrence + + * config/arm/neon.md (vec_shl, vec_shr): Remove. + 2015-04-29 Tom de Vries PR tree-optimization/65893 diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index a48c39ba118..654d9d5c1aa 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1194,71 +1194,6 @@ [(set_attr "type" "neon_add_widen")] ) -;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit -;; shift-count granularity. That's good enough for the middle-end's current -;; needs. - -;; Note that it's not safe to perform such an operation in big-endian mode, -;; due to element-ordering issues. - -(define_expand "vec_shr_" - [(match_operand:VDQ 0 "s_register_operand" "") - (match_operand:VDQ 1 "s_register_operand" "") - (match_operand:SI 2 "const_multiple_of_8_operand" "")] - "TARGET_NEON && !BYTES_BIG_ENDIAN" -{ - rtx zero_reg; - HOST_WIDE_INT num_bits = INTVAL (operands[2]); - const int width = GET_MODE_BITSIZE (mode); - const machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode; - rtx (*gen_ext) (rtx, rtx, rtx, rtx) = - (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi; - - if (num_bits == width) - { - emit_move_insn (operands[0], operands[1]); - DONE; - } - - zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode)); - operands[0] = gen_lowpart (bvecmode, operands[0]); - operands[1] = gen_lowpart (bvecmode, operands[1]); - - emit_insn (gen_ext (operands[0], operands[1], zero_reg, - GEN_INT (num_bits / BITS_PER_UNIT))); - DONE; -}) - -(define_expand "vec_shl_" - [(match_operand:VDQ 0 "s_register_operand" "") - (match_operand:VDQ 1 "s_register_operand" "") - (match_operand:SI 2 "const_multiple_of_8_operand" "")] - "TARGET_NEON && !BYTES_BIG_ENDIAN" -{ - rtx zero_reg; - HOST_WIDE_INT num_bits = INTVAL (operands[2]); - const int width = GET_MODE_BITSIZE (mode); - const machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode; - rtx (*gen_ext) (rtx, rtx, rtx, rtx) = - (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi; - - if (num_bits == 0) - { - emit_move_insn (operands[0], CONST0_RTX (mode)); - DONE; - } - - num_bits = width - num_bits; - - zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode)); - operands[0] = gen_lowpart (bvecmode, operands[0]); - operands[1] = gen_lowpart (bvecmode, operands[1]); - - emit_insn (gen_ext (operands[0], zero_reg, operands[1], - GEN_INT (num_bits / BITS_PER_UNIT))); - DONE; -}) - ;; Helpers for quad-word reduction operations ; Add (or smin, smax...) the low N/2 elements of the N-element vector -- 2.11.4.GIT