From e8185ed3085a3b7bf3ace3ce5950f0090388d731 Mon Sep 17 00:00:00 2001 From: wschmidt Date: Thu, 9 Mar 2017 22:41:34 +0000 Subject: [PATCH] 2017-03-09 Bill Schmidt * config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Use rotate instead of vec_select for V1TImode. * conifg/rs6000/vsx.md (VSX_LE): Remove mode iterator that is no longer needed. (VSX_LE_128): Add V1TI to this mode iterator. (*vsx_le_perm_load_): Change to use VSX_D mode iterator. (*vsx_le_perm_store_): Likewise. (pre-reload splitter for VSX stores): Likewise. (post-reload splitter for VSX stores): Likewise. (*vsx_xxpermdi2_le_): Likewise. (*vsx_lxvd2x2_le_): Likewise. (*vsx_stxvd2x2_le_): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246015 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 17 ++++++++++++++++- gcc/config/rs6000/rs6000.c | 2 +- gcc/config/rs6000/vsx.md | 41 +++++++++++++++++++---------------------- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 96fb28b0901..83bf26eaeab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2017-03-09 Bill Schmidt + + * config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Use rotate + instead of vec_select for V1TImode. + * conifg/rs6000/vsx.md (VSX_LE): Remove mode iterator that is no + longer needed. + (VSX_LE_128): Add V1TI to this mode iterator. + (*vsx_le_perm_load_): Change to use VSX_D mode iterator. + (*vsx_le_perm_store_): Likewise. + (pre-reload splitter for VSX stores): Likewise. + (post-reload splitter for VSX stores): Likewise. + (*vsx_xxpermdi2_le_): Likewise. + (*vsx_lxvd2x2_le_): Likewise. + (*vsx_stxvd2x2_le_): Likewise. + 2017-03-09 Michael Eager Correct failures with --enable-checking=yes,rtl. @@ -7,7 +22,7 @@ test for const0_rtx. * config/microblaze/microblaze.md (ashlsi3_byone, ashrsi3_byone, lshrsi3_byone): Replace INTVAL with test for const1_rtx. - + 2017-03-09 Richard Biener PR tree-optimization/79977 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fde7cc71fac..e528bdf8973 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -10420,7 +10420,7 @@ rs6000_gen_le_vsx_permute (rtx source, machine_mode mode) { /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point, and 128-bit integers if they are allowed in VSX registers. */ - if (FLOAT128_VECTOR_P (mode) || mode == TImode) + if (FLOAT128_VECTOR_P (mode) || mode == TImode || mode == V1TImode) return gen_rtx_ROTATE (mode, source, GEN_INT (64)); else { diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index aabc8f61ece..01b55e616b7 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -27,15 +27,12 @@ ;; Iterator for the 2 64-bit vector types (define_mode_iterator VSX_D [V2DF V2DI]) -;; Iterator for the 2 64-bit vector types + 128-bit types that are loaded with -;; lxvd2x to properly handle swapping words on little endian -(define_mode_iterator VSX_LE [V2DF V2DI V1TI]) - ;; Mode iterator to handle swapping words on little endian for the 128-bit ;; types that goes in a single vector register. (define_mode_iterator VSX_LE_128 [(KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)") - (TI "TARGET_VSX_TIMODE")]) + (TI "TARGET_VSX_TIMODE") + V1TI]) ;; Iterator for the 2 32-bit vector types (define_mode_iterator VSX_W [V4SF V4SI]) @@ -387,8 +384,8 @@ ;; The patterns for LE permuted loads and stores come before the general ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") - (match_operand:VSX_LE 1 "memory_operand" "Z"))] + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") + (match_operand:VSX_D 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -501,16 +498,16 @@ (set_attr "length" "8")]) (define_insn "*vsx_le_perm_store_" - [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (match_operand:VSX_LE 1 "vsx_register_operand" "+"))] + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (match_operand:VSX_D 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_LE 0 "memory_operand" "") - (match_operand:VSX_LE 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_D 0 "memory_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select: @@ -528,8 +525,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_LE 0 "memory_operand" "") - (match_operand:VSX_LE 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_D 0 "memory_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select: @@ -2061,9 +2058,9 @@ ;; xxpermdi for little endian loads and stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_xxpermdi2_le_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") - (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") + (vec_select:VSX_D + (match_operand:VSX_D 1 "vsx_register_operand" "") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" "xxpermdi %x0,%x1,%x1,2" @@ -2110,9 +2107,9 @@ ;; lxvd2x for little endian loads. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_lxvd2x2_le_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") - (vec_select:VSX_LE - (match_operand:VSX_LE 1 "memory_operand" "Z") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") + (vec_select:VSX_D + (match_operand:VSX_D 1 "memory_operand" "Z") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" @@ -2159,9 +2156,9 @@ ;; stxvd2x for little endian stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_stxvd2x2_le_" - [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "") + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (vec_select:VSX_D + (match_operand:VSX_D 1 "vsx_register_operand" "") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0" -- 2.11.4.GIT