From dd6d7504386a7a5a76861d015679f664de1384b0 Mon Sep 17 00:00:00 2001 From: rearnsha Date: Sat, 6 May 2000 11:10:44 +0000 Subject: [PATCH] * arm.c (arm_gen_load_multiple, arm_gen_store_mulitple): Don't add bogus clobber to insns. (load_multiple_operation, store_mulitple_operation): Don't check for it. * arm.md (ldmsi_postinc, stmsi_postinc): Adjust accordingly. * arm.md (and_scc, ior_scc): Add missing mode. * arm.md (call_value_symbol): Remove predicate from op2. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@33723 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/arm/arm.c | 26 ++++---------------------- gcc/config/arm/arm.md | 18 +++++++++--------- 3 files changed, 25 insertions(+), 31 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 58bb7a68bed..db0ce02bae7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2000-05-06 Richard Earnshaw (reanrsha@arm.com) + + * arm.c (arm_gen_load_multiple, arm_gen_store_mulitple): Don't add + bogus clobber to insns. + (load_multiple_operation, store_mulitple_operation): Don't check + for it. + * arm.md (ldmsi_postinc, stmsi_postinc): Adjust accordingly. + + * arm.md (and_scc, ior_scc): Add missing mode. + + * arm.md (call_value_symbol): Remove predicate from op2. + Sat May 6 06:25:56 2000 Richard Kenner * expr.c (get_subtarget): New function. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9311ba48836..ba5b38cb17d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3203,14 +3203,8 @@ load_multiple_operation (op, mode) || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT - || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4 - || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER - || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG - || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0)) - != REGNO (SET_DEST (elt))) + || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) return 0; - - count--; } /* Perform a quick check so we don't blow up below. */ @@ -3271,14 +3265,8 @@ store_multiple_operation (op, mode) || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT - || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4 - || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER - || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG - || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0)) - != REGNO (SET_DEST (elt))) + || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) return 0; - - count--; } /* Perform a quick check so we don't blow up below. */ @@ -3812,7 +3800,7 @@ arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, rtx mem; result = gen_rtx_PARALLEL (VOIDmode, - rtvec_alloc (count + (write_back ? 2 : 0))); + rtvec_alloc (count + (write_back ? 1 : 0))); if (write_back) { XVECEXP (result, 0, 0) @@ -3832,9 +3820,6 @@ arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); } - if (write_back) - XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from); - return result; } @@ -3856,7 +3841,7 @@ arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, rtx mem; result = gen_rtx_PARALLEL (VOIDmode, - rtvec_alloc (count + (write_back ? 2 : 0))); + rtvec_alloc (count + (write_back ? 1 : 0))); if (write_back) { XVECEXP (result, 0, 0) @@ -3877,9 +3862,6 @@ arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); } - if (write_back) - XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to); - return result; } diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 0862668df94..67e053b4418 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4956,7 +4956,7 @@ (match_operand:SI 2 "const_int_operand" "n"))) (set (match_operand:SI 3 "s_register_operand" "=r") (mem:SI (match_dup 1)))])] - "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 2))" + "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 1))" "* { rtx ops[3]; @@ -4964,7 +4964,7 @@ ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); ops[1] = SET_DEST (XVECEXP (operands[0], 0, 1)); - ops[2] = SET_DEST (XVECEXP (operands[0], 0, count - 2)); + ops[2] = SET_DEST (XVECEXP (operands[0], 0, count - 1)); output_asm_insn (\"ldm%?ia\\t%0!, {%1-%2}\\t%@ load multiple\", ops); return \"\"; @@ -5027,7 +5027,7 @@ (match_operand:SI 2 "const_int_operand" "n"))) (set (mem:SI (match_dup 1)) (match_operand:SI 3 "s_register_operand" "r"))])] - "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 2))" + "TARGET_ARM && (INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 1))" "* { rtx ops[3]; @@ -5035,16 +5035,16 @@ ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); ops[1] = SET_SRC (XVECEXP (operands[0], 0, 1)); - ops[2] = SET_SRC (XVECEXP (operands[0], 0, count - 2)); + ops[2] = SET_SRC (XVECEXP (operands[0], 0, count - 1)); output_asm_insn (\"stm%?ia\\t%0!, {%1-%2}\\t%@ str multiple\", ops); return \"\"; } " [(set (attr "type") - (cond [(eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 4)) + (cond [(eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 3)) (const_string "store2") - (eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 5)) + (eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 4)) (const_string "store3")] (const_string "store4")))] ) @@ -6006,7 +6006,7 @@ (define_insn "*call_value_symbol" [(set (match_operand 0 "s_register_operand" "=rf") (call (mem:SI (match_operand:SI 1 "" "X")) - (match_operand:SI 2 "general_operand" "g"))) + (match_operand:SI 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI 14))] "TARGET_ARM @@ -6445,7 +6445,7 @@ (define_insn "*and_scc" [(set (match_operand:SI 0 "s_register_operand" "=r") - (and:SI (match_operator 1 "comparison_operator" + (and:SI (match_operator:SI 1 "comparison_operator" [(match_operand 3 "cc_register" "") (const_int 0)]) (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_ARM" @@ -6455,7 +6455,7 @@ (define_insn "*ior_scc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (ior:SI (match_operator 2 "comparison_operator" + (ior:SI (match_operator:SI 2 "comparison_operator" [(match_operand 3 "cc_register" "") (const_int 0)]) (match_operand:SI 1 "s_register_operand" "0,?r")))] "TARGET_ARM" -- 2.11.4.GIT