From ccd9e27d2c85f87f1668021ae9a6bd01ffbdc5ad Mon Sep 17 00:00:00 2001 From: rth Date: Wed, 9 Jan 2002 11:02:07 +0000 Subject: [PATCH] * config/m32r/m32r.c (move_src_operand): Fix 32-bit int test. * config/m32r/m32r.md (and ior xor splitters): Swap operands to match insn patterns. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@48679 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 ++++++ gcc/config/m32r/m32r.c | 8 +++++++- gcc/config/m32r/m32r.md | 6 +++--- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7df79a97486..65dc90f93cb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2002-01-09 Richard Henderson + * config/m32r/m32r.c (move_src_operand): Fix 32-bit int test. + * config/m32r/m32r.md (and ior xor splitters): Swap operands + to match insn patterns. + +2002-01-09 Richard Henderson + * regrename.c (find_oldest_value_reg): Use gen_rtx_raw_REG. (copyprop_hardreg_forward_1): Likewise. diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index a3692c9af5c..9ae218e1d06 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -793,7 +793,13 @@ move_src_operand (op, mode) loadable with one insn, and split the rest into two. The instances where this would help should be rare and the current way is simpler. */ - return UINT32_P (INTVAL (op)); + if (HOST_BITS_PER_WIDE_INT > 32) + { + HOST_WIDE_INT rest = INTVAL (op) >> 31; + return (rest == 0 || rest == -1); + } + else + return 1; case LABEL_REF : return TARGET_ADDR24; case CONST_DOUBLE : diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index 2d10057f0f3..a8e28db0ba9 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1032,7 +1032,7 @@ (match_operand:SI 2 "int8_operand" "")))] "optimize_size && m32r_not_same_reg (operands[0], operands[1])" [(set (match_dup 0) (match_dup 2)) - (set (match_dup 0) (and:SI (match_dup 1) (match_dup 0)))] + (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))] "") (define_insn "iorsi3" @@ -1064,7 +1064,7 @@ (match_operand:SI 2 "int8_operand" "")))] "optimize_size && m32r_not_same_reg (operands[0], operands[1])" [(set (match_dup 0) (match_dup 2)) - (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 0)))] + (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))] "") (define_insn "xorsi3" @@ -1096,7 +1096,7 @@ (match_operand:SI 2 "int8_operand" "")))] "optimize_size && m32r_not_same_reg (operands[0], operands[1])" [(set (match_dup 0) (match_dup 2)) - (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 0)))] + (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))] "") (define_insn "negsi2" -- 2.11.4.GIT