From c9fcbe2fece55b37628bdbbfaf521f305f78c10f Mon Sep 17 00:00:00 2001 From: bergner Date: Thu, 27 Jul 2017 20:03:35 +0000 Subject: [PATCH] gcc/ * config/rs6000/rs6000.opt (mlra): Replace with stub. * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete OPTION_MASK_LRA. * config/rs6000/rs6000.c (TARGET_LRA_P): Delete. (rs6000_debug_reg_global): Delete print of LRA status. (rs6000_option_override_internal): Delete dead LRA related code. (rs6000_lra_p): Delete function. * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mlra. gcc/testsuite/ * g++.dg/pr69667.C: Remove option -mlra. * gcc.target/powerpc/dform-1.c: Likewise. * gcc.target/powerpc/dform-2.c: Likewise. * gcc.target/powerpc/dform-3.c: Likewise. * gcc.target/powerpc/p8vector-int128-1.c: Likewise. * gcc.target/powerpc/p9-vparity.c: Likewise. * gcc.target/powerpc/pr63491.c: Likewise. * gcc.target/powerpc/pr67808.c: Likewise. * gcc.target/powerpc/pr68805.c: Likewise. * gcc.target/powerpc/pr69461.c: Likewise. * gcc.target/powerpc/pr71680.c: Likewise. * gcc.target/powerpc/pr77289.c: Likewise. * gcc.target/powerpc/pr78458.c: Likewise. * gcc.target/powerpc/pr78543.c: Likewise. * g++.dg/pr71294.C: Remove option -mno-lra. * gcc.target/powerpc/pr71656-1.c: Likewise. * gcc.target/powerpc/pr71656-2.c: Likewise. * gcc.target/powerpc/pr71698.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250637 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 +++++ gcc/config/rs6000/rs6000-cpus.def | 1 - gcc/config/rs6000/rs6000.c | 46 ++-------------------- gcc/config/rs6000/rs6000.opt | 4 +- gcc/doc/invoke.texi | 8 +--- gcc/testsuite/ChangeLog | 21 ++++++++++ gcc/testsuite/g++.dg/pr69667.C | 2 +- gcc/testsuite/g++.dg/pr71294.C | 2 +- gcc/testsuite/gcc.target/powerpc/dform-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/dform-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/dform-3.c | 2 +- .../gcc.target/powerpc/p8vector-int128-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr63491.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr67808.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr68805.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr69461.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71656-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71656-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71680.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71698.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr77289.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr78458.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr78543.c | 2 +- 24 files changed, 56 insertions(+), 70 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d8069d3ac68..252229e0d25 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-07-27 Peter Bergner + + * config/rs6000/rs6000.opt (mlra): Replace with stub. + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete OPTION_MASK_LRA. + * config/rs6000/rs6000.c (TARGET_LRA_P): Delete. + (rs6000_debug_reg_global): Delete print of LRA status. + (rs6000_option_override_internal): Delete dead LRA related code. + (rs6000_lra_p): Delete function. + * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mlra. + 2017-07-27 Sebastian Huber * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*). diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 51aff3a5c31..190f9123fa0 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -123,7 +123,6 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ - | OPTION_MASK_LRA \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MFPGPR \ | OPTION_MASK_MODULO \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7461decd99c..016a9bef2df 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1887,9 +1887,6 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_MODE_DEPENDENT_ADDRESS_P #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p -#undef TARGET_LRA_P -#define TARGET_LRA_P rs6000_lra_p - #undef TARGET_COMPUTE_PRESSURE_CLASSES #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes @@ -2790,8 +2787,6 @@ rs6000_debug_reg_global (void) if (TARGET_LINK_STACK) fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); - fprintf (stderr, DEBUG_FMT_S, "lra", TARGET_LRA ? "true" : "false"); - if (TARGET_P8_FUSION) { char options[80]; @@ -4555,35 +4550,10 @@ rs6000_option_override_internal (bool global_init_p) } } - /* Enable LRA by default. */ - if ((rs6000_isa_flags_explicit & OPTION_MASK_LRA) == 0) - rs6000_isa_flags |= OPTION_MASK_LRA; - - /* There have been bugs with -mvsx-timode that don't show up with -mlra, - but do show up with -mno-lra. Given -mlra will become the default once - PR 69847 is fixed, turn off the options with problems by default if - -mno-lra was used, and warn if the user explicitly asked for the option. - - Enable -mpower9-dform-vector by default if LRA and other power9 options. - Enable -mvsx-timode by default if LRA and VSX. */ - if (!TARGET_LRA) - { - if (TARGET_VSX_TIMODE) - { - if ((rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) != 0) - warning (0, "-mvsx-timode might need -mlra"); - - else - rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE; - } - } - - else - { - if (TARGET_VSX && !TARGET_VSX_TIMODE - && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0) - rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE; - } + /* Enable -mvsx-timode by default if VSX. */ + if (TARGET_VSX && !TARGET_VSX_TIMODE + && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0) + rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE; /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07 support. If we only have ISA 2.06 support, and the user did not specify @@ -35876,14 +35846,6 @@ rs6000_libcall_value (machine_mode mode) return gen_rtx_REG (mode, regno); } - -/* Return true if we use LRA instead of reload pass. */ -static bool -rs6000_lra_p (void) -{ - return TARGET_LRA; -} - /* Compute register pressure classes. We implement the target hook to avoid IRA picking something like NON_SPECIAL_REGS as a pressure class, which can lead to incorrect estimates of number of available registers and therefor diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 1fa65a0551f..e94aa07bc7a 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -430,9 +430,9 @@ mlong-double- Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save -mlong-double- Specify size of long double (64 or 128 bits). +; This option existed in the past, but now is always on. mlra -Target Report Mask(LRA) Var(rs6000_isa_flags) -Enable Local Register Allocation. +Target RejectNegative Undocumented Ignore msched-costly-dep= Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6e174c5b3ff..5ae9dc4128d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1048,8 +1048,7 @@ See RS/6000 and PowerPC Options. -mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol -mgnu-attribute -mno-gnu-attribute @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol --mstack-protector-guard-offset=@var{offset} @gol --mlra -mno-lra} +-mstack-protector-guard-offset=@var{offset}} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -21841,11 +21840,6 @@ This switch enables or disables the generation of ISEL instructions. This switch has been deprecated. Use @option{-misel} and @option{-mno-isel} instead. -@item -mlra -@opindex mlra -Enable Local Register Allocation. By default the port uses LRA. -(i.e. @option{-mno-lra}). - @item -mspe @itemx -mno-spe @opindex mspe diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 87d3b6fce2f..40f9501afb8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,24 @@ +2017-07-27 Peter Bergner + + * g++.dg/pr69667.C: Remove option -mlra. + * gcc.target/powerpc/dform-1.c: Likewise. + * gcc.target/powerpc/dform-2.c: Likewise. + * gcc.target/powerpc/dform-3.c: Likewise. + * gcc.target/powerpc/p8vector-int128-1.c: Likewise. + * gcc.target/powerpc/p9-vparity.c: Likewise. + * gcc.target/powerpc/pr63491.c: Likewise. + * gcc.target/powerpc/pr67808.c: Likewise. + * gcc.target/powerpc/pr68805.c: Likewise. + * gcc.target/powerpc/pr69461.c: Likewise. + * gcc.target/powerpc/pr71680.c: Likewise. + * gcc.target/powerpc/pr77289.c: Likewise. + * gcc.target/powerpc/pr78458.c: Likewise. + * gcc.target/powerpc/pr78543.c: Likewise. + * g++.dg/pr71294.C: Remove option -mno-lra. + * gcc.target/powerpc/pr71656-1.c: Likewise. + * gcc.target/powerpc/pr71656-2.c: Likewise. + * gcc.target/powerpc/pr71698.c: Likewise. + 2017-07-27 Kyrylo Tkachov Sudakshina Das diff --git a/gcc/testsuite/g++.dg/pr69667.C b/gcc/testsuite/g++.dg/pr69667.C index 2b3e93d2e1e..76f7cb3d40b 100644 --- a/gcc/testsuite/g++.dg/pr69667.C +++ b/gcc/testsuite/g++.dg/pr69667.C @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-mcpu=power8 -w -std=c++14 -mlra" } */ +/* { dg-options "-mcpu=power8 -w -std=c++14" } */ /* target/69667, compiler got internal compiler error: Max. number of generated reload insns per insn is achieved (90) */ diff --git a/gcc/testsuite/g++.dg/pr71294.C b/gcc/testsuite/g++.dg/pr71294.C index 55dd01e5ccf..67675dd7e30 100644 --- a/gcc/testsuite/g++.dg/pr71294.C +++ b/gcc/testsuite/g++.dg/pr71294.C @@ -1,7 +1,7 @@ // { dg-do compile { target { powerpc64*-*-* && lp64 } } } // { dg-require-effective-target powerpc_p8vector_ok } */ // { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } -// { dg-options "-mcpu=power8 -O3 -fstack-protector -mno-lra" } +// { dg-options "-mcpu=power8 -O3 -fstack-protector" } // PAR target/71294 failed because RELOAD could not figure how create a V2DI // vector that auto vectorization created with each element being the same diff --git a/gcc/testsuite/gcc.target/powerpc/dform-1.c b/gcc/testsuite/gcc.target/powerpc/dform-1.c index 12623f20262..37a30d1c92f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-1.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/dform-2.c b/gcc/testsuite/gcc.target/powerpc/dform-2.c index 86d65b5b1fd..b4c4199c0b3 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-2.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE float diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c index b1c481fbf6d..c261c4e6f5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-3.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE vector double diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c index 23663b96da6..992ed225d5f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O3 -mvsx-timode -mlra" } */ +/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c index af5b5905a6f..6e49606fe0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mlra -mvsx-timode" } */ +/* { dg-options "-mcpu=power9 -O2 -mvsx-timode" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr63491.c b/gcc/testsuite/gcc.target/powerpc/pr63491.c index a1518912308..be6a40eb32d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63491.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63491.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-options "-O1 -mcpu=power8 -mlra" } */ +/* { dg-options "-O1 -mcpu=power8" } */ typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; typedef unsigned long long scalar_64_t; diff --git a/gcc/testsuite/gcc.target/powerpc/pr67808.c b/gcc/testsuite/gcc.target/powerpc/pr67808.c index 16b309c151e..3ee8003bebc 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr67808.c +++ b/gcc/testsuite/gcc.target/powerpc/pr67808.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O1 -mvsx -mlra -mcpu=power7 -mlong-double-128" } */ +/* { dg-options "-O1 -mvsx -mcpu=power7 -mlong-double-128" } */ /* PR 67808: LRA ICEs on simple double to long double conversion test case */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr68805.c b/gcc/testsuite/gcc.target/powerpc/pr68805.c index 5510811107d..f4454a9e2d2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr68805.c +++ b/gcc/testsuite/gcc.target/powerpc/pr68805.c @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc64le-*-* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-O2 -mvsx-timode -mcpu=power8 -mlra" } */ +/* { dg-options "-O2 -mvsx-timode -mcpu=power8" } */ typedef struct bar { void *a; diff --git a/gcc/testsuite/gcc.target/powerpc/pr69461.c b/gcc/testsuite/gcc.target/powerpc/pr69461.c index 406e7049d29..f693a5f0146 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr69461.c +++ b/gcc/testsuite/gcc.target/powerpc/pr69461.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mlra" } */ +/* { dg-options "-O3" } */ extern void _setjmp (void); typedef struct { diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c index fa6b4ffb816..1cb809f8b2a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */ +/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector" } */ typedef __attribute__((altivec(vector__))) int type_t; type_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c index 99855fa1667..f953ebe4f9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */ +/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -funroll-loops -fno-aggressive-loop-optimizations" } */ typedef double vec[3]; struct vec_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71680.c b/gcc/testsuite/gcc.target/powerpc/pr71680.c index fe5260f73d9..cdb7b5143ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71680.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71680.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O1 -mlra" } */ +/* { dg-options "-mcpu=power8 -O1" } */ #pragma pack(1) struct diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c index c752f64e1c7..eba47b0951f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71698.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-require-effective-target dfp } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */ +/* { dg-options "-O1 -mcpu=power9" } */ extern void testvad128 (int n, ...); void diff --git a/gcc/testsuite/gcc.target/powerpc/pr77289.c b/gcc/testsuite/gcc.target/powerpc/pr77289.c index 295aa27acdc..474bdbf0b16 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr77289.c +++ b/gcc/testsuite/gcc.target/powerpc/pr77289.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mlra -mupdate -fno-auto-inc-dec" } */ +/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mupdate -fno-auto-inc-dec" } */ /* PR 77289: LRA ICEs due to invalid constraint checking. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78458.c b/gcc/testsuite/gcc.target/powerpc/pr78458.c index 777ac43bcad..a27876375af 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78458.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78458.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe" } */ /* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ extern void bar (void); diff --git a/gcc/testsuite/gcc.target/powerpc/pr78543.c b/gcc/testsuite/gcc.target/powerpc/pr78543.c index 0421344d3ce..13b34e58a0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78543.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78543.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O1 -mno-lra" } */ +/* { dg-options "-mcpu=power8 -O1" } */ typedef long a; enum c { e, f, g, h, i, ab } j(); -- 2.11.4.GIT