From c33994bea00461d5c408a64fc11f601831a7c74c Mon Sep 17 00:00:00 2001 From: rearnsha Date: Thu, 2 Aug 2012 16:20:22 +0000 Subject: [PATCH] * arm.c (arm_gen_constant): Use UBFX for some AND operations when available. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@190088 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/arm.c | 25 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 973ae0d3587..578b0a05485 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-08-02 Richard Earnshaw + + * arm.c (arm_gen_constant): Use UBFX for some AND operations when + available. + 2012-08-02 Richard Guenther * tree-into-ssa.c (struct common_info_d): New struct. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 701ab4cfe2d..00ccb9280de 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2982,6 +2982,31 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, return 1; } + /* On targets with UXTH/UBFX, we can deal with AND (2^N)-1 in a single + insn. */ + if (code == AND && (i = exact_log2 (remainder + 1)) > 0 + && (arm_arch_thumb2 || (i == 16 && arm_arch6 && mode == SImode))) + { + if (generate) + { + if (mode == SImode && i == 16) + /* Use UXTH in preference to UBFX, since on Thumb2 it's a + smaller insn. */ + emit_constant_insn (cond, + gen_zero_extendhisi2 + (target, gen_lowpart (HImode, source))); + else + /* Extz only supports SImode, but we can coerce the operands + into that mode. */ + emit_constant_insn (cond, + gen_extzv_t2 (gen_lowpart (mode, target), + gen_lowpart (mode, source), + GEN_INT (i), const0_rtx)); + } + + return 1; + } + /* Calculate a few attributes that may be useful for specific optimizations. */ /* Count number of leading zeros. */ -- 2.11.4.GIT