From a21bd7faba67997a6da457dbda16f15bca1a9156 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Tue, 28 Mar 2023 10:13:24 +0200 Subject: [PATCH] Fix PR target/109140 This is a regression present on the mainline and 12 branch at -O2, but the issue is related to vectorization so was present at -O3 in earlier versions. The vcondu expander that was added for VIS 3 more than a decade ago does not fully work, because it does not filter out the unsigned condition codes (the instruction is an UNSPEC that accepts only signed condition codes). While I was at it, I also added the missing vcond and vcondu expanders for the new comparison instructions that were added in VIS 4. gcc/ PR target/109140 * config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition on operand #3 to get the final condition code. Use std::swap. * config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander. (fucmp8_vis): Move around. (fpcmpu_vis): Likewise. (vcondu): New VIS 4 expander. gcc/testsuite/ * gcc.target/sparc/20230328-1.c: New test. * gcc.target/sparc/20230328-2.c: Likewise. * gcc.target/sparc/20230328-3.c: Likewise. * gcc.target/sparc/20230328-4.c: Likewise. --- gcc/config/sparc/sparc.cc | 6 +-- gcc/config/sparc/sparc.md | 62 ++++++++++++++++++++--------- gcc/testsuite/gcc.target/sparc/20230328-1.c | 19 +++++++++ gcc/testsuite/gcc.target/sparc/20230328-2.c | 19 +++++++++ gcc/testsuite/gcc.target/sparc/20230328-3.c | 19 +++++++++ gcc/testsuite/gcc.target/sparc/20230328-4.c | 19 +++++++++ 6 files changed, 122 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.target/sparc/20230328-1.c create mode 100644 gcc/testsuite/gcc.target/sparc/20230328-2.c create mode 100644 gcc/testsuite/gcc.target/sparc/20230328-3.c create mode 100644 gcc/testsuite/gcc.target/sparc/20230328-4.c diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc index 644ff9cf594..8c0c9dce971 100644 --- a/gcc/config/sparc/sparc.cc +++ b/gcc/config/sparc/sparc.cc @@ -13662,18 +13662,16 @@ sparc_expand_conditional_move (machine_mode mode, rtx *operands) void sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) { + enum rtx_code code = signed_condition (GET_CODE (operands[3])); rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr; - enum rtx_code code = GET_CODE (operands[3]); mask = gen_reg_rtx (Pmode); cop0 = operands[4]; cop1 = operands[5]; if (code == LT || code == GE) { - rtx t; - code = swap_condition (code); - t = cop0; cop0 = cop1; cop1 = t; + std::swap (cop0, cop1); } gsr = gen_rtx_REG (DImode, SPARC_GSR_REG); diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 417b588e610..94779c16c63 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -9033,6 +9033,50 @@ visl") DONE; }) +(define_expand "vcondv8qiv8qi" + [(match_operand:V8QI 0 "register_operand" "") + (match_operand:V8QI 1 "register_operand" "") + (match_operand:V8QI 2 "register_operand" "") + (match_operator 3 "" + [(match_operand:V8QI 4 "register_operand" "") + (match_operand:V8QI 5 "register_operand" "")])] + "TARGET_VIS4" +{ + sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FCMP); + DONE; +}) + +(define_insn "fucmp8_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") + (match_operand:V8QI 2 "register_operand" "e"))] + UNSPEC_FUCMP))] + "TARGET_VIS3" + "fucmp8\t%1, %2, %0" + [(set_attr "type" "viscmp")]) + +(define_insn "fpcmpu_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") + (match_operand:GCM 2 "register_operand" "e"))] + UNSPEC_FUCMP))] + "TARGET_VIS4" + "fpcmpu\t%1, %2, %0" + [(set_attr "type" "viscmp")]) + +(define_expand "vcondu" + [(match_operand:GCM 0 "register_operand" "") + (match_operand:GCM 1 "register_operand" "") + (match_operand:GCM 2 "register_operand" "") + (match_operator 3 "" + [(match_operand:GCM 4 "register_operand" "") + (match_operand:GCM 5 "register_operand" "")])] + "TARGET_VIS4" +{ + sparc_expand_vcond (mode, operands, UNSPEC_CMASK, UNSPEC_FUCMP); + DONE; +}) + (define_expand "vconduv8qiv8qi" [(match_operand:V8QI 0 "register_operand" "") (match_operand:V8QI 1 "register_operand" "") @@ -9351,24 +9395,6 @@ visl") [(set_attr "type" "fga") (set_attr "subtype" "other")]) -(define_insn "fucmp8_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") - (match_operand:V8QI 2 "register_operand" "e"))] - UNSPEC_FUCMP))] - "TARGET_VIS3" - "fucmp8\t%1, %2, %0" - [(set_attr "type" "viscmp")]) - -(define_insn "fpcmpu_vis" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") - (match_operand:GCM 2 "register_operand" "e"))] - UNSPEC_FUCMP))] - "TARGET_VIS4" - "fpcmpu\t%1, %2, %0" - [(set_attr "type" "viscmp")]) - (define_insn "*naddsf3" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "f") diff --git a/gcc/testsuite/gcc.target/sparc/20230328-1.c b/gcc/testsuite/gcc.target/sparc/20230328-1.c new file mode 100644 index 00000000000..bc0e35f100e --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-1.c @@ -0,0 +1,19 @@ +/* PR target/109140 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mvis3 -std=c99" } */ + +#define TYPE unsigned char + +struct S { TYPE ub[8]; }; + +struct S s; + +TYPE v; + +void foo (void) +{ + for (int i = 0; i < 8; i++) + s.ub[i] = s.ub[i] > v; +} + +/* { dg-final { scan-assembler "fucmpgt8\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/20230328-2.c b/gcc/testsuite/gcc.target/sparc/20230328-2.c new file mode 100644 index 00000000000..7030344350c --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-2.c @@ -0,0 +1,19 @@ +/* PR target/109140 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mvis4 -std=c99" } */ + +#define TYPE char + +struct S { TYPE ub[8]; }; + +struct S s; + +TYPE v; + +void foo (void) +{ + for (int i = 0; i < 8; i++) + s.ub[i] = s.ub[i] > v; +} + +/* { dg-final { scan-assembler "fpcmpgt8\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/20230328-3.c b/gcc/testsuite/gcc.target/sparc/20230328-3.c new file mode 100644 index 00000000000..23d281e3f1c --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-3.c @@ -0,0 +1,19 @@ +/* PR target/109140 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mvis4 -std=c99" } */ + +#define TYPE unsigned short + +struct S { TYPE ub[4]; }; + +struct S s; + +TYPE v; + +void foo (void) +{ + for (int i = 0; i < 4; i++) + s.ub[i] = s.ub[i] > v; +} + +/* { dg-final { scan-assembler "fpcmpugt16\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/20230328-4.c b/gcc/testsuite/gcc.target/sparc/20230328-4.c new file mode 100644 index 00000000000..0172d0bb4c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/20230328-4.c @@ -0,0 +1,19 @@ +/* PR target/109140 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mvis3 -std=c99" } */ + +#define TYPE short + +struct S { TYPE ub[4]; }; + +struct S s; + +TYPE v; + +void foo (void) +{ + for (int i = 0; i < 4; i++) + s.ub[i] = s.ub[i] > v; +} + +/* { dg-final { scan-assembler "fcmpgt16\t%" } } */ -- 2.11.4.GIT