From 9ecc766d7ecfa2a26c4638786cba8122d1b24321 Mon Sep 17 00:00:00 2001 From: yroux Date: Wed, 3 Sep 2014 13:06:56 +0000 Subject: [PATCH] 2014-09-03 Yvan Roux Backport from trunk r213712. 2014-08-07 Kyrylo Tkachov * config/aarch64/aarch64.md (absdi2): Set simd attribute. (aarch64_reload_mov): Predicate on TARGET_FLOAT. (aarch64_movdi_high): Likewise. (aarch64_movhigh_di): Likewise. (aarch64_movdi_low): Likewise. (aarch64_movlow_di): Likewise. (aarch64_movtilow_tilow): Likewise. Add comment explaining usage of fp,simd attributes and of TARGET_FLOAT and TARGET_SIMD. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro@214875 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc-4_9-branch/gcc/ChangeLog.linaro | 15 ++++++++++++++ gcc-4_9-branch/gcc/config/aarch64/aarch64.md | 31 +++++++++++++++++++--------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/gcc-4_9-branch/gcc/ChangeLog.linaro b/gcc-4_9-branch/gcc/ChangeLog.linaro index 9ae3b482e1d..e0158f8fc2d 100644 --- a/gcc-4_9-branch/gcc/ChangeLog.linaro +++ b/gcc-4_9-branch/gcc/ChangeLog.linaro @@ -1,5 +1,20 @@ 2014-09-03 Yvan Roux + Backport from trunk r213712. + 2014-08-07 Kyrylo Tkachov + + * config/aarch64/aarch64.md (absdi2): Set simd attribute. + (aarch64_reload_mov): Predicate on TARGET_FLOAT. + (aarch64_movdi_high): Likewise. + (aarch64_movhigh_di): Likewise. + (aarch64_movdi_low): Likewise. + (aarch64_movlow_di): Likewise. + (aarch64_movtilow_tilow): Likewise. + Add comment explaining usage of fp,simd attributes and of + TARGET_FLOAT and TARGET_SIMD. + +2014-09-03 Yvan Roux + Backport from trunk r214526. 2014-08-26 Joseph Myers diff --git a/gcc-4_9-branch/gcc/config/aarch64/aarch64.md b/gcc-4_9-branch/gcc/config/aarch64/aarch64.md index be1206dccf7..cc957d7c83e 100644 --- a/gcc-4_9-branch/gcc/config/aarch64/aarch64.md +++ b/gcc-4_9-branch/gcc/config/aarch64/aarch64.md @@ -141,12 +141,22 @@ ; to share pipeline descriptions. (include "../arm/types.md") +;; It is important to set the fp or simd attributes to yes when a pattern +;; alternative uses the FP or SIMD register files, usually signified by use of +;; the 'w' constraint. This will ensure that the alternative will be +;; disabled when compiling with -mgeneral-regs-only or with the +nofp/+nosimd +;; architecture extensions. If all the alternatives in a pattern use the +;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT +;; or TARGET_SIMD. + ;; Attribute that specifies whether or not the instruction touches fp -;; registers. +;; registers. When this is set to yes for an alternative, that alternative +;; will be disabled when !TARGET_FLOAT. (define_attr "fp" "no,yes" (const_string "no")) ;; Attribute that specifies whether or not the instruction touches simd -;; registers. +;; registers. When this is set to yes for an alternative, that alternative +;; will be disabled when !TARGET_SIMD. (define_attr "simd" "no,yes" (const_string "no")) (define_attr "length" "" @@ -1906,7 +1916,8 @@ GEN_INT (63))))); DONE; } - [(set_attr "type" "alu_reg")] + [(set_attr "type" "alu_sreg") + (set_attr "simd" "no,yes")] ) (define_insn "neg2" @@ -3676,7 +3687,7 @@ (match_operand:TX 1 "register_operand" "w")) (clobber (match_operand:DI 2 "register_operand" "=&r")) ] - "" + "TARGET_FLOAT" { rtx op0 = simplify_gen_subreg (TImode, operands[0], mode, 0); rtx op1 = simplify_gen_subreg (TImode, operands[1], mode, 0); @@ -3694,7 +3705,7 @@ (define_insn "aarch64_movdi_low" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI (match_operand:TX 1 "register_operand" "w")))] - "reload_completed || reload_in_progress" + "TARGET_FLOAT && (reload_completed || reload_in_progress)" "fmov\\t%x0, %d1" [(set_attr "type" "f_mrc") (set_attr "length" "4") @@ -3705,7 +3716,7 @@ (truncate:DI (lshiftrt:TX (match_operand:TX 1 "register_operand" "w") (const_int 64))))] - "reload_completed || reload_in_progress" + "TARGET_FLOAT && (reload_completed || reload_in_progress)" "fmov\\t%x0, %1.d[1]" [(set_attr "type" "f_mrc") (set_attr "length" "4") @@ -3715,7 +3726,7 @@ [(set (zero_extract:TX (match_operand:TX 0 "register_operand" "+w") (const_int 64) (const_int 64)) (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))] - "reload_completed || reload_in_progress" + "TARGET_FLOAT && (reload_completed || reload_in_progress)" "fmov\\t%0.d[1], %x1" [(set_attr "type" "f_mcr") (set_attr "length" "4") @@ -3724,7 +3735,7 @@ (define_insn "aarch64_movlow_di" [(set (match_operand:TX 0 "register_operand" "=w") (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))] - "reload_completed || reload_in_progress" + "TARGET_FLOAT && (reload_completed || reload_in_progress)" "fmov\\t%d0, %x1" [(set_attr "type" "f_mcr") (set_attr "length" "4") @@ -3732,9 +3743,9 @@ (define_insn "aarch64_movtilow_tilow" [(set (match_operand:TI 0 "register_operand" "=w") - (zero_extend:TI + (zero_extend:TI (truncate:DI (match_operand:TI 1 "register_operand" "w"))))] - "reload_completed || reload_in_progress" + "TARGET_FLOAT && (reload_completed || reload_in_progress)" "fmov\\t%d0, %d1" [(set_attr "type" "fmov") (set_attr "length" "4") -- 2.11.4.GIT