From 98b1f9f24d409365d8edb006a05e29bcbd81a12a Mon Sep 17 00:00:00 2001 From: clyon Date: Tue, 10 Sep 2013 08:17:11 +0000 Subject: [PATCH] 2013-09-10 Christophe Lyon Backport from trunk r200593,201024,201025,201122,201124,201126. 2013-07-02 Kyrylo Tkachov * config/arm/arm.md (arm_andsi3_insn): Add alternatives for 16-bit encoding. (iorsi3_insn): Likewise. (arm_xorsi3): Likewise. 2013-07-18 Sofiane Naci * config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to "arlo_imm". Rename "alu_reg" to "arlo_reg". Rename "simple_alu_shift" to "extend". Split "alu_shift" into "shift" and "arlo_shift". Split "alu_shift_reg" into "shift_reg" and "arlo_shift_reg". List types in alphabetical order. (attribute "core_cycles"): Update for attribute changes. (arm_addsi3): Likewise. (addsi3_compare0): Likewise. (addsi3_compare0_scratch): Likewise. (addsi3_compare_op1): Likewise. (addsi3_compare_op2): Likewise. (compare_addsi2_op0): Likewise. (compare_addsi2_op1): Likewise. (addsi3_carryin_shift_): Likewise. (subsi3_carryin_shift): Likewise. (rsbsi3_carryin_shift): Likewise. (arm_subsi3_insn): Likewise. (subsi3_compare0): Likewise. (subsi3_compare): Likewise. (arm_andsi3_insn): Likewise. (thumb1_andsi3_insn): Likewise. (andsi3_compare0): Likewise. (andsi3_compare0_scratch): Likewise. (zeroextractsi_compare0_scratch (andsi_not_shiftsi_si): Likewise. (iorsi3_insn): Likewise. (iorsi3_compare0): Likewise. (iorsi3_compare0_scratch): Likewise. (arm_xorsi3): Likewise. (thumb1_xorsi3_insn): Likewise. (xorsi3_compare0): Likewise. (xorsi3_compare0_scratch): Likewise. (satsi__shift): Likewise. (rrx): Likewise. (arm_shiftsi3): Likewise. (shiftsi3_compare0): Likewise. (not_shiftsi): Likewise. (not_shiftsi_compare0): Likewise. (not_shiftsi_compare0_scratch): Likewise. (arm_one_cmplsi2): Likewise. (thumb_one_complsi2): Likewise. (notsi_compare0): Likewise. (notsi_compare0_scratch): Likewise. (thumb1_zero_extendhisi2): Likewise. (arm_zero_extendhisi2): Likewise. (arm_zero_extendhisi2_v6): Likewise. (arm_zero_extendhisi2addsi): Likewise. (thumb1_zero_extendqisi2): Likewise. (thumb1_zero_extendqisi2_v6): Likewise. (arm_zero_extendqisi2): Likewise. (arm_zero_extendqisi2_v6): Likewise. (arm_zero_extendqisi2addsi): Likewise. (thumb1_extendhisi2): Likewise. (arm_extendhisi2): Likewise. (arm_extendhisi2_v6): Likewise. (arm_extendqisi): Likewise. (arm_extendqisi_v6): Likewise. (arm_extendqisi2addsi): Likewise. (thumb1_extendqisi2): Likewise. (thumb1_movdi_insn): Likewise. (arm_movsi_insn): Likewise. (movsi_compare0): Likewise. (movhi_insn_arch4): Likewise. (movhi_bytes): Likewise. (arm_movqi_insn): Likewise. (thumb1_movqi_insn): Likewise. (arm32_movhf): Likewise. (thumb1_movhf): Likewise. (arm_movsf_soft_insn): Likewise. (thumb1_movsf_insn): Likewise. (movdf_soft_insn): Likewise. (thumb_movdf_insn): Likewise. (arm_cmpsi_insn): Likewise. (cmpsi_shiftsi): Likewise. (cmpsi_shiftsi_swp): Likewise. (arm_cmpsi_negshiftsi_si): Likewise. (movsicc_insn): Likewise. (movsfcc_soft_insn): Likewise. (arith_shiftsi): Likewise. (arith_shiftsi_compare0 (arith_shiftsi_compare0_scratch (sub_shiftsi): Likewise. (sub_shiftsi_compare0 (sub_shiftsi_compare0_scratch (and_scc): Likewise. (cond_move): Likewise. (if_plus_move): Likewise. (if_move_plus): Likewise. (if_move_not): Likewise. (if_not_move): Likewise. (if_shift_move): Likewise. (if_move_shift): Likewise. (if_shift_shift): Likewise. (if_not_arith): Likewise. (if_arith_not): Likewise. (cond_move_not): Likewise. (thumb1_ashlsi3): Set type attribute. (thumb1_ashrsi3): Likewise. (thumb1_lshrsi3): Likewise. (thumb1_rotrsi3): Likewise. (shiftsi3_compare0_scratch): Likewise. * config/arm/neon.md (neon_mov): Update for attribute changes. (neon_mov): Likewise. * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute changes. (thumb2_movsi_insn): Likewise. (thumb2_cmpsi_neg_shiftsi): Likewise. (thumb2_extendqisi_v6): Likewise. (thumb2_zero_extendhisi2_v6): Likewise. (thumb2_zero_extendqisi2_v6): Likewise. (thumb2_shiftsi3_short): Likewise. (thumb2_addsi3_compare0_scratch): Likewise. (orsi_not_shiftsi_si): Likewise. * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes. * config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute changes. * config/arm/arm1020e.md (1020alu_op): Update for attribute changes. (1020alu_shift_op): Likewise. (1020alu_shift_reg_op): Likewise. * config/arm/arm1026ejs.md (alu_op): Update for attribute changes. (alu_shift_op): Likewise. (alu_shift_reg_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes. (11_alu_shift_op): Likewise. (11_alu_shift_reg_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Update for attribute changes. (9_alu_shift_reg_op): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes. (cortex_a15_alu_shift): Likewise. (cortex_a15_alu_shift_reg): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes. (cortex_a5_alu_shift): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute changes. (cortex_a53_alu_shift): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute changes. (cortex_a7_alu_reg): Likewise. (cortex_a7_alu_shift): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes. (cortex_a8_alu_shift): Likewise. (cortex_a8_alu_shift_reg): Likewise. (cortex_a8_mov): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes. (cortex_a9_dp_shift): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes. * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes. (cortex_r4_mov): Likewise. (cortex_r4_alu_shift): Likewise. (cortex_r4_alu_shift_reg): Likewise. * config/arm/fa526.md (526_alu_op): Update for attribute changes. (526_alu_shift_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Update for attribute changes. * config/arm/fa626te.md (626te_alu_op): Update for attribute changes. (626te_alu_shift_op): Likewise. * config/arm/fa726te.md (726te_shift_op): Update for attribute changes. (726te_alu_op): Likewise. (726te_alu_shift_op): Likewise. (726te_alu_shift_reg_op): Likewise. * config/arm/fmp626.md (mp626_alu_op): Update for attribute changes. (mp626_alu_shift_op): Likewise. * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes. (pj4_alu_e1_conds): Likewise. (pj4_alu): Likewise. (pj4_alu_conds): Likewise. (pj4_shift): Likewise. (pj4_shift_conds): Likewise. (pj4_alu_shift): Likewise. (pj4_alu_shift_conds): Likewise. * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes. (cortexa7_older_only): Likewise. (cortexa7_younger): Likewise. 2013-07-18 Sofiane Naci * config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr", "xtab" and "sat". Move value "clz" from here to ... (attriubte "type"): ... here. (satsi_): Delete "insn" attribute. (satsi__shift): Likewise. (arm_zero_extendqisi2addsi): Likewise. (arm_extendqisi2addsi): Likewise. (clzsi2): Update for attribute changes. (rbitsi2): Likewise. * config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute. (arm_usatsihi): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. 2013-07-22 Kyrylo Tkachov * config/arm/predicates.md (shiftable_operator_strict_it): New predicate. * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Disable cond_exec version for arm_restrict_it. (thumb2_smaxsi3): Convert to generate cond_exec. (thumb2_sminsi3): Likewise. (thumb32_umaxsi3): Likewise. (thumb2_uminsi3): Likewise. (thumb2_abssi2): Adjust constraints for arm_restrict_it. (thumb2_neg_abssi2): Likewise. (thumb2_mov_scc): Add alternative for 16-bit encoding. (thumb2_movsicc_insn): Adjust alternatives. (thumb2_mov_negscc): Disable for arm_restrict_it. (thumb2_mov_negscc_strict_it): New pattern. (thumb2_mov_notscc_strict_it): New pattern. (thumb2_mov_notscc): Disable for arm_restrict_it. (thumb2_ior_scc): Likewise. (thumb2_ior_scc_strict_it): New pattern. (thumb2_cond_move): Adjust for arm_restrict_it. (thumb2_cond_arith): Disable for arm_restrict_it. (thumb2_cond_arith_strict_it): New pattern. (thumb2_cond_sub): Adjust for arm_restrict_it. (thumb2_movcond): Likewise. (thumb2_extendqisi_v6): Disable cond_exec variant for arm_restrict_it. (thumb2_zero_extendhisi2_v6): Likewise. (thumb2_zero_extendqisi2_v6): Likewise. (orsi_notsi_si): Likewise. (orsi_not_shiftsi_si): Likewise. 2013-07-22 Sofiane Naci * config/arm/arm.md (attribute "insn"): Delete. (attribute "type"): Add "mov_imm", "mov_reg", "mov_shift", "mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg". (not_shiftsi): Update for attribute change. (not_shiftsi_compare0): Likewise. (not_shiftsi_compare0_scratch): Likewise. (arm_one_cmplsi2): Likewise. (thumb1_one_cmplsi2): Likewise. (notsi_compare0): Likewise. (notsi_compare0_scratch): Likewise. (thumb1_movdi_insn): Likewise. (arm_movsi_insn): Likewise. (movhi_insn_arch4): Likewise. (movhi_bytes): Likewise. (arm_movqi_insn): Likewise. (thumb1_movqi_insn): Likewise. (arm32_movhf): Likewise. (thumb1_movhf): Likewise. (arm_movsf_soft_insn): Likewise. (thumb1_movsf_insn): Likewise. (thumb_movdf_insn): Likewise. (movsicc_insn): Likewise. (movsfcc_soft_insn): Likewise. (and_scc): Likewise. (cond_move): Likewise. (if_move_not): Likewise. (if_not_move): Likewise. (if_shift_move): Likewise. (if_move_shift): Likewise. (if_shift_shift): Likewise. (if_not_arith): Likewise. (if_arith_not): Likewise. (cond_move_not): Likewise. * config/arm/neon.md (neon_mov): Update for attribute change. (neon_mov): Likewise. * config/arm/vfp.md (arm_movsi_vfp): Update for attribute change. (thumb2_movsi_vfp): Likewise. (movsf_vfp): Likewise. (thumb2_movsf_vfp): Likewise. * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change. (cortexa7_older_only): Likewise. (cortexa7_younger): Likewise. * config/arm/arm1020e.md (1020alu_op): Update for attribute change. (1020alu_shift_op): Likewise. (1020alu_shift_reg_op): Likewise. * config/arm/arm1026ejs.md (alu_op): Update for attribute change. (alu_shift_op): Likewise. (alu_shift_reg_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Update for attribute change. (11_alu_shift_op): Likewise. (11_alu_shift_reg_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Update for attribute change. (9_alu_shift_reg_op): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change. (cortex_a15_alu_shift): Likewise. (cortex_a15_alu_shift_reg): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change. (cortex_a5_alu_shift): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change. (cortex_a53_alu_shift): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change. (cortex_a7_alu_reg): Likewise. (cortex_a7_alu_shift): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. (cortex_a8_alu_shift): Likewise. (cortex_a8_alu_shift_reg): Likewise. (cortex_a8_mov): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change. (cortex_a9_dp_shift): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change. * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change. (cortex_r4_mov): Likewise. (cortex_r4_alu_shift): Likewise. (cortex_r4_alu_shift_reg): Likewise. * config/arm/fa526.md (526_alu_op): Update for attribute change. (526_alu_shift_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Update for attribute change. * config/arm/fa626te.md (626te_alu_op): Update for attribute change. (626te_alu_shift_op): Likewise. * config/arm/fa726te.md (726te_shift_op): Update for attribute change. (726te_alu_op): Likewise. (726te_alu_shift_op): Likewise. (726te_alu_shift_reg_op): Likewise. * config/arm/fmp626.md (mp626_alu_op): Update for attribute change. (mp626_alu_shift_op): Likewise. * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change. (pj4_alu_e1_conds): Likewise. (pj4_alu): Likewise. (pj4_alu_conds): Likewise. (pj4_shift): Likewise. (pj4_shift_conds): Likewise. (pj4_alu_shift): Likewise. (pj4_alu_shift_conds): Likewise. 2013-07-22 Kyrylo Tkachov * config/arm/constraints.md (Pd): Allow TARGET_THUMB instead of TARGET_THUMB1. (Pz): New constraint. * config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit encodings. (compare_negsi_si): Likewise. (compare_addsi2_op0): Likewise. (compare_addsi2_op1): Likewise. (addsi3_carryin_): Likewise. (addsi3_carryin_alt2_): Likewise. (addsi3_carryin_shift_): Disable cond_exec variant for arm_restrict_it. (subsi3_carryin): Likewise. (arm_subsi3_insn): Add alternatives for 16-bit encoding. (minmax_arithsi): Disable for arm_restrict_it. (minmax_arithsi_non_canon): Adjust for arm_restrict_it. (satsi_): Disable cond_exec variant for arm_restrict_it. (satsi__shift): Likewise. (arm_shiftsi3): Add alternative for 16-bit encoding. (arm32_movhf): Disable for arm_restrict_it. (arm_cmpdi_unsigned): Add alternatives for 16-bit encoding. (arm_movtas_ze): Disable cond_exec variant for arm_restrict_it. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro@202424 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc-4_8-branch/gcc/ChangeLog.linaro | 352 +++++++++++++++ gcc-4_8-branch/gcc/config/arm/arm-fixed.md | 7 +- gcc-4_8-branch/gcc/config/arm/arm.c | 27 +- gcc-4_8-branch/gcc/config/arm/arm.md | 648 ++++++++++++++------------- gcc-4_8-branch/gcc/config/arm/arm1020e.md | 7 +- gcc-4_8-branch/gcc/config/arm/arm1026ejs.md | 7 +- gcc-4_8-branch/gcc/config/arm/arm1136jfs.md | 7 +- gcc-4_8-branch/gcc/config/arm/arm926ejs.md | 6 +- gcc-4_8-branch/gcc/config/arm/constraints.md | 9 +- gcc-4_8-branch/gcc/config/arm/cortex-a15.md | 8 +- gcc-4_8-branch/gcc/config/arm/cortex-a5.md | 7 +- gcc-4_8-branch/gcc/config/arm/cortex-a53.md | 7 +- gcc-4_8-branch/gcc/config/arm/cortex-a7.md | 12 +- gcc-4_8-branch/gcc/config/arm/cortex-a8.md | 17 +- gcc-4_8-branch/gcc/config/arm/cortex-a9.md | 13 +- gcc-4_8-branch/gcc/config/arm/cortex-m4.md | 6 +- gcc-4_8-branch/gcc/config/arm/cortex-r4.md | 10 +- gcc-4_8-branch/gcc/config/arm/fa526.md | 7 +- gcc-4_8-branch/gcc/config/arm/fa606te.md | 5 +- gcc-4_8-branch/gcc/config/arm/fa626te.md | 7 +- gcc-4_8-branch/gcc/config/arm/fa726te.md | 12 +- gcc-4_8-branch/gcc/config/arm/fmp626.md | 7 +- gcc-4_8-branch/gcc/config/arm/marvell-pj4.md | 32 +- gcc-4_8-branch/gcc/config/arm/neon.md | 6 +- gcc-4_8-branch/gcc/config/arm/predicates.md | 4 + gcc-4_8-branch/gcc/config/arm/thumb2.md | 356 ++++++++++----- gcc-4_8-branch/gcc/config/arm/vfp.md | 12 +- 27 files changed, 1091 insertions(+), 507 deletions(-) diff --git a/gcc-4_8-branch/gcc/ChangeLog.linaro b/gcc-4_8-branch/gcc/ChangeLog.linaro index b825f5b652f..44ab523ffdb 100644 --- a/gcc-4_8-branch/gcc/ChangeLog.linaro +++ b/gcc-4_8-branch/gcc/ChangeLog.linaro @@ -1,3 +1,355 @@ +2013-09-10 Christophe Lyon + + Backport from trunk r200593,201024,201025,201122,201124,201126. + 2013-07-02 Kyrylo Tkachov + + * config/arm/arm.md (arm_andsi3_insn): Add alternatives for 16-bit + encoding. + (iorsi3_insn): Likewise. + (arm_xorsi3): Likewise. + + 2013-07-18 Sofiane Naci + + * config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to + "arlo_imm". Rename "alu_reg" to "arlo_reg". Rename "simple_alu_shift" to + "extend". Split "alu_shift" into "shift" and "arlo_shift". Split + "alu_shift_reg" into "shift_reg" and "arlo_shift_reg". List types + in alphabetical order. + (attribute "core_cycles"): Update for attribute changes. + (arm_addsi3): Likewise. + (addsi3_compare0): Likewise. + (addsi3_compare0_scratch): Likewise. + (addsi3_compare_op1): Likewise. + (addsi3_compare_op2): Likewise. + (compare_addsi2_op0): Likewise. + (compare_addsi2_op1): Likewise. + (addsi3_carryin_shift_): Likewise. + (subsi3_carryin_shift): Likewise. + (rsbsi3_carryin_shift): Likewise. + (arm_subsi3_insn): Likewise. + (subsi3_compare0): Likewise. + (subsi3_compare): Likewise. + (arm_andsi3_insn): Likewise. + (thumb1_andsi3_insn): Likewise. + (andsi3_compare0): Likewise. + (andsi3_compare0_scratch): Likewise. + (zeroextractsi_compare0_scratch + (andsi_not_shiftsi_si): Likewise. + (iorsi3_insn): Likewise. + (iorsi3_compare0): Likewise. + (iorsi3_compare0_scratch): Likewise. + (arm_xorsi3): Likewise. + (thumb1_xorsi3_insn): Likewise. + (xorsi3_compare0): Likewise. + (xorsi3_compare0_scratch): Likewise. + (satsi__shift): Likewise. + (rrx): Likewise. + (arm_shiftsi3): Likewise. + (shiftsi3_compare0): Likewise. + (not_shiftsi): Likewise. + (not_shiftsi_compare0): Likewise. + (not_shiftsi_compare0_scratch): Likewise. + (arm_one_cmplsi2): Likewise. + (thumb_one_complsi2): Likewise. + (notsi_compare0): Likewise. + (notsi_compare0_scratch): Likewise. + (thumb1_zero_extendhisi2): Likewise. + (arm_zero_extendhisi2): Likewise. + (arm_zero_extendhisi2_v6): Likewise. + (arm_zero_extendhisi2addsi): Likewise. + (thumb1_zero_extendqisi2): Likewise. + (thumb1_zero_extendqisi2_v6): Likewise. + (arm_zero_extendqisi2): Likewise. + (arm_zero_extendqisi2_v6): Likewise. + (arm_zero_extendqisi2addsi): Likewise. + (thumb1_extendhisi2): Likewise. + (arm_extendhisi2): Likewise. + (arm_extendhisi2_v6): Likewise. + (arm_extendqisi): Likewise. + (arm_extendqisi_v6): Likewise. + (arm_extendqisi2addsi): Likewise. + (thumb1_extendqisi2): Likewise. + (thumb1_movdi_insn): Likewise. + (arm_movsi_insn): Likewise. + (movsi_compare0): Likewise. + (movhi_insn_arch4): Likewise. + (movhi_bytes): Likewise. + (arm_movqi_insn): Likewise. + (thumb1_movqi_insn): Likewise. + (arm32_movhf): Likewise. + (thumb1_movhf): Likewise. + (arm_movsf_soft_insn): Likewise. + (thumb1_movsf_insn): Likewise. + (movdf_soft_insn): Likewise. + (thumb_movdf_insn): Likewise. + (arm_cmpsi_insn): Likewise. + (cmpsi_shiftsi): Likewise. + (cmpsi_shiftsi_swp): Likewise. + (arm_cmpsi_negshiftsi_si): Likewise. + (movsicc_insn): Likewise. + (movsfcc_soft_insn): Likewise. + (arith_shiftsi): Likewise. + (arith_shiftsi_compare0 + (arith_shiftsi_compare0_scratch + (sub_shiftsi): Likewise. + (sub_shiftsi_compare0 + (sub_shiftsi_compare0_scratch + (and_scc): Likewise. + (cond_move): Likewise. + (if_plus_move): Likewise. + (if_move_plus): Likewise. + (if_move_not): Likewise. + (if_not_move): Likewise. + (if_shift_move): Likewise. + (if_move_shift): Likewise. + (if_shift_shift): Likewise. + (if_not_arith): Likewise. + (if_arith_not): Likewise. + (cond_move_not): Likewise. + (thumb1_ashlsi3): Set type attribute. + (thumb1_ashrsi3): Likewise. + (thumb1_lshrsi3): Likewise. + (thumb1_rotrsi3): Likewise. + (shiftsi3_compare0_scratch): Likewise. + * config/arm/neon.md (neon_mov): Update for attribute changes. + (neon_mov): Likewise. + * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute + changes. + (thumb2_movsi_insn): Likewise. + (thumb2_cmpsi_neg_shiftsi): Likewise. + (thumb2_extendqisi_v6): Likewise. + (thumb2_zero_extendhisi2_v6): Likewise. + (thumb2_zero_extendqisi2_v6): Likewise. + (thumb2_shiftsi3_short): Likewise. + (thumb2_addsi3_compare0_scratch): Likewise. + (orsi_not_shiftsi_si): Likewise. + * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes. + * config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute + changes. + * config/arm/arm1020e.md (1020alu_op): Update for attribute changes. + (1020alu_shift_op): Likewise. + (1020alu_shift_reg_op): Likewise. + * config/arm/arm1026ejs.md (alu_op): Update for attribute changes. + (alu_shift_op): Likewise. + (alu_shift_reg_op): Likewise. + * config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes. + (11_alu_shift_op): Likewise. + (11_alu_shift_reg_op): Likewise. + * config/arm/arm926ejs.md (9_alu_op): Update for attribute changes. + (9_alu_shift_reg_op): Likewise. + * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes. + (cortex_a15_alu_shift): Likewise. + (cortex_a15_alu_shift_reg): Likewise. + * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes. + (cortex_a5_alu_shift): Likewise. + * config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute + changes. + (cortex_a53_alu_shift): Likewise. + * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute + changes. + (cortex_a7_alu_reg): Likewise. + (cortex_a7_alu_shift): Likewise. + * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes. + (cortex_a8_alu_shift): Likewise. + (cortex_a8_alu_shift_reg): Likewise. + (cortex_a8_mov): Likewise. + * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes. + (cortex_a9_dp_shift): Likewise. + * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes. + * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes. + (cortex_r4_mov): Likewise. + (cortex_r4_alu_shift): Likewise. + (cortex_r4_alu_shift_reg): Likewise. + * config/arm/fa526.md (526_alu_op): Update for attribute changes. + (526_alu_shift_op): Likewise. + * config/arm/fa606te.md (606te_alu_op): Update for attribute changes. + * config/arm/fa626te.md (626te_alu_op): Update for attribute changes. + (626te_alu_shift_op): Likewise. + * config/arm/fa726te.md (726te_shift_op): Update for attribute changes. + (726te_alu_op): Likewise. + (726te_alu_shift_op): Likewise. + (726te_alu_shift_reg_op): Likewise. + * config/arm/fmp626.md (mp626_alu_op): Update for attribute changes. + (mp626_alu_shift_op): Likewise. + * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes. + (pj4_alu_e1_conds): Likewise. + (pj4_alu): Likewise. + (pj4_alu_conds): Likewise. + (pj4_shift): Likewise. + (pj4_shift_conds): Likewise. + (pj4_alu_shift): Likewise. + (pj4_alu_shift_conds): Likewise. + * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes. + (cortexa7_older_only): Likewise. + (cortexa7_younger): Likewise. + + 2013-07-18 Sofiane Naci + + * config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr", + "xtab" and "sat". Move value "clz" from here to ... + (attriubte "type"): ... here. + (satsi_): Delete "insn" attribute. + (satsi__shift): Likewise. + (arm_zero_extendqisi2addsi): Likewise. + (arm_extendqisi2addsi): Likewise. + (clzsi2): Update for attribute changes. + (rbitsi2): Likewise. + * config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute. + (arm_usatsihi): Likewise. + * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. + + 2013-07-22 Kyrylo Tkachov + + * config/arm/predicates.md (shiftable_operator_strict_it): + New predicate. + * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): + Disable cond_exec version for arm_restrict_it. + (thumb2_smaxsi3): Convert to generate cond_exec. + (thumb2_sminsi3): Likewise. + (thumb32_umaxsi3): Likewise. + (thumb2_uminsi3): Likewise. + (thumb2_abssi2): Adjust constraints for arm_restrict_it. + (thumb2_neg_abssi2): Likewise. + (thumb2_mov_scc): Add alternative for 16-bit encoding. + (thumb2_movsicc_insn): Adjust alternatives. + (thumb2_mov_negscc): Disable for arm_restrict_it. + (thumb2_mov_negscc_strict_it): New pattern. + (thumb2_mov_notscc_strict_it): New pattern. + (thumb2_mov_notscc): Disable for arm_restrict_it. + (thumb2_ior_scc): Likewise. + (thumb2_ior_scc_strict_it): New pattern. + (thumb2_cond_move): Adjust for arm_restrict_it. + (thumb2_cond_arith): Disable for arm_restrict_it. + (thumb2_cond_arith_strict_it): New pattern. + (thumb2_cond_sub): Adjust for arm_restrict_it. + (thumb2_movcond): Likewise. + (thumb2_extendqisi_v6): Disable cond_exec variant for arm_restrict_it. + (thumb2_zero_extendhisi2_v6): Likewise. + (thumb2_zero_extendqisi2_v6): Likewise. + (orsi_notsi_si): Likewise. + (orsi_not_shiftsi_si): Likewise. + + 2013-07-22 Sofiane Naci + + * config/arm/arm.md (attribute "insn"): Delete. + (attribute "type"): Add "mov_imm", "mov_reg", "mov_shift", + "mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg". + (not_shiftsi): Update for attribute change. + (not_shiftsi_compare0): Likewise. + (not_shiftsi_compare0_scratch): Likewise. + (arm_one_cmplsi2): Likewise. + (thumb1_one_cmplsi2): Likewise. + (notsi_compare0): Likewise. + (notsi_compare0_scratch): Likewise. + (thumb1_movdi_insn): Likewise. + (arm_movsi_insn): Likewise. + (movhi_insn_arch4): Likewise. + (movhi_bytes): Likewise. + (arm_movqi_insn): Likewise. + (thumb1_movqi_insn): Likewise. + (arm32_movhf): Likewise. + (thumb1_movhf): Likewise. + (arm_movsf_soft_insn): Likewise. + (thumb1_movsf_insn): Likewise. + (thumb_movdf_insn): Likewise. + (movsicc_insn): Likewise. + (movsfcc_soft_insn): Likewise. + (and_scc): Likewise. + (cond_move): Likewise. + (if_move_not): Likewise. + (if_not_move): Likewise. + (if_shift_move): Likewise. + (if_move_shift): Likewise. + (if_shift_shift): Likewise. + (if_not_arith): Likewise. + (if_arith_not): Likewise. + (cond_move_not): Likewise. + * config/arm/neon.md (neon_mov): Update for attribute change. + (neon_mov): Likewise. + * config/arm/vfp.md (arm_movsi_vfp): Update for attribute change. + (thumb2_movsi_vfp): Likewise. + (movsf_vfp): Likewise. + (thumb2_movsf_vfp): Likewise. + * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change. + (cortexa7_older_only): Likewise. + (cortexa7_younger): Likewise. + * config/arm/arm1020e.md (1020alu_op): Update for attribute change. + (1020alu_shift_op): Likewise. + (1020alu_shift_reg_op): Likewise. + * config/arm/arm1026ejs.md (alu_op): Update for attribute change. + (alu_shift_op): Likewise. + (alu_shift_reg_op): Likewise. + * config/arm/arm1136jfs.md (11_alu_op): Update for attribute change. + (11_alu_shift_op): Likewise. + (11_alu_shift_reg_op): Likewise. + * config/arm/arm926ejs.md (9_alu_op): Update for attribute change. + (9_alu_shift_reg_op): Likewise. + * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change. + (cortex_a15_alu_shift): Likewise. + (cortex_a15_alu_shift_reg): Likewise. + * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change. + (cortex_a5_alu_shift): Likewise. + * config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change. + (cortex_a53_alu_shift): Likewise. + * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change. + (cortex_a7_alu_reg): Likewise. + (cortex_a7_alu_shift): Likewise. + * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. + (cortex_a8_alu_shift): Likewise. + (cortex_a8_alu_shift_reg): Likewise. + (cortex_a8_mov): Likewise. + * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change. + (cortex_a9_dp_shift): Likewise. + * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change. + * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change. + (cortex_r4_mov): Likewise. + (cortex_r4_alu_shift): Likewise. + (cortex_r4_alu_shift_reg): Likewise. + * config/arm/fa526.md (526_alu_op): Update for attribute change. + (526_alu_shift_op): Likewise. + * config/arm/fa606te.md (606te_alu_op): Update for attribute change. + * config/arm/fa626te.md (626te_alu_op): Update for attribute change. + (626te_alu_shift_op): Likewise. + * config/arm/fa726te.md (726te_shift_op): Update for attribute change. + (726te_alu_op): Likewise. + (726te_alu_shift_op): Likewise. + (726te_alu_shift_reg_op): Likewise. + * config/arm/fmp626.md (mp626_alu_op): Update for attribute change. + (mp626_alu_shift_op): Likewise. + * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change. + (pj4_alu_e1_conds): Likewise. + (pj4_alu): Likewise. + (pj4_alu_conds): Likewise. + (pj4_shift): Likewise. + (pj4_shift_conds): Likewise. + (pj4_alu_shift): Likewise. + (pj4_alu_shift_conds): Likewise. + + 2013-07-22 Kyrylo Tkachov + + * config/arm/constraints.md (Pd): Allow TARGET_THUMB + instead of TARGET_THUMB1. + (Pz): New constraint. + * config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit + encodings. + (compare_negsi_si): Likewise. + (compare_addsi2_op0): Likewise. + (compare_addsi2_op1): Likewise. + (addsi3_carryin_): Likewise. + (addsi3_carryin_alt2_): Likewise. + (addsi3_carryin_shift_): Disable cond_exec variant + for arm_restrict_it. + (subsi3_carryin): Likewise. + (arm_subsi3_insn): Add alternatives for 16-bit encoding. + (minmax_arithsi): Disable for arm_restrict_it. + (minmax_arithsi_non_canon): Adjust for arm_restrict_it. + (satsi_): Disable cond_exec variant for arm_restrict_it. + (satsi__shift): Likewise. + (arm_shiftsi3): Add alternative for 16-bit encoding. + (arm32_movhf): Disable for arm_restrict_it. + (arm_cmpdi_unsigned): Add alternatives for 16-bit encoding. + (arm_movtas_ze): Disable cond_exec variant for arm_restrict_it. + 2013-09-09 Kugan Vivekanandarajah Backport from trunk r201412. diff --git a/gcc-4_8-branch/gcc/config/arm/arm-fixed.md b/gcc-4_8-branch/gcc/config/arm/arm-fixed.md index ca9e1f833aa..dc8e7ac8c14 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm-fixed.md +++ b/gcc-4_8-branch/gcc/config/arm/arm-fixed.md @@ -405,9 +405,8 @@ "ssat%?\\t%0, #16, %2%S1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "insn" "sat") (set_attr "shift" "1") - (set_attr "type" "alu_shift")]) + (set_attr "type" "arlo_shift")]) (define_insn "arm_usatsihi" [(set (match_operand:HI 0 "s_register_operand" "=r") @@ -415,5 +414,5 @@ "TARGET_INT_SIMD" "usat%?\\t%0, #16, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") - (set_attr "insn" "sat")]) + (set_attr "predicable_short_it" "no")] +) diff --git a/gcc-4_8-branch/gcc/config/arm/arm.c b/gcc-4_8-branch/gcc/config/arm/arm.c index cdb674c925a..312d1ddfac0 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.c +++ b/gcc-4_8-branch/gcc/config/arm/arm.c @@ -8649,7 +8649,12 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) instruction we depend on is another ALU instruction, then we may have to account for an additional stall. */ if (shift_opnum != 0 - && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) + && (attr_type == TYPE_ARLO_SHIFT + || attr_type == TYPE_ARLO_SHIFT_REG + || attr_type == TYPE_MOV_SHIFT + || attr_type == TYPE_MVN_SHIFT + || attr_type == TYPE_MOV_SHIFT_REG + || attr_type == TYPE_MVN_SHIFT_REG)) { rtx shifted_operand; int opno; @@ -8930,12 +8935,12 @@ cortexa7_older_only (rtx insn) if (recog_memoized (insn) < 0) return false; - if (get_attr_insn (insn) == INSN_MOV) - return false; - switch (get_attr_type (insn)) { - case TYPE_ALU_REG: + case TYPE_ARLO_REG: + case TYPE_MVN_REG: + case TYPE_SHIFT: + case TYPE_SHIFT_REG: case TYPE_LOAD_BYTE: case TYPE_LOAD1: case TYPE_STORE1: @@ -8976,13 +8981,15 @@ cortexa7_younger (FILE *file, int verbose, rtx insn) return false; } - if (get_attr_insn (insn) == INSN_MOV) - return true; - switch (get_attr_type (insn)) { - case TYPE_SIMPLE_ALU_IMM: - case TYPE_SIMPLE_ALU_SHIFT: + case TYPE_ARLO_IMM: + case TYPE_EXTEND: + case TYPE_MVN_IMM: + case TYPE_MOV_IMM: + case TYPE_MOV_REG: + case TYPE_MOV_SHIFT: + case TYPE_MOV_SHIFT_REG: case TYPE_BRANCH: case TYPE_CALL: return true; diff --git a/gcc-4_8-branch/gcc/config/arm/arm.md b/gcc-4_8-branch/gcc/config/arm/arm.md index 1c6c5d38318..615c1ea3bb3 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.md +++ b/gcc-4_8-branch/gcc/config/arm/arm.md @@ -226,27 +226,26 @@ (set_attr "length" "4") (set_attr "pool_range" "250")]) -;; The instruction used to implement a particular pattern. This -;; information is used by pipeline descriptions to provide accurate -;; scheduling information. - -(define_attr "insn" - "mov,mvn,clz,mrs,msr,xtab,sat,other" - (const_string "other")) - ; TYPE attribute is used to classify instructions for use in scheduling. ; ; Instruction classification: ; -; alu_reg any alu instruction that doesn't hit memory or fp -; regs or have a shifted source operand and does not have -; an immediate operand. This is also the default. -; alu_shift any data instruction that doesn't hit memory or fp. -; regs, but has a source operand shifted by a constant. -; alu_shift_reg any data instruction that doesn't hit memory or fp. +; arlo_imm any arithmetic or logical instruction that doesn't have +; a shifted operand and has an immediate operand. This +; excludes MOV, MVN and RSB(S) immediate. +; arlo_reg any arithmetic or logical instruction that doesn't have +; a shifted or an immediate operand. This excludes +; MOV and MVN but includes MOVT. This is also the default. +; arlo_shift any arithmetic or logical instruction that has a source +; operand shifted by a constant. This excludes +; simple shifts. +; arlo_shift_reg as arlo_shift, with the shift amount specified in a +; register. ; block blockage insn, this blocks all functional units. ; branch branch. ; call subroutine call. +; clz count leading zeros (CLZ). +; extend extend instruction (SXTB, SXTH, UXTB, UXTH). ; f_2_r transfer from float to core (no memory needed). ; f_cvt conversion between float and integral. ; f_flag transfer of co-processor flags to the CPSR. @@ -272,16 +271,23 @@ ; load4 load 4 words from memory to arm registers. ; mla integer multiply accumulate. ; mlas integer multiply accumulate, flag setting. -; mov integer move. +; mov_imm simple MOV instruction that moves an immediate to +; register. This includes MOVW, but not MOVT. +; mov_reg simple MOV instruction that moves a register to another +; register. This includes MOVW, but not MOVT. +; mov_shift simple MOV instruction, shifted operand by a constant. +; mov_shift_reg simple MOV instruction, shifted operand by a register. ; mul integer multiply. ; muls integer multiply, flag setting. +; mvn_imm inverting move instruction, immediate. +; mvn_reg inverting move instruction, register. +; mvn_shift inverting move instruction, shifted operand by a constant. +; mvn_shift_reg inverting move instruction, shifted operand by a register. ; r_2_f transfer from core to float. ; sdiv signed division. -; simple_alu_imm simple alu instruction that doesn't hit memory or fp -; regs or have a shifted source operand and has an -; immediate operand. This currently only tracks very basic -; immediate alu operations. -; simple_alu_shift simple alu instruction with a shifted source operand. +; shift simple shift operation (LSL, LSR, ASR, ROR) with an +; immediate. +; shift_reg simple shift by a register. ; smlad signed multiply accumulate dual. ; smladx signed multiply accumulate dual reverse. ; smlal signed multiply accumulate long. @@ -382,89 +388,100 @@ ; wmmx_wxor (define_attr "type" - "simple_alu_imm,\ - alu_reg,\ - simple_alu_shift,\ - alu_shift,\ - alu_shift_reg,\ + "arlo_imm,\ + arlo_reg,\ + arlo_shift,\ + arlo_shift_reg,\ block,\ - float,\ - fdivd,\ - fdivs,\ - fmuls,\ - fmuld,\ - fmacs,\ - fmacd,\ - ffmas,\ - ffmad,\ - f_rints,\ - f_rintd,\ - f_minmaxs,\ - f_minmaxd,\ - f_flag,\ - f_loads,\ - f_loadd,\ - f_stores,\ - f_stored,\ + branch,\ + call,\ + clz,\ + extend,\ f_2_r,\ - r_2_f,\ f_cvt,\ - f_sels,\ + f_flag,\ + f_loadd,\ + f_loads,\ + f_minmaxd,\ + f_minmaxs,\ + f_rintd,\ + f_rints,\ f_seld,\ - branch,\ - call,\ + f_sels,\ + f_stored,\ + f_stores,\ + faddd,\ + fadds,\ + fcmpd,\ + fcmps,\ + fconstd,\ + fconsts,\ + fcpys,\ + fdivd,\ + fdivs,\ + ffarithd,\ + ffariths,\ + ffmad,\ + ffmas,\ + float,\ + fmacd,\ + fmacs,\ + fmuld,\ + fmuls,\ load_byte,\ load1,\ load2,\ load3,\ load4,\ - store1,\ - store2,\ - store3,\ - store4,\ - fconsts,\ - fconstd,\ - fadds,\ - faddd,\ - ffariths,\ - ffarithd,\ - fcmps,\ - fcmpd,\ - fcpys,\ - smulxy,\ - smlaxy,\ - smlalxy,\ - smulwy,\ - smlawx,\ - mul,\ - muls,\ mla,\ mlas,\ - umull,\ - umulls,\ - umlal,\ - umlals,\ - smull,\ - smulls,\ + mov_imm,\ + mov_reg,\ + mov_shift,\ + mov_shift_reg,\ + mul,\ + muls,\ + mvn_imm,\ + mvn_reg,\ + mvn_shift,\ + mvn_shift_reg,\ + r_2_f,\ + sdiv,\ + shift,\ + shift_reg,\ + smlad,\ + smladx,\ smlal,\ + smlald,\ smlals,\ + smlalxy,\ + smlawx,\ smlawy,\ - smuad,\ - smuadx,\ - smlad,\ - smladx,\ - smusd,\ - smusdx,\ + smlaxy,\ smlsd,\ smlsdx,\ + smlsld,\ + smmla,\ smmul,\ smmulr,\ - smmla,\ - umaal,\ - smlald,\ - smlsld,\ - sdiv,\ + smuad,\ + smuadx,\ + smull,\ + smulls,\ + smulwy,\ + smulxy,\ + smusd,\ + smusdx,\ + store1,\ + store2,\ + store3,\ + store4,\ udiv,\ + umaal,\ + umlal,\ + umlals,\ + umull,\ + umulls,\ wmmx_tandc,\ wmmx_tbcst,\ wmmx_textrc,\ @@ -524,7 +541,7 @@ wmmx_wunpckih,\ wmmx_wunpckil,\ wmmx_wxor" - (const_string "alu_reg")) + (const_string "arlo_reg")) ; Is this an (integer side) multiply with a 32-bit (or smaller) result? (define_attr "mul32" "no,yes" @@ -667,8 +684,8 @@ ; than one on the main cpu execution unit. (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" - "simple_alu_imm, alu_reg,\ - simple_alu_shift, alu_shift, float, fdivd, fdivs,\ + "arlo_imm, arlo_reg,\ + extend, shift, arlo_shift, float, fdivd, fdivs,\ wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\ wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\ wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\ @@ -917,13 +934,16 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk, r,k, r,r, k, r, k,k,r, k, r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, rk,k,r,rk,k, rk") - (match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 add%?\\t%0, %1, %2 + add%?\\t%0, %2 + add%?\\t%0, %1, %2 + add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 addw%?\\t%0, %1, %2 @@ -945,12 +965,13 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "simple_alu_imm") - (const_string "alu_reg"))) + (const_string "arlo_imm") + (const_string "arlo_reg"))) ] ) @@ -1031,7 +1052,7 @@ sub%.\\t%0, %1, #%n2 add%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm, simple_alu_imm, *")] + (set_attr "type" "arlo_imm,arlo_imm,*")] ) (define_insn "*addsi3_compare0_scratch" @@ -1047,19 +1068,22 @@ cmn%?\\t%0, %1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "type" "simple_alu_imm, simple_alu_imm, *") + (set_attr "type" "arlo_imm,arlo_imm,*") ] ) (define_insn "*compare_negsi_si" [(set (reg:CC_Z CC_REGNUM) (compare:CC_Z - (neg:SI (match_operand:SI 0 "s_register_operand" "r")) - (match_operand:SI 1 "s_register_operand" "r")))] + (neg:SI (match_operand:SI 0 "s_register_operand" "l,r")) + (match_operand:SI 1 "s_register_operand" "l,r")))] "TARGET_32BIT" "cmn%?\\t%1, %0" [(set_attr "conds" "set") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "arch" "t2,*") + (set_attr "length" "2,4") + (set_attr "predicable_short_it" "yes,no")] ) ;; This is the canonicalization of addsi3_compare0_for_combiner when the @@ -1134,7 +1158,7 @@ sub%.\\t%0, %1, #%n2 add%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + (set_attr "type" "arlo_imm,arlo_imm,*")] ) (define_insn "*addsi3_compare_op2" @@ -1151,65 +1175,84 @@ add%.\\t%0, %1, %2 sub%.\\t%0, %1, #%n2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + (set_attr "type" "arlo_imm,arlo_imm,*")] ) (define_insn "*compare_addsi2_op0" [(set (reg:CC_C CC_REGNUM) - (compare:CC_C - (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") - (match_operand:SI 1 "arm_add_operand" "I,L,r")) - (match_dup 0)))] + (compare:CC_C + (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r") + (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r")) + (match_dup 0)))] "TARGET_32BIT" "@ + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1 cmn%?\\t%0, %1 cmp%?\\t%0, #%n1 cmn%?\\t%0, %1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + (set_attr "arch" "t2,t2,*,*,*") + (set_attr "predicable_short_it" "yes,yes,no,no,no") + (set_attr "length" "2,2,4,4,4") + (set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")] ) (define_insn "*compare_addsi2_op1" [(set (reg:CC_C CC_REGNUM) - (compare:CC_C - (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") - (match_operand:SI 1 "arm_add_operand" "I,L,r")) - (match_dup 1)))] + (compare:CC_C + (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r") + (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r")) + (match_dup 1)))] "TARGET_32BIT" "@ + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1 cmn%?\\t%0, %1 cmp%?\\t%0, #%n1 cmn%?\\t%0, %1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] -) + (set_attr "arch" "t2,t2,*,*,*") + (set_attr "predicable_short_it" "yes,yes,no,no,no") + (set_attr "length" "2,2,4,4,4") + (set_attr "type" + "arlo_imm,*,arlo_imm,arlo_imm,*")] + ) (define_insn "*addsi3_carryin_" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r,r") - (match_operand:SI 2 "arm_not_operand" "rI,K")) - (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") + (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r") + (match_operand:SI 2 "arm_not_operand" "0,rI,K")) + (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] "TARGET_32BIT" "@ + adc%?\\t%0, %1 adc%?\\t%0, %1, %2 sbc%?\\t%0, %1, #%B2" [(set_attr "conds" "use") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "arch" "t2,*,*") + (set_attr "length" "4") + (set_attr "predicable_short_it" "yes,no,no")] ) (define_insn "*addsi3_carryin_alt2_" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) - (match_operand:SI 1 "s_register_operand" "%r,r")) - (match_operand:SI 2 "arm_rhs_operand" "rI,K")))] + [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") + (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) + (match_operand:SI 1 "s_register_operand" "%l,r,r")) + (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))] "TARGET_32BIT" "@ + adc%?\\t%0, %1 adc%?\\t%0, %1, %2 sbc%?\\t%0, %1, #%B2" [(set_attr "conds" "use") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "arch" "t2,*,*") + (set_attr "length" "4") + (set_attr "predicable_short_it" "yes,no,no")] ) (define_insn "*addsi3_carryin_shift_" @@ -1224,9 +1267,10 @@ "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "arlo_shift") + (const_string "arlo_shift_reg")))] ) (define_insn "*addsi3_carryin_clobercc_" @@ -1251,7 +1295,8 @@ rsc%?\\t%0, %2, %1" [(set_attr "conds" "use") (set_attr "arch" "*,a") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")] ) (define_insn "*subsi3_carryin_const" @@ -1303,8 +1348,8 @@ [(set_attr "conds" "use") (set_attr "predicable" "yes") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "arlo_shift") + (const_string "arlo_shift_reg")))] ) (define_insn "*rsbsi3_carryin_shift" @@ -1320,8 +1365,8 @@ [(set_attr "conds" "use") (set_attr "predicable" "yes") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "arlo_shift") + (const_string "arlo_shift_reg")))] ) ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. @@ -1568,11 +1613,15 @@ ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,rk,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,r,k,?n") - (match_operand:SI 2 "reg_or_int_operand" "r,I,r,r, r")))] + [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n") + (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))] "TARGET_32BIT" "@ + sub%?\\t%0, %1, %2 + sub%?\\t%0, %2 + sub%?\\t%0, %1, %2 + rsb%?\\t%0, %2, %1 rsb%?\\t%0, %2, %1 sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2 @@ -1586,9 +1635,11 @@ INTVAL (operands[1]), operands[0], operands[2], 0); DONE; " - [(set_attr "length" "4,4,4,4,16") + [(set_attr "length" "4,4,4,4,4,4,4,4,16") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*") (set_attr "predicable" "yes") - (set_attr "type" "*,simple_alu_imm,*,*,*")] + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no") + (set_attr "type" "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")] ) (define_peephole2 @@ -1618,7 +1669,7 @@ sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,*,*")] + (set_attr "type" "arlo_imm,*,*")] ) (define_insn "subsi3_compare" @@ -1633,7 +1684,7 @@ sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,*,*")] + (set_attr "type" "arlo_imm,*,*")] ) (define_expand "subsf3" @@ -2559,12 +2610,13 @@ ; ??? Check split length for Thumb-2 (define_insn_and_split "*arm_andsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") - (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r") + (and:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r") + (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))] "TARGET_32BIT" "@ and%?\\t%0, %1, %2 + and%?\\t%0, %1, %2 bic%?\\t%0, %1, #%B2 and%?\\t%0, %1, %2 #" @@ -2578,9 +2630,11 @@ INTVAL (operands[2]), operands[0], operands[1], 0); DONE; " - [(set_attr "length" "4,4,4,16") + [(set_attr "length" "4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*,simple_alu_imm")] + (set_attr "predicable_short_it" "no,yes,no,no,no") + (set_attr "type" + "arlo_imm,arlo_imm,*,*,arlo_imm")] ) (define_insn "*thumb1_andsi3_insn" @@ -2590,7 +2644,7 @@ "TARGET_THUMB1" "and\\t%0, %2" [(set_attr "length" "2") - (set_attr "type" "simple_alu_imm") + (set_attr "type" "arlo_imm") (set_attr "conds" "set")]) (define_insn "*andsi3_compare0" @@ -2607,7 +2661,7 @@ bic%.\\t%0, %1, #%B2 and%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + (set_attr "type" "arlo_imm,arlo_imm,*")] ) (define_insn "*andsi3_compare0_scratch" @@ -2623,7 +2677,7 @@ bic%.\\t%2, %0, #%B1 tst%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] + (set_attr "type" "arlo_imm,arlo_imm,*")] ) (define_insn "*zeroextractsi_compare0_scratch" @@ -2647,7 +2701,7 @@ [(set_attr "conds" "set") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "simple_alu_imm")] + (set_attr "type" "arlo_imm")] ) (define_insn_and_split "*ne_zeroextractsi" @@ -3197,8 +3251,8 @@ [(set_attr "predicable" "yes") (set_attr "shift" "2") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "arlo_shift") + (const_string "arlo_shift_reg")))] ) (define_insn "*andsi_notsi_si_compare0" @@ -3333,12 +3387,13 @@ ) (define_insn_and_split "*iorsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") - (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r,r") - (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r") + (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r") + (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))] "TARGET_32BIT" "@ orr%?\\t%0, %1, %2 + orr%?\\t%0, %1, %2 orn%?\\t%0, %1, #%B2 orr%?\\t%0, %1, %2 #" @@ -3348,14 +3403,15 @@ || (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))" [(clobber (const_int 0))] { - arm_split_constant (IOR, SImode, curr_insn, + arm_split_constant (IOR, SImode, curr_insn, INTVAL (operands[2]), operands[0], operands[1], 0); DONE; } - [(set_attr "length" "4,4,4,16") - (set_attr "arch" "32,t2,32,32") + [(set_attr "length" "4,4,4,4,16") + (set_attr "arch" "32,t2,t2,32,32") (set_attr "predicable" "yes") - (set_attr "type" "simple_alu_imm,simple_alu_imm,*,*")] + (set_attr "predicable_short_it" "no,yes,no,no,no") + (set_attr "type" "arlo_imm,*,arlo_imm,*,*")] ) (define_insn "*thumb1_iorsi3_insn" @@ -3390,7 +3446,7 @@ "TARGET_32BIT" "orr%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,*")] + (set_attr "type" "arlo_imm,*")] ) (define_insn "*iorsi3_compare0_scratch" @@ -3402,7 +3458,7 @@ "TARGET_32BIT" "orr%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm, *")] + (set_attr "type" "arlo_imm,*")] ) (define_expand "xordi3" @@ -3507,13 +3563,14 @@ ) (define_insn_and_split "*arm_xorsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") - (match_operand:SI 2 "reg_or_int_operand" "I,r,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r") + (xor:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r") + (match_operand:SI 2 "reg_or_int_operand" "I,l,r,?n")))] "TARGET_32BIT" "@ eor%?\\t%0, %1, %2 eor%?\\t%0, %1, %2 + eor%?\\t%0, %1, %2 #" "TARGET_32BIT && CONST_INT_P (operands[2]) @@ -3524,9 +3581,10 @@ INTVAL (operands[2]), operands[0], operands[1], 0); DONE; } - [(set_attr "length" "4,4,16") + [(set_attr "length" "4,4,4,16") (set_attr "predicable" "yes") - (set_attr "type" "simple_alu_imm,*,*")] + (set_attr "predicable_short_it" "no,yes,no,no") + (set_attr "type" "arlo_imm,*,*,*")] ) (define_insn "*thumb1_xorsi3_insn" @@ -3537,7 +3595,7 @@ "eor\\t%0, %2" [(set_attr "length" "2") (set_attr "conds" "set") - (set_attr "type" "simple_alu_imm")] + (set_attr "type" "arlo_imm")] ) (define_insn "*xorsi3_compare0" @@ -3550,7 +3608,7 @@ "TARGET_32BIT" "eor%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,*")] + (set_attr "type" "arlo_imm,*")] ) (define_insn "*xorsi3_compare0_scratch" @@ -3561,7 +3619,7 @@ "TARGET_32BIT" "teq%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm, *")] + (set_attr "type" "arlo_imm,*")] ) ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), @@ -3914,7 +3972,7 @@ (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT && !arm_eliminable_register (operands[1])" + "TARGET_32BIT && !arm_eliminable_register (operands[1]) && !arm_restrict_it" "* { enum rtx_code code = GET_CODE (operands[4]); @@ -3951,14 +4009,15 @@ ; Reject the frame pointer in operand[1], since reloading this after ; it has been eliminated can cause carnage. (define_insn_and_split "*minmax_arithsi_non_canon" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") + [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") (minus:SI - (match_operand:SI 1 "s_register_operand" "0,?r") + (match_operand:SI 1 "s_register_operand" "0,?Ts") (match_operator:SI 4 "minmax_operator" - [(match_operand:SI 2 "s_register_operand" "r,r") - (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) + [(match_operand:SI 2 "s_register_operand" "Ts,Ts") + (match_operand:SI 3 "arm_rhs_operand" "TsI,TsI")]))) (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT && !arm_eliminable_register (operands[1])" + "TARGET_32BIT && !arm_eliminable_register (operands[1]) + && !(arm_restrict_it && CONST_INT_P (operands[3]))" "#" "TARGET_32BIT && !arm_eliminable_register (operands[1]) && reload_completed" [(set (reg:CC CC_REGNUM) @@ -4021,7 +4080,8 @@ return "usat%?\t%0, %1, %3"; } [(set_attr "predicable" "yes") - (set_attr "insn" "sat")]) + (set_attr "predicable_short_it" "no")] +) (define_insn "*satsi__shift" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -4046,9 +4106,9 @@ return "usat%?\t%0, %1, %4%S3"; } [(set_attr "predicable" "yes") - (set_attr "insn" "sat") + (set_attr "predicable_short_it" "no") (set_attr "shift" "3") - (set_attr "type" "alu_shift")]) + (set_attr "type" "arlo_shift")]) ;; Shift and rotation insns @@ -4151,6 +4211,7 @@ "TARGET_THUMB1" "lsl\\t%0, %1, %2" [(set_attr "length" "2") + (set_attr "type" "shift,shift_reg") (set_attr "conds" "set")]) (define_expand "ashrdi3" @@ -4233,8 +4294,7 @@ "TARGET_32BIT" "mov\\t%0, %1, rrx" [(set_attr "conds" "use") - (set_attr "insn" "mov") - (set_attr "type" "alu_shift")] + (set_attr "type" "mov_shift")] ) (define_expand "ashrsi3" @@ -4256,6 +4316,7 @@ "TARGET_THUMB1" "asr\\t%0, %1, %2" [(set_attr "length" "2") + (set_attr "type" "shift,shift_reg") (set_attr "conds" "set")]) (define_expand "lshrdi3" @@ -4352,6 +4413,7 @@ "TARGET_THUMB1" "lsr\\t%0, %1, %2" [(set_attr "length" "2") + (set_attr "type" "shift,shift_reg") (set_attr "conds" "set")]) (define_expand "rotlsi3" @@ -4397,68 +4459,67 @@ (match_operand:SI 2 "register_operand" "l")))] "TARGET_THUMB1" "ror\\t%0, %0, %2" - [(set_attr "length" "2")] + [(set_attr "type" "shift_reg") + (set_attr "length" "2")] ) (define_insn "*arm_shiftsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "reg_or_int_operand" "rM")]))] + [(match_operand:SI 1 "s_register_operand" "0,r,r") + (match_operand:SI 2 "reg_or_int_operand" "l,M,r")]))] "TARGET_32BIT" "* return arm_output_shift(operands, 0);" [(set_attr "predicable" "yes") + (set_attr "arch" "t2,*,*") + (set_attr "predicable_short_it" "yes,no,no") + (set_attr "length" "4") (set_attr "shift" "1") - (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")] ) (define_insn "*shiftsi3_compare" [(set (reg:CC CC_REGNUM) (compare:CC (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rM")]) + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r") + (set (match_operand:SI 0 "s_register_operand" "=r,r") (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] "TARGET_32BIT" "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1") - (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (set_attr "type" "arlo_shift,arlo_shift_reg")] ) (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rM")]) + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r") + (set (match_operand:SI 0 "s_register_operand" "=r,r") (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] "TARGET_32BIT" "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1") - (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (set_attr "type" "arlo_shift,arlo_shift_reg")] ) (define_insn "*shiftsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rM")]) + [(match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) - (clobber (match_scratch:SI 0 "=r"))] + (clobber (match_scratch:SI 0 "=r,r"))] "TARGET_32BIT" "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") - (set_attr "shift" "1")] + (set_attr "shift" "1") + (set_attr "type" "shift,shift_reg")] ) (define_insn "*not_shiftsi" @@ -4471,9 +4532,8 @@ [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "shift" "1") - (set_attr "insn" "mvn") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "mvn_shift,mvn_shift_reg")]) (define_insn "*not_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) @@ -4488,9 +4548,8 @@ "mvn%.\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "insn" "mvn") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "mvn_shift,mvn_shift_reg")]) (define_insn "*not_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) @@ -4504,9 +4563,8 @@ "mvn%.\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "insn" "mvn") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "mvn_shift,mvn_shift_reg")]) ;; We don't really have extzv, but defining this using shifts helps ;; to reduce register pressure later on. @@ -5234,7 +5292,7 @@ (set_attr "predicable_short_it" "yes,no") (set_attr "arch" "t2,*") (set_attr "length" "4") - (set_attr "insn" "mvn")] + (set_attr "type" "mvn_reg")] ) (define_insn "*thumb1_one_cmplsi2" @@ -5243,7 +5301,7 @@ "TARGET_THUMB1" "mvn\\t%0, %1" [(set_attr "length" "2") - (set_attr "insn" "mvn")] + (set_attr "type" "mvn_reg")] ) (define_insn "*notsi_compare0" @@ -5255,7 +5313,7 @@ "TARGET_32BIT" "mvn%.\\t%0, %1" [(set_attr "conds" "set") - (set_attr "insn" "mvn")] + (set_attr "type" "mvn_reg")] ) (define_insn "*notsi_compare0_scratch" @@ -5266,7 +5324,7 @@ "TARGET_32BIT" "mvn%.\\t%0, %1" [(set_attr "conds" "set") - (set_attr "insn" "mvn")] + (set_attr "type" "mvn_reg")] ) ;; Fixed <--> Floating conversion insns @@ -5527,7 +5585,7 @@ [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr "type" "simple_alu_shift, load_byte")] + (set_attr "type" "extend,load_byte")] ) (define_insn "*arm_zero_extendhisi2" @@ -5537,7 +5595,7 @@ "@ # ldr%(h%)\\t%0, %1" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr "type" "arlo_shift,load_byte") (set_attr "predicable" "yes")] ) @@ -5549,7 +5607,7 @@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "type" "simple_alu_shift,load_byte")] + (set_attr "type" "extend,load_byte")] ) (define_insn "*arm_zero_extendhisi2addsi" @@ -5558,7 +5616,7 @@ (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "uxtah%?\\t%0, %2, %1" - [(set_attr "type" "alu_shift") + [(set_attr "type" "arlo_shift") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")] ) @@ -5608,7 +5666,7 @@ # ldrb\\t%0, %1" [(set_attr "length" "4,2") - (set_attr "type" "alu_shift,load_byte") + (set_attr "type" "arlo_shift,load_byte") (set_attr "pool_range" "*,32")] ) @@ -5620,7 +5678,7 @@ uxtb\\t%0, %1 ldrb\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "simple_alu_shift,load_byte")] + (set_attr "type" "extend,load_byte")] ) (define_insn "*arm_zero_extendqisi2" @@ -5631,7 +5689,7 @@ # ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "length" "8,4") - (set_attr "type" "alu_shift,load_byte") + (set_attr "type" "arlo_shift,load_byte") (set_attr "predicable" "yes")] ) @@ -5642,7 +5700,7 @@ "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr "type" "simple_alu_shift,load_byte") + [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes")] ) @@ -5654,8 +5712,7 @@ "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "insn" "xtab") - (set_attr "type" "alu_shift")] + (set_attr "type" "arlo_shift")] ) (define_split @@ -5818,7 +5875,7 @@ [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr "type" "simple_alu_shift,load_byte") + (set_attr "type" "extend,load_byte") (set_attr "pool_range" "*,1018")] ) @@ -5877,7 +5934,7 @@ # ldr%(sh%)\\t%0, %1" [(set_attr "length" "8,4") - (set_attr "type" "alu_shift,load_byte") + (set_attr "type" "arlo_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5891,7 +5948,7 @@ "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" - [(set_attr "type" "simple_alu_shift,load_byte") + [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,256") @@ -5978,7 +6035,7 @@ # ldr%(sb%)\\t%0, %1" [(set_attr "length" "8,4") - (set_attr "type" "alu_shift,load_byte") + (set_attr "type" "arlo_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5992,7 +6049,7 @@ "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" - [(set_attr "type" "simple_alu_shift,load_byte") + [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -6004,8 +6061,7 @@ (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" - [(set_attr "type" "alu_shift") - (set_attr "insn" "xtab") + [(set_attr "type" "arlo_shift") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")] ) @@ -6106,7 +6162,7 @@ (const_int 2) (if_then_else (eq_attr "is_arch6" "yes") (const_int 4) (const_int 6))]) - (set_attr "type" "simple_alu_shift,load_byte,load_byte")] + (set_attr "type" "extend,load_byte,load_byte")] ) (define_expand "extendsfdf2" @@ -6365,8 +6421,7 @@ } }" [(set_attr "length" "4,4,6,2,2,6,4,4") - (set_attr "type" "*,*,*,load2,store2,load2,store2,*") - (set_attr "insn" "*,mov,*,*,*,*,*,mov") + (set_attr "type" "*,mov_reg,*,load2,store2,load2,store2,mov_reg") (set_attr "pool_range" "*,*,*,*,*,1018,*,*")] ) @@ -6481,8 +6536,7 @@ movw%?\\t%0, %1 ldr%?\\t%0, %1 str%?\\t%1, %0" - [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1,store1") - (set_attr "insn" "mov,mov,mvn,mov,*,*") + [(set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,load1,store1") (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,*,*,4096,*") (set_attr "neg_pool_range" "*,*,*,*,4084,*")] @@ -6784,7 +6838,7 @@ cmp%?\\t%0, #0 sub%.\\t%0, %1, #0" [(set_attr "conds" "set") - (set_attr "type" "simple_alu_imm,simple_alu_imm")] + (set_attr "type" "arlo_imm,arlo_imm")] ) ;; Subroutine to store a half word from a register into memory. @@ -7198,14 +7252,13 @@ str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "predicable" "yes") - (set_attr "insn" "mov,mvn,*,*") (set_attr "pool_range" "*,*,*,256") (set_attr "neg_pool_range" "*,*,*,244") (set_attr_alternative "type" [(if_then_else (match_operand 1 "const_int_operand" "") - (const_string "simple_alu_imm" ) - (const_string "*")) - (const_string "simple_alu_imm") + (const_string "mov_imm" ) + (const_string "mov_reg")) + (const_string "mvn_imm") (const_string "store1") (const_string "load1")])] ) @@ -7219,8 +7272,7 @@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi" [(set_attr "predicable" "yes") - (set_attr "insn" "mov, mov,mvn") - (set_attr "type" "simple_alu_imm,*,simple_alu_imm")] + (set_attr "type" "mov_imm,mov_reg,mvn_imm")] ) (define_expand "thumb_movhi_clobber" @@ -7359,8 +7411,7 @@ str%(b%)\\t%1, %0 ldr%(b%)\\t%0, %1 str%(b%)\\t%1, %0" - [(set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1, store1, load1, store1") - (set_attr "insn" "mov,mov,mov,mov,mvn,*,*,*,*") + [(set_attr "type" "mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load1,store1,load1,store1") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no") (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any") @@ -7381,8 +7432,7 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "simple_alu_imm,load1,store1,*,*,simple_alu_imm") - (set_attr "insn" "*,*,*,mov,mov,mov") + (set_attr "type" "arlo_imm,load1,store1,mov_reg,mov_imm,mov_imm") (set_attr "pool_range" "*,32,*,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")]) @@ -7411,7 +7461,7 @@ (define_insn "*arm32_movhf" [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r") (match_operand:HF 1 "general_operand" " m,r,r,F"))] - "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) && !arm_restrict_it && ( s_register_operand (operands[0], HFmode) || s_register_operand (operands[1], HFmode))" "* @@ -7447,8 +7497,7 @@ } " [(set_attr "conds" "unconditional") - (set_attr "type" "load1,store1,*,*") - (set_attr "insn" "*,*,mov,mov") + (set_attr "type" "load1,store1,mov_reg,mov_reg") (set_attr "length" "4,4,4,8") (set_attr "predicable" "yes")] ) @@ -7483,8 +7532,7 @@ } " [(set_attr "length" "2") - (set_attr "type" "*,load1,store1,*,*") - (set_attr "insn" "mov,*,*,mov,mov") + (set_attr "type" "mov_reg,load1,store1,mov_reg,mov_reg") (set_attr "pool_range" "*,1018,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond")]) @@ -7538,8 +7586,8 @@ ldr%?\\t%0, %1\\t%@ float str%?\\t%1, %0\\t%@ float" [(set_attr "predicable" "yes") - (set_attr "type" "*,load1,store1") - (set_attr "insn" "mov,*,*") + (set_attr "predicable_short_it" "no") + (set_attr "type" "mov_reg,load1,store1") (set_attr "arm_pool_range" "*,4096,*") (set_attr "thumb2_pool_range" "*,4094,*") (set_attr "arm_neg_pool_range" "*,4084,*") @@ -7562,9 +7610,8 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "*,load1,store1,load1,store1,*,*") + (set_attr "type" "*,load1,store1,load1,store1,mov_reg,mov_reg") (set_attr "pool_range" "*,*,*,1018,*,*,*") - (set_attr "insn" "*,*,*,*,*,mov,mov") (set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")] ) @@ -7695,8 +7742,7 @@ } " [(set_attr "length" "4,2,2,6,4,4") - (set_attr "type" "*,load2,store2,load2,store2,*") - (set_attr "insn" "*,*,*,*,*,mov") + (set_attr "type" "*,load2,store2,load2,store2,mov_reg") (set_attr "pool_range" "*,*,*,1018,*,*")] ) @@ -8472,7 +8518,7 @@ (set_attr "arch" "t2,t2,any,any") (set_attr "length" "2,2,4,4") (set_attr "predicable" "yes") - (set_attr "type" "*,*,*,simple_alu_imm")] + (set_attr "type" "*,*,*,arlo_imm")] ) (define_insn "*cmpsi_shiftsi" @@ -8486,7 +8532,7 @@ [(set_attr "conds" "set") (set_attr "shift" "1") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn "*cmpsi_shiftsi_swp" [(set (reg:CC_SWP CC_REGNUM) @@ -8499,7 +8545,7 @@ [(set_attr "conds" "set") (set_attr "shift" "1") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn "*arm_cmpsi_negshiftsi_si" [(set (reg:CC_Z CC_REGNUM) @@ -8512,8 +8558,8 @@ "cmn%?\\t%0, %2%S1" [(set_attr "conds" "set") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg"))) + (const_string "arlo_shift") + (const_string "arlo_shift_reg"))) (set_attr "predicable" "yes")] ) @@ -8560,8 +8606,9 @@ (define_insn_and_split "*arm_cmpdi_unsigned" [(set (reg:CC_CZ CC_REGNUM) - (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") - (match_operand:DI 1 "arm_di_operand" "rDi")))] + (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r") + (match_operand:DI 1 "arm_di_operand" "Py,r,rDi")))] + "TARGET_32BIT" "#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1" "&& reload_completed" @@ -8580,7 +8627,9 @@ operands[1] = gen_lowpart (SImode, operands[1]); } [(set_attr "conds" "set") - (set_attr "length" "8")] + (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "arch" "t2,t2,*") + (set_attr "length" "6,6,8")] ) (define_insn "*arm_cmpdi_zero" @@ -9162,20 +9211,19 @@ } [(set_attr "length" "4,4,4,4,8,8,8,8") (set_attr "conds" "use") - (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") (set_attr_alternative "type" [(if_then_else (match_operand 2 "const_int_operand" "") - (const_string "simple_alu_imm") - (const_string "*")) - (const_string "simple_alu_imm") + (const_string "mov_imm") + (const_string "mov_reg")) + (const_string "mvn_imm") (if_then_else (match_operand 1 "const_int_operand" "") - (const_string "simple_alu_imm") - (const_string "*")) - (const_string "simple_alu_imm") - (const_string "*") - (const_string "*") - (const_string "*") - (const_string "*")])] + (const_string "mov_imm") + (const_string "mov_reg")) + (const_string "mvn_imm") + (const_string "mov_reg") + (const_string "mov_reg") + (const_string "mov_reg") + (const_string "mov_reg")])] ) (define_insn "*movsfcc_soft_insn" @@ -9189,7 +9237,7 @@ mov%D3\\t%0, %2 mov%d3\\t%0, %1" [(set_attr "conds" "use") - (set_attr "insn" "mov")] + (set_attr "type" "mov_reg")] ) @@ -10053,7 +10101,7 @@ (if_then_else (match_operand:SI 3 "mult_operator" "") (const_string "no") (const_string "yes"))]) - (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") @@ -10090,7 +10138,7 @@ [(set_attr "conds" "set") (set_attr "shift" "4") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn "*arith_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) @@ -10107,7 +10155,7 @@ [(set_attr "conds" "set") (set_attr "shift" "4") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn "*sub_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -10120,7 +10168,7 @@ [(set_attr "predicable" "yes") (set_attr "shift" "3") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn "*sub_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) @@ -10138,7 +10186,7 @@ [(set_attr "conds" "set") (set_attr "shift" "3") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn "*sub_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) @@ -10154,7 +10202,7 @@ [(set_attr "conds" "set") (set_attr "shift" "3") (set_attr "arch" "32,a") - (set_attr "type" "alu_shift,alu_shift_reg")]) + (set_attr "type" "arlo_shift,arlo_shift_reg")]) (define_insn_and_split "*and_scc" @@ -10182,7 +10230,7 @@ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); } [(set_attr "conds" "use") - (set_attr "insn" "mov") + (set_attr "type" "mov_reg") (set_attr "length" "8")] ) @@ -10361,7 +10409,7 @@ return \"\"; " [(set_attr "conds" "use") - (set_attr "insn" "mov") + (set_attr "type" "mov_reg") (set_attr "length" "4,4,8")] ) @@ -11094,9 +11142,9 @@ (set_attr "length" "4,4,8,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "simple_alu_imm" ) + (const_string "arlo_imm" ) (const_string "*")) - (const_string "simple_alu_imm") + (const_string "arlo_imm") (const_string "*") (const_string "*")])] ) @@ -11136,9 +11184,9 @@ (set_attr "length" "4,4,8,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "simple_alu_imm" ) + (const_string "arlo_imm" ) (const_string "*")) - (const_string "simple_alu_imm") + (const_string "arlo_imm") (const_string "*") (const_string "*")])] ) @@ -11324,7 +11372,7 @@ mov%d4\\t%0, %1\;mvn%D4\\t%0, %2 mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2" [(set_attr "conds" "use") - (set_attr "insn" "mvn") + (set_attr "type" "mvn_reg") (set_attr "length" "4,8,8")] ) @@ -11357,7 +11405,7 @@ mov%D4\\t%0, %1\;mvn%d4\\t%0, %2 mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2" [(set_attr "conds" "use") - (set_attr "insn" "mvn") + (set_attr "type" "mvn_reg") (set_attr "length" "4,8,8")] ) @@ -11395,10 +11443,9 @@ [(set_attr "conds" "use") (set_attr "shift" "2") (set_attr "length" "4,8,8") - (set_attr "insn" "mov") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "mov_shift") + (const_string "mov_shift_reg")))] ) (define_insn "*ifcompare_move_shift" @@ -11435,10 +11482,9 @@ [(set_attr "conds" "use") (set_attr "shift" "2") (set_attr "length" "4,8,8") - (set_attr "insn" "mov") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "mov_shift") + (const_string "mov_shift_reg")))] ) (define_insn "*ifcompare_shift_shift" @@ -11476,12 +11522,11 @@ [(set_attr "conds" "use") (set_attr "shift" "1") (set_attr "length" "8") - (set_attr "insn" "mov") (set (attr "type") (if_then_else (and (match_operand 2 "const_int_operand" "") (match_operand 4 "const_int_operand" "")) - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "mov_shift") + (const_string "mov_shift_reg")))] ) (define_insn "*ifcompare_not_arith" @@ -11513,7 +11558,7 @@ "TARGET_ARM" "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3" [(set_attr "conds" "use") - (set_attr "insn" "mvn") + (set_attr "type" "mvn_reg") (set_attr "length" "8")] ) @@ -11546,7 +11591,7 @@ "TARGET_ARM" "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3" [(set_attr "conds" "use") - (set_attr "insn" "mvn") + (set_attr "type" "mvn_reg") (set_attr "length" "8")] ) @@ -11994,7 +12039,7 @@ mvn%D4\\t%0, %2 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2" [(set_attr "conds" "use") - (set_attr "insn" "mvn") + (set_attr "type" "mvn_reg") (set_attr "length" "4,8")] ) @@ -12389,7 +12434,7 @@ "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "insn" "clz")]) + (set_attr "type" "clz")]) (define_insn "rbitsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -12397,7 +12442,7 @@ "TARGET_32BIT && arm_arch_thumb2" "rbit%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "insn" "clz")]) + (set_attr "type" "clz")]) (define_expand "ctzsi2" [(set (match_operand:SI 0 "s_register_operand" "") @@ -12550,7 +12595,8 @@ "arm_arch_thumb2" "movt%?\t%0, %L1" [(set_attr "predicable" "yes") - (set_attr "length" "4")] + (set_attr "predicable_short_it" "no") + (set_attr "length" "4")] ) (define_insn "*arm_rev" diff --git a/gcc-4_8-branch/gcc/config/arm/arm1020e.md b/gcc-4_8-branch/gcc/config/arm/arm1020e.md index 94e8c35f839..317e4cd4ad6 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm1020e.md +++ b/gcc-4_8-branch/gcc/config/arm/arm1020e.md @@ -66,13 +66,14 @@ ;; ALU operations with no shifted operand (define_insn_reservation "1020alu_op" 1 (and (eq_attr "tune" "arm1020e,arm1022e") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "1020a_e,1020a_m,1020a_w") ;; ALU operations with a shift-by-constant operand (define_insn_reservation "1020alu_shift_op" 1 (and (eq_attr "tune" "arm1020e,arm1022e") - (eq_attr "type" "simple_alu_shift,alu_shift")) + (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) "1020a_e,1020a_m,1020a_w") ;; ALU operations with a shift-by-register operand @@ -81,7 +82,7 @@ ;; the execute stage. (define_insn_reservation "1020alu_shift_reg_op" 2 (and (eq_attr "tune" "arm1020e,arm1022e") - (eq_attr "type" "alu_shift_reg")) + (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) "1020a_e*2,1020a_m,1020a_w") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/arm1026ejs.md b/gcc-4_8-branch/gcc/config/arm/arm1026ejs.md index 67b985ce68e..9112122d67b 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm1026ejs.md +++ b/gcc-4_8-branch/gcc/config/arm/arm1026ejs.md @@ -66,13 +66,14 @@ ;; ALU operations with no shifted operand (define_insn_reservation "alu_op" 1 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "a_e,a_m,a_w") ;; ALU operations with a shift-by-constant operand (define_insn_reservation "alu_shift_op" 1 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "simple_alu_shift,alu_shift")) + (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) "a_e,a_m,a_w") ;; ALU operations with a shift-by-register operand @@ -81,7 +82,7 @@ ;; the execute stage. (define_insn_reservation "alu_shift_reg_op" 2 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "alu_shift_reg")) + (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) "a_e*2,a_m,a_w") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/arm1136jfs.md b/gcc-4_8-branch/gcc/config/arm/arm1136jfs.md index 3030182acca..f83b9d14f2b 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm1136jfs.md +++ b/gcc-4_8-branch/gcc/config/arm/arm1136jfs.md @@ -75,13 +75,14 @@ ;; ALU operations with no shifted operand (define_insn_reservation "11_alu_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "e_1,e_2,e_3,e_wb") ;; ALU operations with a shift-by-constant operand (define_insn_reservation "11_alu_shift_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "simple_alu_shift,alu_shift")) + (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) "e_1,e_2,e_3,e_wb") ;; ALU operations with a shift-by-register operand @@ -90,7 +91,7 @@ ;; the shift stage. (define_insn_reservation "11_alu_shift_reg_op" 3 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "alu_shift_reg")) + (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) "e_1*2,e_2,e_3,e_wb") ;; alu_ops can start sooner, if there is no shifter dependency diff --git a/gcc-4_8-branch/gcc/config/arm/arm926ejs.md b/gcc-4_8-branch/gcc/config/arm/arm926ejs.md index 4db404e766f..8c38e86ce66 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm926ejs.md +++ b/gcc-4_8-branch/gcc/config/arm/arm926ejs.md @@ -58,7 +58,9 @@ ;; ALU operations with no shifted operand (define_insn_reservation "9_alu_op" 1 (and (eq_attr "tune" "arm926ejs") - (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\ + mov_imm,mov_reg,mov_shift,\ + mvn_imm,mvn_reg,mvn_shift")) "e,m,w") ;; ALU operations with a shift-by-register operand @@ -67,7 +69,7 @@ ;; the execute stage. (define_insn_reservation "9_alu_shift_reg_op" 2 (and (eq_attr "tune" "arm926ejs") - (eq_attr "type" "alu_shift_reg")) + (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) "e*2,m,w") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/constraints.md b/gcc-4_8-branch/gcc/config/arm/constraints.md index de7f4c20d5f..d7b9cb99808 100644 --- a/gcc-4_8-branch/gcc/config/arm/constraints.md +++ b/gcc-4_8-branch/gcc/config/arm/constraints.md @@ -170,9 +170,9 @@ && ival > 1020 && ival <= 1275"))) (define_constraint "Pd" - "@internal In Thumb-1 state a constant in the range 0 to 7" + "@internal In Thumb state a constant in the range 0 to 7" (and (match_code "const_int") - (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7"))) + (match_test "TARGET_THUMB && ival >= 0 && ival <= 7"))) (define_constraint "Pe" "@internal In Thumb-1 state a constant in the range 256 to +510" @@ -214,6 +214,11 @@ (and (match_code "const_int") (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255"))) +(define_constraint "Pz" + "@internal In Thumb-2 state the constant 0" + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && (ival == 0)"))) + (define_constraint "G" "In ARM/Thumb-2 state the floating-point constant 0." (and (match_code "const_double") diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-a15.md b/gcc-4_8-branch/gcc/config/arm/cortex-a15.md index 981d055c668..4ad87121d6d 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-a15.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-a15.md @@ -61,14 +61,16 @@ ;; Simple ALU without shift (define_insn_reservation "cortex_a15_alu" 2 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "alu_reg,simple_alu_imm") + (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,\ + mvn_imm,mvn_reg") (eq_attr "neon_type" "none"))) "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") ;; ALU ops with immediate shift (define_insn_reservation "cortex_a15_alu_shift" 3 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "simple_alu_shift,alu_shift") + (and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift") (eq_attr "neon_type" "none"))) "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)") @@ -76,7 +78,7 @@ ;; ALU ops with register controlled shift (define_insn_reservation "cortex_a15_alu_shift_reg" 3 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "alu_shift_reg") + (and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg") (eq_attr "neon_type" "none"))) "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\ |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\ diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-a5.md b/gcc-4_8-branch/gcc/config/arm/cortex-a5.md index 963d5babd7b..1400c47d95a 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-a5.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-a5.md @@ -58,12 +58,15 @@ (define_insn_reservation "cortex_a5_alu" 2 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "cortex_a5_ex1") (define_insn_reservation "cortex_a5_alu_shift" 2 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg")) "cortex_a5_ex1") ;; Forwarding path for unshifted operands. diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-a53.md b/gcc-4_8-branch/gcc/config/arm/cortex-a53.md index e67fe55ecd3..2f9107994c9 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-a53.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-a53.md @@ -67,12 +67,15 @@ (define_insn_reservation "cortex_a53_alu" 2 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "cortex_a53_slot_any") (define_insn_reservation "cortex_a53_alu_shift" 2 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "alu_shift,alu_shift_reg")) + (eq_attr "type" "arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg")) "cortex_a53_slot_any") ;; Forwarding path for unshifted operands. diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-a7.md b/gcc-4_8-branch/gcc/config/arm/cortex-a7.md index 960174fb90a..e14413d5083 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-a7.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-a7.md @@ -88,9 +88,9 @@ ;; ALU instruction with an immediate operand can dual-issue. (define_insn_reservation "cortex_a7_alu_imm" 2 (and (eq_attr "tune" "cortexa7") - (and (ior (eq_attr "type" "simple_alu_imm") - (ior (eq_attr "type" "simple_alu_shift") - (and (eq_attr "insn" "mov") + (and (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm") + (ior (eq_attr "type" "extend") + (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg") (not (eq_attr "length" "8"))))) (eq_attr "neon_type" "none"))) "cortex_a7_ex2|cortex_a7_ex1") @@ -99,13 +99,15 @@ ;; with a younger immediate-based instruction. (define_insn_reservation "cortex_a7_alu_reg" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "alu_reg") + (and (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg") (eq_attr "neon_type" "none"))) "cortex_a7_ex1") (define_insn_reservation "cortex_a7_alu_shift" 2 (and (eq_attr "tune" "cortexa7") - (and (eq_attr "type" "alu_shift,alu_shift_reg") + (and (eq_attr "type" "arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg") (eq_attr "neon_type" "none"))) "cortex_a7_ex1") diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-a8.md b/gcc-4_8-branch/gcc/config/arm/cortex-a8.md index 8d3e98734ce..1113a45ff0e 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-a8.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-a8.md @@ -85,30 +85,27 @@ ;; (source read in E2 and destination available at the end of that cycle). (define_insn_reservation "cortex_a8_alu" 2 (and (eq_attr "tune" "cortexa8") - (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm") - (eq_attr "neon_type" "none")) - (not (eq_attr "insn" "mov,mvn"))) - (eq_attr "insn" "clz"))) + (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") + (eq_attr "neon_type" "none")) + (eq_attr "type" "clz"))) "cortex_a8_default") (define_insn_reservation "cortex_a8_alu_shift" 2 (and (eq_attr "tune" "cortexa8") - (and (eq_attr "type" "simple_alu_shift,alu_shift") - (not (eq_attr "insn" "mov,mvn")))) + (eq_attr "type" "extend,arlo_shift")) "cortex_a8_default") (define_insn_reservation "cortex_a8_alu_shift_reg" 2 (and (eq_attr "tune" "cortexa8") - (and (eq_attr "type" "alu_shift_reg") - (not (eq_attr "insn" "mov,mvn")))) + (eq_attr "type" "arlo_shift_reg")) "cortex_a8_default") ;; Move instructions. (define_insn_reservation "cortex_a8_mov" 1 (and (eq_attr "tune" "cortexa8") - (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg") - (eq_attr "insn" "mov,mvn"))) + (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\ + mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) "cortex_a8_default") ;; Exceptions to the default latencies for data processing instructions. diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-a9.md b/gcc-4_8-branch/gcc/config/arm/cortex-a9.md index 05c114dc366..11dc0b32c38 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-a9.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-a9.md @@ -80,18 +80,17 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") ;; which can go down E2 without any problem. (define_insn_reservation "cortex_a9_dp" 2 (and (eq_attr "tune" "cortexa9") - (ior (and (eq_attr "type" "alu_reg,simple_alu_imm") - (eq_attr "neon_type" "none")) - (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") - (eq_attr "insn" "mov")) - (eq_attr "neon_type" "none")))) + (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg,\ + mov_shift_reg,mov_shift") + (eq_attr "neon_type" "none"))) "cortex_a9_p0_default|cortex_a9_p1_default") ;; An instruction using the shifter will go down E1. (define_insn_reservation "cortex_a9_dp_shift" 3 (and (eq_attr "tune" "cortexa9") - (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") - (not (eq_attr "insn" "mov")))) + (eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\ + mvn_shift,mvn_shift_reg")) "cortex_a9_p0_shift | cortex_a9_p1_shift") ;; Loads have a latency of 4 cycles. diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-m4.md b/gcc-4_8-branch/gcc/config/arm/cortex-m4.md index fc16d5988f2..5b7ce50df94 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-m4.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-m4.md @@ -31,8 +31,10 @@ ;; ALU and multiply is one cycle. (define_insn_reservation "cortex_m4_alu" 1 (and (eq_attr "tune" "cortexm4") - (ior (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,\ - alu_shift,alu_shift_reg") + (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\ + arlo_shift,arlo_shift_reg,\ + mov_imm,mov_reg,mov_shift,mov_shift_reg,\ + mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg") (ior (eq_attr "mul32" "yes") (eq_attr "mul64" "yes")))) "cortex_m4_ex") diff --git a/gcc-4_8-branch/gcc/config/arm/cortex-r4.md b/gcc-4_8-branch/gcc/config/arm/cortex-r4.md index 6d37079f2b3..597774dbd89 100644 --- a/gcc-4_8-branch/gcc/config/arm/cortex-r4.md +++ b/gcc-4_8-branch/gcc/config/arm/cortex-r4.md @@ -78,24 +78,22 @@ ;; for the purposes of the dual-issue constraints above. (define_insn_reservation "cortex_r4_alu" 2 (and (eq_attr "tune_cortexr4" "yes") - (and (eq_attr "type" "alu_reg,simple_alu_imm") - (not (eq_attr "insn" "mov")))) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,mvn_imm,mvn_reg")) "cortex_r4_alu") (define_insn_reservation "cortex_r4_mov" 2 (and (eq_attr "tune_cortexr4" "yes") - (and (eq_attr "type" "alu_reg,simple_alu_imm") - (eq_attr "insn" "mov"))) + (eq_attr "type" "mov_imm,mov_reg")) "cortex_r4_mov") (define_insn_reservation "cortex_r4_alu_shift" 2 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "simple_alu_shift,alu_shift")) + (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) "cortex_r4_alu") (define_insn_reservation "cortex_r4_alu_shift_reg" 2 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "alu_shift_reg")) + (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) "cortex_r4_alu_shift_reg") ;; An ALU instruction followed by an ALU instruction with no early dep. diff --git a/gcc-4_8-branch/gcc/config/arm/fa526.md b/gcc-4_8-branch/gcc/config/arm/fa526.md index efc6a1db959..9ec92d60dc5 100644 --- a/gcc-4_8-branch/gcc/config/arm/fa526.md +++ b/gcc-4_8-branch/gcc/config/arm/fa526.md @@ -62,12 +62,15 @@ ;; ALU operations (define_insn_reservation "526_alu_op" 1 (and (eq_attr "tune" "fa526") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "fa526_core") (define_insn_reservation "526_alu_shift_op" 2 (and (eq_attr "tune" "fa526") - (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg")) "fa526_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/fa606te.md b/gcc-4_8-branch/gcc/config/arm/fa606te.md index dec26c5c3ac..e61242886d7 100644 --- a/gcc-4_8-branch/gcc/config/arm/fa606te.md +++ b/gcc-4_8-branch/gcc/config/arm/fa606te.md @@ -62,7 +62,10 @@ ;; ALU operations (define_insn_reservation "606te_alu_op" 1 (and (eq_attr "tune" "fa606te") - (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg, + extend,arlo_shift,arlo_shift_reg,\ + mov_imm,mov_reg,mov_shift,mov_shift_reg,\ + mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) "fa606te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/fa626te.md b/gcc-4_8-branch/gcc/config/arm/fa626te.md index 818ad607b47..04d2a5cf33f 100644 --- a/gcc-4_8-branch/gcc/config/arm/fa626te.md +++ b/gcc-4_8-branch/gcc/config/arm/fa626te.md @@ -68,12 +68,15 @@ ;; ALU operations (define_insn_reservation "626te_alu_op" 1 (and (eq_attr "tune" "fa626,fa626te") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "fa626te_core") (define_insn_reservation "626te_alu_shift_op" 2 (and (eq_attr "tune" "fa626,fa626te") - (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg")) "fa626te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/fa726te.md b/gcc-4_8-branch/gcc/config/arm/fa726te.md index 8790b035aa5..342b9bf5d33 100644 --- a/gcc-4_8-branch/gcc/config/arm/fa726te.md +++ b/gcc-4_8-branch/gcc/config/arm/fa726te.md @@ -78,15 +78,15 @@ ;; Move instructions. (define_insn_reservation "726te_shift_op" 1 (and (eq_attr "tune" "fa726te") - (eq_attr "insn" "mov,mvn")) + (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\ + mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") ;; ALU operations with no shifted operand will finished in 1 cycle ;; Other ALU instructions 2 cycles. (define_insn_reservation "726te_alu_op" 1 (and (eq_attr "tune" "fa726te") - (and (eq_attr "type" "alu_reg,simple_alu_imm") - (not (eq_attr "insn" "mov,mvn")))) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") ;; ALU operations with a shift-by-register operand. @@ -95,14 +95,12 @@ ;; it takes 3 cycles. (define_insn_reservation "726te_alu_shift_op" 3 (and (eq_attr "tune" "fa726te") - (and (eq_attr "type" "simple_alu_shift,alu_shift") - (not (eq_attr "insn" "mov,mvn")))) + (eq_attr "type" "extend,arlo_shift")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") (define_insn_reservation "726te_alu_shift_reg_op" 3 (and (eq_attr "tune" "fa726te") - (and (eq_attr "type" "alu_shift_reg") - (not (eq_attr "insn" "mov,mvn")))) + (eq_attr "type" "arlo_shift_reg")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; Multiplication Instructions diff --git a/gcc-4_8-branch/gcc/config/arm/fmp626.md b/gcc-4_8-branch/gcc/config/arm/fmp626.md index f3b7dadcba2..944645b9ead 100644 --- a/gcc-4_8-branch/gcc/config/arm/fmp626.md +++ b/gcc-4_8-branch/gcc/config/arm/fmp626.md @@ -63,12 +63,15 @@ ;; ALU operations (define_insn_reservation "mp626_alu_op" 1 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "alu_reg,simple_alu_imm")) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ + mov_imm,mov_reg,mvn_imm,mvn_reg")) "fmp626_core") (define_insn_reservation "mp626_alu_shift_op" 2 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) + (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ + mov_shift,mov_shift_reg,\ + mvn_shift,mvn_shift_reg")) "fmp626_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc-4_8-branch/gcc/config/arm/marvell-pj4.md b/gcc-4_8-branch/gcc/config/arm/marvell-pj4.md index 4004fa59409..0e2c443721e 100644 --- a/gcc-4_8-branch/gcc/config/arm/marvell-pj4.md +++ b/gcc-4_8-branch/gcc/config/arm/marvell-pj4.md @@ -41,54 +41,54 @@ (define_insn_reservation "pj4_alu_e1" 1 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "simple_alu_imm,alu_reg") - (not (eq_attr "conds" "set")) - (eq_attr "insn" "mov,mvn")) + (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg") + (not (eq_attr "conds" "set"))) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_alu_e1_conds" 4 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "simple_alu_imm,alu_reg") - (eq_attr "conds" "set") - (eq_attr "insn" "mov,mvn")) + (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg") + (eq_attr "conds" "set")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_alu" 1 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "simple_alu_imm,alu_reg") - (not (eq_attr "conds" "set")) - (not (eq_attr "insn" "mov,mvn"))) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") + (not (eq_attr "conds" "set"))) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_alu_conds" 4 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "simple_alu_imm,alu_reg") - (eq_attr "conds" "set") - (not (eq_attr "insn" "mov,mvn"))) + (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") + (eq_attr "conds" "set")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_shift" 1 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift") + (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ + mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg") (not (eq_attr "conds" "set")) (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_shift_conds" 4 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift") + (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ + mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg") (eq_attr "conds" "set") (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_alu_shift" 1 (and (eq_attr "tune" "marvell_pj4") (not (eq_attr "conds" "set")) - (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")) + (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ + mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_alu_shift_conds" 4 (and (eq_attr "tune" "marvell_pj4") (eq_attr "conds" "set") - (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")) + (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ + mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)") (define_bypass 2 "pj4_alu_shift,pj4_shift" diff --git a/gcc-4_8-branch/gcc/config/arm/neon.md b/gcc-4_8-branch/gcc/config/arm/neon.md index 0e0cde2d85e..8f7f87b4a90 100644 --- a/gcc-4_8-branch/gcc/config/arm/neon.md +++ b/gcc-4_8-branch/gcc/config/arm/neon.md @@ -61,8 +61,7 @@ } } [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*") - (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2") - (set_attr "insn" "*,*,*,*,*,*,mov,*,*") + (set_attr "type" "*,f_stored,*,f_loadd,*,*,mov_reg,load2,store2") (set_attr "length" "4,4,4,4,4,4,8,8,8") (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") @@ -107,8 +106,7 @@ } [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\ neon_mrrc,neon_mcr_2_mcrr,*,*,*") - (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4") - (set_attr "insn" "*,*,*,*,*,*,mov,*,*") + (set_attr "type" "*,*,*,*,*,*,mov_reg,load4,store4") (set_attr "length" "4,8,4,8,8,8,16,8,16") (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") diff --git a/gcc-4_8-branch/gcc/config/arm/predicates.md b/gcc-4_8-branch/gcc/config/arm/predicates.md index bc5cc831d5d..de71c6dc9c3 100644 --- a/gcc-4_8-branch/gcc/config/arm/predicates.md +++ b/gcc-4_8-branch/gcc/config/arm/predicates.md @@ -246,6 +246,10 @@ (and (match_code "plus,minus,ior,xor,and") (match_test "mode == GET_MODE (op)"))) +(define_special_predicate "shiftable_operator_strict_it" + (and (match_code "plus,and") + (match_test "mode == GET_MODE (op)"))) + ;; True for logical binary operators. (define_special_predicate "logical_binary_operator" (and (match_code "ior,xor,and") diff --git a/gcc-4_8-branch/gcc/config/arm/thumb2.md b/gcc-4_8-branch/gcc/config/arm/thumb2.md index cef68d43d18..edac9b66bd6 100644 --- a/gcc-4_8-branch/gcc/config/arm/thumb2.md +++ b/gcc-4_8-branch/gcc/config/arm/thumb2.md @@ -60,96 +60,91 @@ "TARGET_THUMB2" "bic%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "shift" "2") - (set_attr "type" "alu_shift")] + (set_attr "type" "arlo_shift")] ) +;; We use the '0' constraint for operand 1 because reload should +;; be smart enough to generate an appropriate move for the r/r/r case. (define_insn_and_split "*thumb2_smaxsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") + (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") + (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB2" - "#" - ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2 - ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1 - ; cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2 - "TARGET_THUMB2" + "TARGET_THUMB2" + "#" + ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2 + "TARGET_THUMB2 && reload_completed" [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0)) - (match_dup 1) - (match_dup 2)))] + (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) + (match_dup 2)))] "" [(set_attr "conds" "clob") - (set_attr "length" "10,10,14")] + (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "length" "6,6,10")] ) (define_insn_and_split "*thumb2_sminsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") + (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") + (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "#" - ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2 - ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1 - ; cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2" - "TARGET_THUMB2" + ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2 + "TARGET_THUMB2 && reload_completed" [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0)) - (match_dup 1) - (match_dup 2)))] + (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) + (match_dup 2)))] "" [(set_attr "conds" "clob") - (set_attr "length" "10,10,14")] + (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "length" "6,6,10")] ) (define_insn_and_split "*thumb32_umaxsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) - (clobber (reg:CC CC_REGNUM))] + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") + (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") + (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "#" - ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2 - ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1 - ; cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2" - "TARGET_THUMB2" + ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2 + "TARGET_THUMB2 && reload_completed" [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0)) - (match_dup 1) - (match_dup 2)))] + (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) + (match_dup 2)))] "" [(set_attr "conds" "clob") - (set_attr "length" "10,10,14")] + (set_attr "length" "6,6,10") + (set_attr "enabled_for_depr_it" "yes,yes,no")] ) (define_insn_and_split "*thumb2_uminsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") + (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") + (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "#" - ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2 - ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1 - ; cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2" - "TARGET_THUMB2" + ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2 + "TARGET_THUMB2 && reload_completed" [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) - (match_dup 1) - (match_dup 2)))] + (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) + (match_dup 2)))] "" [(set_attr "conds" "clob") - (set_attr "length" "10,10,14")] + (set_attr "length" "6,6,10") + (set_attr "enabled_for_depr_it" "yes,yes,no")] ) ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands. @@ -178,17 +173,17 @@ ) (define_insn_and_split "*thumb2_abssi2" - [(set (match_operand:SI 0 "s_register_operand" "=r,&r") - (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) + [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r") + (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "#" - ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0 ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31 + ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0 + ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0 "&& reload_completed" [(const_int 0)] { - /* if (which_alternative == 0) */ if (REGNO(operands[0]) == REGNO(operands[1])) { rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); @@ -225,25 +220,27 @@ } DONE; } - [(set_attr "conds" "clob,*") + [(set_attr "conds" "*,clob,clob") (set_attr "shift" "1") - (set_attr "predicable" "no, yes") + (set_attr "predicable" "yes,no,no") + (set_attr "predicable_short_it" "no") + (set_attr "enabled_for_depr_it" "yes,yes,no") (set_attr "ce_count" "2") - (set_attr "length" "10,8")] + (set_attr "length" "8,6,10")] ) (define_insn_and_split "*thumb2_neg_abssi2" - [(set (match_operand:SI 0 "s_register_operand" "=r,&r") - (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) + [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r") + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "#" + ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31 + ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0 - ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" "&& reload_completed" [(const_int 0)] { - /* if (which_alternative == 0) */ if (REGNO(operands[0]) == REGNO(operands[1])) { rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); @@ -280,11 +277,13 @@ } DONE; } - [(set_attr "conds" "clob,*") + [(set_attr "conds" "*,clob,clob") (set_attr "shift" "1") - (set_attr "predicable" "no, yes") + (set_attr "predicable" "yes,no,no") + (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "predicable_short_it" "no") (set_attr "ce_count" "2") - (set_attr "length" "10,8")] + (set_attr "length" "8,6,10")] ) ;; We have two alternatives here for memory loads (and similarly for stores) @@ -309,7 +308,7 @@ ldr%?\\t%0, %1 str%?\\t%1, %0 str%?\\t%1, %0" - [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,*,load1,load1,store1,store1") + [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1") (set_attr "length" "2,4,2,4,4,4,4,4,4") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no") @@ -362,11 +361,11 @@ "cmn%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "type" "alu_shift")] + (set_attr "type" "arlo_shift")] ) (define_insn_and_split "*thumb2_mov_scc" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "=l,r") (match_operator:SI 1 "arm_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)]))] "TARGET_THUMB2" @@ -378,14 +377,15 @@ (const_int 0)))] "" [(set_attr "conds" "use") - (set_attr "length" "10")] + (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "length" "8,10")] ) (define_insn_and_split "*thumb2_mov_negscc" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operator:SI 1 "arm_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] - "TARGET_THUMB2" + "TARGET_THUMB2 && !arm_restrict_it" "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" "TARGET_THUMB2" [(set (match_dup 0) @@ -399,11 +399,39 @@ (set_attr "length" "10")] ) +(define_insn_and_split "*thumb2_mov_negscc_strict_it" + [(set (match_operand:SI 0 "low_register_operand" "=l") + (neg:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] + "TARGET_THUMB2 && arm_restrict_it" + "#" ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\" + "&& reload_completed" + [(set (match_dup 0) + (match_dup 3)) + (cond_exec (match_dup 4) + (set (match_dup 0) + (const_int 0)))] + { + operands[3] = GEN_INT (~0); + enum machine_mode mode = GET_MODE (operands[2]); + enum rtx_code rc = GET_CODE (operands[1]); + + if (mode == CCFPmode || mode == CCFPEmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); + operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); + + } + [(set_attr "conds" "use") + (set_attr "length" "8")] +) + (define_insn_and_split "*thumb2_mov_notscc" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_operator:SI 1 "arm_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] - "TARGET_THUMB2" + "TARGET_THUMB2 && !arm_restrict_it" "#" ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" "TARGET_THUMB2" [(set (match_dup 0) @@ -418,13 +446,35 @@ (set_attr "length" "10")] ) +(define_insn_and_split "*thumb2_mov_notscc_strict_it" + [(set (match_operand:SI 0 "low_register_operand" "=l") + (not:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] + "TARGET_THUMB2 && arm_restrict_it" + "#" ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1" + "&& reload_completed" + [(set (match_dup 0) + (match_dup 3)) + (cond_exec (match_dup 4) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (const_int 1))))] + { + operands[3] = GEN_INT (~0); + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]), + VOIDmode, operands[2], const0_rtx); + } + [(set_attr "conds" "use") + (set_attr "length" "8")] +) + (define_insn_and_split "*thumb2_movsicc_insn" - [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,l") + [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r") (if_then_else:SI (match_operator 3 "arm_comparison_operator" [(match_operand 4 "cc_register" "") (const_int 0)]) - (match_operand:SI 1 "arm_not_operand" "0 ,Py,0 ,0,rI,K,rI,rI,K ,K,r,lPy") - (match_operand:SI 2 "arm_not_operand" "Py,0 ,rI,K,0 ,0,rI,K ,rI,K,r,lPy")))] + (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,rI,rI,K ,K,r") + (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,K ,rI,K,r")))] "TARGET_THUMB2" "@ it\\t%D3\;mov%D3\\t%0, %2 @@ -437,14 +487,12 @@ # # # - # #" ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2 ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 ; alt 8: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2 ; alt 10: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2 - ; alt 11: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2" "&& reload_completed" [(const_int 0)] { @@ -475,8 +523,8 @@ operands[2]))); DONE; } - [(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6,6") - (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes,yes") + [(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6") + (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes") (set_attr "conds" "use")] ) @@ -558,7 +606,7 @@ (ior:SI (match_operator:SI 1 "arm_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)]) (match_operand:SI 3 "s_register_operand" "0,?r")))] - "TARGET_THUMB2" + "TARGET_THUMB2 && !arm_restrict_it" "@ it\\t%d1\;orr%d1\\t%0, %3, #1 #" @@ -583,6 +631,19 @@ (set_attr "length" "6,10")] ) +(define_insn "*thumb2_ior_scc_strict_it" + [(set (match_operand:SI 0 "s_register_operand" "=l,l") + (ior:SI (match_operator:SI 2 "arm_comparison_operator" + [(match_operand 3 "cc_register" "") (const_int 0)]) + (match_operand:SI 1 "s_register_operand" "0,?l")))] + "TARGET_THUMB2 && arm_restrict_it" + "@ + it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1 + mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1" + [(set_attr "conds" "use") + (set_attr "length" "8")] +) + (define_insn "*thumb2_cond_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (if_then_else:SI (match_operator 3 "equality_operator" @@ -610,13 +671,20 @@ output_asm_insn (\"it\\t%D4\", operands); break; case 2: - output_asm_insn (\"ite\\t%D4\", operands); + if (arm_restrict_it) + output_asm_insn (\"it\\t%D4\", operands); + else + output_asm_insn (\"ite\\t%D4\", operands); break; default: abort(); } if (which_alternative != 0) - output_asm_insn (\"mov%D4\\t%0, %1\", operands); + { + output_asm_insn (\"mov%D4\\t%0, %1\", operands); + if (arm_restrict_it && which_alternative == 2) + output_asm_insn (\"it\\t%d4\", operands); + } if (which_alternative != 1) output_asm_insn (\"mov%d4\\t%0, %2\", operands); return \"\"; @@ -633,7 +701,7 @@ (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB2" + "TARGET_THUMB2 && !arm_restrict_it" "* if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) return \"%i5\\t%0, %1, %2, lsr #31\"; @@ -662,9 +730,78 @@ (set_attr "length" "14")] ) +(define_insn_and_split "*thumb2_cond_arith_strict_it" + [(set (match_operand:SI 0 "s_register_operand" "=l") + (match_operator:SI 5 "shiftable_operator_strict_it" + [(match_operator:SI 4 "arm_comparison_operator" + [(match_operand:SI 2 "s_register_operand" "r") + (match_operand:SI 3 "arm_rhs_operand" "rI")]) + (match_operand:SI 1 "s_register_operand" "0")])) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2 && arm_restrict_it" + "#" + "&& reload_completed" + [(const_int 0)] + { + if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) + { + /* %i5 %0, %1, %2, lsr #31 */ + rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31)); + rtx op = NULL_RTX; + + switch (GET_CODE (operands[5])) + { + case AND: + op = gen_rtx_AND (SImode, shifted_op, operands[1]); + break; + case PLUS: + op = gen_rtx_PLUS (SImode, shifted_op, operands[1]); + break; + default: gcc_unreachable (); + } + emit_insn (gen_rtx_SET (VOIDmode, operands[0], op)); + DONE; + } + + /* "cmp %2, %3" */ + emit_insn (gen_rtx_SET (VOIDmode, + gen_rtx_REG (CCmode, CC_REGNUM), + gen_rtx_COMPARE (CCmode, operands[2], operands[3]))); + + if (GET_CODE (operands[5]) == AND) + { + /* %i5 %0, %1, #1 + it%D4 + mov%D4 %0, #0 */ + enum rtx_code rc = reverse_condition (GET_CODE (operands[4])); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_AND (SImode, operands[1], GEN_INT (1)))); + emit_insn (gen_rtx_COND_EXEC (VOIDmode, + gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx), + gen_rtx_SET (VOIDmode, operands[0], const0_rtx))); + DONE; + } + else + { + /* it\\t%d4 + %i5%d4\\t%0, %1, #1 */ + emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]), + VOIDmode, + gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx), + gen_rtx_SET(VOIDmode, operands[0], + gen_rtx_PLUS (SImode, + operands[1], + GEN_INT (1))))); + DONE; + } + FAIL; + } + [(set_attr "conds" "clob") + (set_attr "length" "12")] +) + (define_insn "*thumb2_cond_sub" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") + [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") + (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts") (match_operator:SI 4 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) @@ -674,8 +811,16 @@ output_asm_insn (\"cmp\\t%2, %3\", operands); if (which_alternative != 0) { - output_asm_insn (\"ite\\t%D4\", operands); - output_asm_insn (\"mov%D4\\t%0, %1\", operands); + if (arm_restrict_it) + { + output_asm_insn (\"mov\\t%0, %1\", operands); + output_asm_insn (\"it\\t%d4\", operands); + } + else + { + output_asm_insn (\"ite\\t%D4\", operands); + output_asm_insn (\"mov%D4\\t%0, %1\", operands); + } } else output_asm_insn (\"it\\t%d4\", operands); @@ -754,13 +899,13 @@ ) (define_insn "*thumb2_movcond" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts") (if_then_else:SI (match_operator 5 "arm_comparison_operator" [(match_operand:SI 3 "s_register_operand" "r,r,r") (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")]) - (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) + (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI") + (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" "* @@ -815,12 +960,18 @@ output_asm_insn (\"it\\t%d5\", operands); break; case 2: - output_asm_insn (\"ite\\t%d5\", operands); + if (arm_restrict_it) + { + output_asm_insn (\"mov\\t%0, %1\", operands); + output_asm_insn (\"it\\t%D5\", operands); + } + else + output_asm_insn (\"ite\\t%d5\", operands); break; default: abort(); } - if (which_alternative != 0) + if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2)) output_asm_insn (\"mov%d5\\t%0, %1\", operands); if (which_alternative != 1) output_asm_insn (\"mov%D5\\t%0, %2\", operands); @@ -841,8 +992,9 @@ "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" - [(set_attr "type" "simple_alu_shift,load_byte") + [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -854,8 +1006,9 @@ "@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" - [(set_attr "type" "simple_alu_shift,load_byte") + [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -867,8 +1020,9 @@ "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr "type" "simple_alu_shift,load_byte") + [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -959,8 +1113,8 @@ (set_attr "shift" "1") (set_attr "length" "2") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] + (const_string "arlo_shift") + (const_string "arlo_shift_reg")))] ) (define_insn "*thumb2_mov_shortim" @@ -1082,7 +1236,7 @@ " [(set_attr "conds" "set") (set_attr "length" "2,2,4,4") - (set_attr "type" "simple_alu_imm,*,simple_alu_imm,*")] + (set_attr "type" "arlo_imm,*,arlo_imm,*")] ) (define_insn "*thumb2_mulsi_short" @@ -1193,7 +1347,8 @@ (match_operand:SI 1 "s_register_operand" "r")))] "TARGET_THUMB2" "orn%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")] + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")] ) (define_insn "*orsi_not_shiftsi_si" @@ -1205,8 +1360,9 @@ "TARGET_THUMB2" "orn%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "shift" "2") - (set_attr "type" "alu_shift")] + (set_attr "type" "arlo_shift")] ) (define_peephole2 diff --git a/gcc-4_8-branch/gcc/config/arm/vfp.md b/gcc-4_8-branch/gcc/config/arm/vfp.md index 9ac887e9b19..ef8777a900b 100644 --- a/gcc-4_8-branch/gcc/config/arm/vfp.md +++ b/gcc-4_8-branch/gcc/config/arm/vfp.md @@ -53,9 +53,8 @@ } " [(set_attr "predicable" "yes") - (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") - (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*") (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] ) @@ -102,10 +101,9 @@ " [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "type" "*,*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4") (set_attr "neon_type" "*,*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") - (set_attr "insn" "mov,mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*") (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*") (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] ) @@ -357,9 +355,8 @@ " [(set_attr "predicable" "yes") (set_attr "type" - "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") + "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") - (set_attr "insn" "*,*,*,*,*,*,*,*,mov") (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] ) @@ -396,9 +393,8 @@ [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" - "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") + "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") - (set_attr "insn" "*,*,*,*,*,*,*,*,mov") (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] ) -- 2.11.4.GIT