From 8fc56618a84446beccd45b80381cdfe0e94050df Mon Sep 17 00:00:00 2001 From: uros Date: Tue, 9 Jan 2007 12:46:17 +0000 Subject: [PATCH] * config/i386/i386.md (*sinxf2): Rename to *sinxf2_i387. (*cosxf2): Rename to cosxf2_i387. (*sindf2, *sinsf2): Extend operand 1 to XFmode. Macroize patterns using X87MODEF12 mode macro. Rename patterns to *sin_extendxf2_i387. Use SSE_FLOAT_MODE_P to disable patterns for SSE math. (*cosdf2, *cossf2): Ditto. (sincosdf3, sincossf3): Ditto. Rewrite corresponding splitters to match extended input operands. (sincos3): New expander. (*sinextendsfdf2, *cosextendsfdf2, *sincosextendsfdf3): Remove insn patterns and corresponding splitters. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@120620 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 18 ++++ gcc/config/i386/i386.md | 234 +++++++++++++++--------------------------------- 2 files changed, 88 insertions(+), 164 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bd58d3a0429..642ae649d98 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2007-01-09 Uros Bizjak + + * config/i386/i386.md (*sinxf2): Rename to *sinxf2_i387. + (*cosxf2): Rename to cosxf2_i387. + + (*sindf2, *sinsf2): Extend operand 1 to XFmode. Macroize patterns + using X87MODEF12 mode macro. Rename patterns to + *sin_extendxf2_i387. Use SSE_FLOAT_MODE_P to disable patterns + for SSE math. + (*cosdf2, *cossf2): Ditto. + (sincosdf3, sincossf3): Ditto. Rewrite corresponding splitters + to match extended input operands. + + (sincos3): New expander. + + (*sinextendsfdf2, *cosextendsfdf2, *sincosextendsfdf3): Remove + insn patterns and corresponding splitters. + 2007-01-09 Kaz Kojima * config/sh/t-linux (TARGET_LIBGCC2_CFLAGS): Delete. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 7066c6355ba..fa8ac3b96d3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15726,39 +15726,7 @@ DONE; }) -(define_insn "*sindf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsin" - [(set_attr "type" "fpspc") - (set_attr "mode" "DF")]) - -(define_insn "*sinsf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsin" - [(set_attr "type" "fpspc") - (set_attr "mode" "SF")]) - -(define_insn "*sinextendsfdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(float_extend:DF - (match_operand:SF 1 "register_operand" "0"))] - UNSPEC_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsin" - [(set_attr "type" "fpspc") - (set_attr "mode" "DF")]) - -(define_insn "*sinxf2" +(define_insn "*sinxf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))] "TARGET_USE_FANCY_MATH_387 @@ -15767,173 +15735,91 @@ [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) -(define_insn "*cosdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))] +(define_insn "*sin_extendxf2_i387" + [(set (match_operand:XF 0 "register_operand" "=f") + (unspec:XF [(float_extend:XF + (match_operand:X87MODEF12 1 "register_operand" "0"))] + UNSPEC_SIN))] "TARGET_USE_FANCY_MATH_387 - && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) + && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" - "fcos" - [(set_attr "type" "fpspc") - (set_attr "mode" "DF")]) - -(define_insn "*cossf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))] - "TARGET_USE_FANCY_MATH_387 - && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fcos" + "fsin" [(set_attr "type" "fpspc") - (set_attr "mode" "SF")]) + (set_attr "mode" "XF")]) -(define_insn "*cosextendsfdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(float_extend:DF - (match_operand:SF 1 "register_operand" "0"))] - UNSPEC_COS))] +(define_insn "*cosxf2_i387" + [(set (match_operand:XF 0 "register_operand" "=f") + (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))] "TARGET_USE_FANCY_MATH_387 - && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" "fcos" [(set_attr "type" "fpspc") - (set_attr "mode" "DF")]) + (set_attr "mode" "XF")]) -(define_insn "*cosxf2" +(define_insn "*cos_extendxf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))] + (unspec:XF [(float_extend:XF + (match_operand:X87MODEF12 1 "register_operand" "0"))] + UNSPEC_COS))] "TARGET_USE_FANCY_MATH_387 + && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" "fcos" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) -;; With sincos pattern defined, sin and cos builtin function will be +;; When sincos pattern is defined, sin and cos builtin functions will be ;; expanded to sincos pattern with one of its outputs left unused. -;; Cse pass will detected, if two sincos patterns can be combined, +;; CSE pass will figure out if two sincos patterns can be combined, ;; otherwise sincos pattern will be split back to sin or cos pattern, ;; depending on the unused output. -(define_insn "sincosdf3" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(match_operand:DF 2 "register_operand" "0")] - UNSPEC_SINCOS_COS)) - (set (match_operand:DF 1 "register_operand" "=u") - (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsincos" - [(set_attr "type" "fpspc") - (set_attr "mode" "DF")]) - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (unspec:DF [(match_operand:DF 2 "register_operand" "")] - UNSPEC_SINCOS_COS)) - (set (match_operand:DF 1 "register_operand" "") - (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) - && !reload_completed && !reload_in_progress" - [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))] - "") - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (unspec:DF [(match_operand:DF 2 "register_operand" "")] - UNSPEC_SINCOS_COS)) - (set (match_operand:DF 1 "register_operand" "") - (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) - && !reload_completed && !reload_in_progress" - [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))] - "") - -(define_insn "sincossf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (unspec:SF [(match_operand:SF 2 "register_operand" "0")] - UNSPEC_SINCOS_COS)) - (set (match_operand:SF 1 "register_operand" "=u") - (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "TARGET_USE_FANCY_MATH_387 - && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fsincos" - [(set_attr "type" "fpspc") - (set_attr "mode" "SF")]) - -(define_split - [(set (match_operand:SF 0 "register_operand" "") - (unspec:SF [(match_operand:SF 2 "register_operand" "")] - UNSPEC_SINCOS_COS)) - (set (match_operand:SF 1 "register_operand" "") - (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) - && !reload_completed && !reload_in_progress" - [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))] - "") - -(define_split - [(set (match_operand:SF 0 "register_operand" "") - (unspec:SF [(match_operand:SF 2 "register_operand" "")] - UNSPEC_SINCOS_COS)) - (set (match_operand:SF 1 "register_operand" "") - (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))] - "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) - && !reload_completed && !reload_in_progress" - [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))] - "") - -(define_insn "*sincosextendsfdf3" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(float_extend:DF - (match_operand:SF 2 "register_operand" "0"))] +(define_insn "sincosxf3" + [(set (match_operand:XF 0 "register_operand" "=f") + (unspec:XF [(match_operand:XF 2 "register_operand" "0")] UNSPEC_SINCOS_COS)) - (set (match_operand:DF 1 "register_operand" "=u") - (unspec:DF [(float_extend:DF - (match_dup 2))] UNSPEC_SINCOS_SIN))] + (set (match_operand:XF 1 "register_operand" "=u") + (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "TARGET_USE_FANCY_MATH_387 - && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" "fsincos" [(set_attr "type" "fpspc") - (set_attr "mode" "DF")]) + (set_attr "mode" "XF")]) (define_split - [(set (match_operand:DF 0 "register_operand" "") - (unspec:DF [(float_extend:DF - (match_operand:SF 2 "register_operand" ""))] + [(set (match_operand:XF 0 "register_operand" "") + (unspec:XF [(match_operand:XF 2 "register_operand" "")] UNSPEC_SINCOS_COS)) - (set (match_operand:DF 1 "register_operand" "") - (unspec:DF [(float_extend:DF - (match_dup 2))] UNSPEC_SINCOS_SIN))] + (set (match_operand:XF 1 "register_operand" "") + (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) && !reload_completed && !reload_in_progress" - [(set (match_dup 1) (unspec:DF [(float_extend:DF - (match_dup 2))] UNSPEC_SIN))] + [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))] "") (define_split - [(set (match_operand:DF 0 "register_operand" "") - (unspec:DF [(float_extend:DF - (match_operand:SF 2 "register_operand" ""))] + [(set (match_operand:XF 0 "register_operand" "") + (unspec:XF [(match_operand:XF 2 "register_operand" "")] UNSPEC_SINCOS_COS)) - (set (match_operand:DF 1 "register_operand" "") - (unspec:DF [(float_extend:DF - (match_dup 2))] UNSPEC_SINCOS_SIN))] + (set (match_operand:XF 1 "register_operand" "") + (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) && !reload_completed && !reload_in_progress" - [(set (match_dup 0) (unspec:DF [(float_extend:DF - (match_dup 2))] UNSPEC_COS))] + [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))] "") -(define_insn "sincosxf3" +(define_insn "sincos_extendxf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(match_operand:XF 2 "register_operand" "0")] + (unspec:XF [(float_extend:XF + (match_operand:X87MODEF12 2 "register_operand" "0"))] UNSPEC_SINCOS_COS)) (set (match_operand:XF 1 "register_operand" "=u") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] + (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "TARGET_USE_FANCY_MATH_387 + && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" "fsincos" [(set_attr "type" "fpspc") @@ -15941,26 +15827,46 @@ (define_split [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "")] + (unspec:XF [(float_extend:XF + (match_operand:X87MODEF12 2 "register_operand" ""))] UNSPEC_SINCOS_COS)) (set (match_operand:XF 1 "register_operand" "") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] + (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) && !reload_completed && !reload_in_progress" - [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))] + [(set (match_dup 1) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))] "") (define_split [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "")] + (unspec:XF [(float_extend:XF + (match_operand:X87MODEF12 2 "register_operand" ""))] UNSPEC_SINCOS_COS)) (set (match_operand:XF 1 "register_operand" "") - (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] + (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) && !reload_completed && !reload_in_progress" - [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))] + [(set (match_dup 0) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))] "") +(define_expand "sincos3" + [(use (match_operand:X87MODEF12 0 "register_operand" "")) + (use (match_operand:X87MODEF12 1 "register_operand" "")) + (use (match_operand:X87MODEF12 2 "register_operand" ""))] + "TARGET_USE_FANCY_MATH_387 + && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + || TARGET_MIX_SSE_I387) + && flag_unsafe_math_optimizations" +{ + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); + + emit_insn (gen_sincos_extendxf3_i387 (op0, op1, operands[2])); + emit_insn (gen_truncxf2_i387_noop_unspec (operands[0], op0)); + emit_insn (gen_truncxf2_i387_noop_unspec (operands[1], op1)); + DONE; +}) + (define_insn "*tandf3_1" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(match_operand:DF 2 "register_operand" "0")] -- 2.11.4.GIT