From 7c81829f812550865859a91f9bca33249f1cf782 Mon Sep 17 00:00:00 2001 From: ktkachov Date: Wed, 2 Nov 2016 08:57:08 +0000 Subject: [PATCH] [AArch64] Add function comments to some prologue/epilogue helpers * config/aarch64/aarch64.c (aarch64_register_saved_on_entry): Add function comment. (aarch64_next_callee_save): Likewise. (aarch64_pushwb_single_reg): Likewise. (aarch64_gen_storewb_pair): Likewise. (aarch64_push_regs): Likewise. (aarch64_gen_loadwb_pair): Likewise. (aarch64_pop_regs): Likewise. (aarch64_gen_store_pair): Likewise. (aarch64_gen_load_pair): Likewise. (aarch64_save_callee_saves): Likewise. (aarch64_restore_callee_saves): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241777 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config/aarch64/aarch64.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index be6c059f26e..52215f6eebf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2016-11-02 Kyrylo Tkachov + + * config/aarch64/aarch64.c (aarch64_register_saved_on_entry): Add + function comment. + (aarch64_next_callee_save): Likewise. + (aarch64_pushwb_single_reg): Likewise. + (aarch64_gen_storewb_pair): Likewise. + (aarch64_push_regs): Likewise. + (aarch64_gen_loadwb_pair): Likewise. + (aarch64_pop_regs): Likewise. + (aarch64_gen_store_pair): Likewise. + (aarch64_gen_load_pair): Likewise. + (aarch64_save_callee_saves): Likewise. + (aarch64_restore_callee_saves): Likewise. + 2016-11-02 Richard Biener PR tree-optimization/78035 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index df74ad96949..28bdbceaa8f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2936,12 +2936,18 @@ aarch64_layout_frame (void) cfun->machine->frame.laid_out = true; } +/* Return true if the register REGNO is saved on entry to + the current function. */ + static bool aarch64_register_saved_on_entry (int regno) { return cfun->machine->frame.reg_offset[regno] >= 0; } +/* Return the next register up from REGNO up to LIMIT for the callee + to save. */ + static unsigned aarch64_next_callee_save (unsigned regno, unsigned limit) { @@ -2950,6 +2956,9 @@ aarch64_next_callee_save (unsigned regno, unsigned limit) return regno; } +/* Push the register number REGNO of mode MODE to the stack with write-back + adjusting the stack by ADJUSTMENT. */ + static void aarch64_pushwb_single_reg (machine_mode mode, unsigned regno, HOST_WIDE_INT adjustment) @@ -2966,6 +2975,10 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno, RTX_FRAME_RELATED_P (insn) = 1; } +/* Generate and return an instruction to store the pair of registers + REG and REG2 of mode MODE to location BASE with write-back adjusting + the stack location BASE by ADJUSTMENT. */ + static rtx aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, HOST_WIDE_INT adjustment) @@ -2985,6 +2998,9 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, } } +/* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the + stack pointer by ADJUSTMENT. */ + static void aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment) { @@ -3004,6 +3020,9 @@ aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment) RTX_FRAME_RELATED_P (insn) = 1; } +/* Load the pair of register REG, REG2 of mode MODE from stack location BASE, + adjusting it by ADJUSTMENT afterwards. */ + static rtx aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, HOST_WIDE_INT adjustment) @@ -3021,6 +3040,10 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, } } +/* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it + afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes + into CFI_OPS. */ + static void aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment, rtx *cfi_ops) @@ -3045,6 +3068,9 @@ aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment, } } +/* Generate and return a store pair instruction of mode MODE to store + register REG1 to MEM1 and register REG2 to MEM2. */ + static rtx aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2, rtx reg2) @@ -3062,6 +3088,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2, } } +/* Generate and regurn a load pair isntruction of mode MODE to load register + REG1 from MEM1 and register REG2 from MEM2. */ + static rtx aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2, rtx mem2) @@ -3079,6 +3108,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2, } } +/* Emit code to save the callee-saved registers from register number START + to LIMIT to the stack at the location starting at offset START_OFFSET, + skipping any write-back candidates if SKIP_WB is true. */ static void aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, @@ -3137,6 +3169,11 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, } } +/* Emit code to restore the callee registers of mode MODE from register + number START up to and including LIMIT. Restore from the stack offset + START_OFFSET, skipping any write-back candidates if SKIP_WB is true. + Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */ + static void aarch64_restore_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, unsigned start, -- 2.11.4.GIT