From 606c99b0de737fa82d51cb0e4a612571b9c82dc8 Mon Sep 17 00:00:00 2001 From: nemet Date: Fri, 1 Aug 2008 01:18:16 +0000 Subject: [PATCH] * config.gcc (mipsisa64*-*-linux*): New configuration. Set ISA to MIPS64r2 for mipsisa64r2*. * config/mips/mips.h (GENERATE_MIPS16E): Update comment. (ISA_MIPS64R2): New macro. (TARGET_CPU_CPP_BUILTINS, MULTILIB_ISA_DEFAULT): Handle it. (ISA_HAS_64BIT_REGS, ISA_HAS_MUL3, ISA_HAS_FP_CONDMOVE, ISA_HAS_8CC, ISA_HAS_FP4, ISA_HAS_PAIRED_SINGLE, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD4_NMSUB4, ISA_HAS_CLZ_CLO, ISA_HAS_ROR, ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX, ISA_HAS_SEB_SEH, ISA_HAS_EXT_INS, ISA_HAS_MXHC1, ISA_HAS_HILO_INTERLOCKS, ISA_HAS_SYNCI, MIN_FPRS_PER_FMT): Return true for ISA_MIPS64R2. (MIPS_ISA_LEVEL_SPEC, ASM_SPEC, LINK_SPEC): Handle -mips64r2. (TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF): Move up to keep list alphabetically sorted. (TUNE_20KC, TUNE_24K, TUNE_74K, TUNE_LOONGSON_2EF): Likewise. * config/mips/mips.c (mips_cpu_info_table): Add default MIPS64r2 processor. * doc/invoke.texi (MIPS Options): Add -mips64r2. (-march=@var{arch}): Add mips64r2. testsuite/ * gcc.target/mips/ext-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@138448 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 22 ++++++++ gcc/config.gcc | 5 +- gcc/config/mips/mips.c | 2 + gcc/config/mips/mips.h | 97 +++++++++++++++++++++++------------ gcc/doc/invoke.texi | 9 +++- gcc/testsuite/ChangeLog | 4 ++ gcc/testsuite/gcc.target/mips/ext-1.c | 18 +++++++ 7 files changed, 121 insertions(+), 36 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/ext-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c8674e59dda..8d21c791d38 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2008-07-31 Adam Nemet + + * config.gcc (mipsisa64r2*-*-linux*): New configuration. Set ISA + to MIPS64r2. + * config/mips/mips.h (GENERATE_MIPS16E): Update comment. + (ISA_MIPS64R2): New macro. + (TARGET_CPU_CPP_BUILTINS, MULTILIB_ISA_DEFAULT): Handle it. + (ISA_HAS_64BIT_REGS, ISA_HAS_MUL3, ISA_HAS_FP_CONDMOVE, + ISA_HAS_8CC, ISA_HAS_FP4, ISA_HAS_PAIRED_SINGLE, + ISA_HAS_MADD_MSUB, ISA_HAS_NMADD4_NMSUB4, ISA_HAS_CLZ_CLO, + ISA_HAS_ROR, ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX, ISA_HAS_SEB_SEH, + ISA_HAS_EXT_INS, ISA_HAS_MXHC1, ISA_HAS_HILO_INTERLOCKS, + ISA_HAS_SYNCI, MIN_FPRS_PER_FMT): Return true for ISA_MIPS64R2. + (MIPS_ISA_LEVEL_SPEC, ASM_SPEC, LINK_SPEC): Handle -mips64r2. + (TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF): + Move up to keep list alphabetically sorted. + (TUNE_20KC, TUNE_24K, TUNE_74K, TUNE_LOONGSON_2EF): Likewise. + * config/mips/mips.c (mips_cpu_info_table): Add default MIPS64r2 + processor. + * doc/invoke.texi (MIPS Options): Add -mips64r2. + (-march=@var{arch}): Add mips64r2. + 2008-07-31 H.J. Lu * config/i386/darwin.h (MAIN_STACK_BOUNDARY): Define to 128. diff --git a/gcc/config.gcc b/gcc/config.gcc index bc818e6f585..a2aa4242f80 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1542,7 +1542,7 @@ mips*-*-netbsd*) # NetBSD/mips, either endian. target_cpu_default="MASK_ABICALLS" tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h" ;; -mips64*-*-linux*) +mips64*-*-linux* | mipsisa64*-*-linux*) tm_file="dbxelf.h elfos.h svr4.h linux.h ${tm_file} mips/linux.h mips/linux64.h" tmake_file="${tmake_file} mips/t-linux64" tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32" @@ -1551,6 +1551,9 @@ mips64*-*-linux*) tm_file="${tm_file} mips/st.h" tmake_file="${tmake_file} mips/t-st" ;; + mipsisa64r2*-*-linux*) + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65" + ;; esac gnu_ld=yes gas=yes diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 913acc71cf1..c4006c2f616 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -565,6 +565,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY }, { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY }, { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY }, + /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */ + { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY }, /* MIPS I processors. */ { "r3000", PROCESSOR_R3000, 1, 0 }, diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 8518a86233b..f5fc2e642ef 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -204,7 +204,7 @@ enum mips_code_readable_setting { /* Generate mips16 code */ #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) -/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */ +/* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) /* Generate mips16e register save/restore sequences. */ #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) @@ -227,8 +227,12 @@ enum mips_code_readable_setting { #define ISA_MIPS32 (mips_isa == 32) #define ISA_MIPS32R2 (mips_isa == 33) #define ISA_MIPS64 (mips_isa == 64) +#define ISA_MIPS64R2 (mips_isa == 65) /* Architecture target defines. */ +#define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) +#define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) +#define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -240,11 +244,18 @@ enum mips_code_readable_setting { #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) -#define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) -#define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) -#define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) /* Scheduling target defines. */ +#define TUNE_20KC (mips_tune == PROCESSOR_20KC) +#define TUNE_24K (mips_tune == PROCESSOR_24KC \ + || mips_tune == PROCESSOR_24KF2_1 \ + || mips_tune == PROCESSOR_24KF1_1) +#define TUNE_74K (mips_tune == PROCESSOR_74KC \ + || mips_tune == PROCESSOR_74KF2_1 \ + || mips_tune == PROCESSOR_74KF1_1 \ + || mips_tune == PROCESSOR_74KF3_2) +#define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ + || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -258,16 +269,6 @@ enum mips_code_readable_setting { #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ || mips_tune == PROCESSOR_SB1A) -#define TUNE_24K (mips_tune == PROCESSOR_24KC \ - || mips_tune == PROCESSOR_24KF2_1 \ - || mips_tune == PROCESSOR_24KF1_1) -#define TUNE_74K (mips_tune == PROCESSOR_74KC \ - || mips_tune == PROCESSOR_74KF2_1 \ - || mips_tune == PROCESSOR_74KF1_1 \ - || mips_tune == PROCESSOR_74KF3_2) -#define TUNE_20KC (mips_tune == PROCESSOR_20KC) -#define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ - || mips_tune == PROCESSOR_LOONGSON_2F) /* Whether vector modes and intrinsics for ST Microelectronics Loongson-2E/2F processors should be enabled. In o32 pairs of @@ -452,6 +453,12 @@ enum mips_code_readable_setting { builtin_define ("__mips_isa_rev=1"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ } \ + else if (ISA_MIPS64R2) \ + { \ + builtin_define ("__mips=64"); \ + builtin_define ("__mips_isa_rev=2"); \ + builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ + } \ \ switch (mips_abi) \ { \ @@ -619,7 +626,11 @@ enum mips_code_readable_setting { # if MIPS_ISA_DEFAULT == 64 # define MULTILIB_ISA_DEFAULT "mips64" # else -# define MULTILIB_ISA_DEFAULT "mips1" +# if MIPS_ISA_DEFAULT == 65 +# define MULTILIB_ISA_DEFAULT "mips64r2" +# else +# define MULTILIB_ISA_DEFAULT "mips1" +# endif # endif # endif # endif @@ -670,6 +681,7 @@ enum mips_code_readable_setting { %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ |march=34k*|march=74k*: -mips32r2} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \ + %{march=mips64r2: -mips64r2} \ %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" /* A spec that infers a -mhard-float or -msoft-float setting from an @@ -726,7 +738,8 @@ enum mips_code_readable_setting { /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ || ISA_MIPS4 \ - || ISA_MIPS64) + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* ISA has branch likely instructions (e.g. mips2). */ /* Disable branchlikely for tx39 until compare rewrite. They haven't @@ -742,7 +755,8 @@ enum mips_code_readable_setting { || TARGET_MAD \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* ISA has the floating-point conditional move instructions introduced @@ -750,7 +764,8 @@ enum mips_code_readable_setting { #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS5500 \ && !TARGET_MIPS16) @@ -766,18 +781,20 @@ enum mips_code_readable_setting { #define ISA_HAS_8CC (ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* This is a catch all for other mips4 instructions: indexed load, the FP madd and msub instructions, and the FP recip and recip sqrt instructions. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ || (ISA_MIPS32R2 && TARGET_FLOAT64) \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* ISA has paired-single instructions. */ -#define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64) +#define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) /* ISA has conditional trap instructions. */ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ @@ -786,7 +803,8 @@ enum mips_code_readable_setting { /* ISA has integer multiply-accumulate instructions, madd and msub. */ #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* Integer multiply-accumulate instructions should be generated. */ @@ -803,7 +821,8 @@ enum mips_code_readable_setting { #define ISA_HAS_NMADD4_NMSUB4(MODE) \ ((ISA_MIPS4 \ || (ISA_MIPS32R2 && (MODE) == V2SFmode) \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && (!TARGET_MIPS5400 || TARGET_MAD) \ && !TARGET_MIPS16) @@ -815,7 +834,8 @@ enum mips_code_readable_setting { /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* ISA has three operand multiply instructions that put @@ -855,6 +875,7 @@ enum mips_code_readable_setting { /* ISA has the "ror" (rotate right) instructions. */ #define ISA_HAS_ROR ((ISA_MIPS32R2 \ + || ISA_MIPS64R2 \ || TARGET_MIPS5400 \ || TARGET_MIPS5500 \ || TARGET_SR71K \ @@ -865,7 +886,8 @@ enum mips_code_readable_setting { #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* ISA has data indexed prefetch instructions. This controls use of @@ -874,7 +896,8 @@ enum mips_code_readable_setting { enabled.) */ #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ || ISA_MIPS32R2 \ - || ISA_MIPS64) \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* True if trunc.w.s and trunc.w.d are real (not synthetic) @@ -883,15 +906,19 @@ enum mips_code_readable_setting { #define ISA_HAS_TRUNC_W (!ISA_MIPS1) /* ISA includes the MIPS32r2 seb and seh instructions. */ -#define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \ +#define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ -#define ISA_HAS_EXT_INS (ISA_MIPS32R2 \ +#define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \ + || ISA_MIPS64R2) \ && !TARGET_MIPS16) /* ISA has instructions for accessing top part of 64-bit fp regs. */ -#define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2) +#define ISA_HAS_MXHC1 (TARGET_FLOAT64 \ + && (ISA_MIPS32R2 \ + || ISA_MIPS64R2)) /* ISA has lwxs instruction (load w/scaled index address. */ #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16) @@ -932,11 +959,14 @@ enum mips_code_readable_setting { #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \ + || ISA_MIPS64R2 \ || TARGET_MIPS5500 \ || TARGET_LOONGSON_2EF) /* ISA includes synci, jr.hb and jalr.hb. */ -#define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16) +#define ISA_HAS_SYNCI ((ISA_MIPS32R2 \ + || ISA_MIPS64R2) \ + && !TARGET_MIPS16) /* ISA includes sync. */ #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16) @@ -1033,7 +1063,7 @@ enum mips_code_readable_setting { #undef ASM_SPEC #define ASM_SPEC "\ %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ -%{mips32} %{mips32r2} %{mips64} \ +%{mips32*} %{mips64*} \ %{mips16} %{mno-mips16:-no-mips16} \ %{mips3d} %{mno-mips3d:-no-mips3d} \ %{mdmx} %{mno-mdmx:-no-mdmx} \ @@ -1059,7 +1089,7 @@ enum mips_code_readable_setting { #ifndef LINK_SPEC #define LINK_SPEC "\ %(endian_spec) \ -%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \ +%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ %{bestGnum} %{shared} %{non_shared}" #endif /* LINK_SPEC defined */ @@ -1214,7 +1244,8 @@ enum mips_code_readable_setting { /* The number of consecutive floating-point registers needed to store the smallest format supported by the FPU. */ #define MIN_FPRS_PER_FMT \ - (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT) + (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \ + ? 1 : MAX_FPRS_PER_FMT) /* The largest size of value that can be held in floating-point registers and moved with a single instruction. */ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 33f0018abfe..c2495b32aec 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -629,7 +629,8 @@ Objective-C and Objective-C++ Dialects}. @emph{MIPS Options} @gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol --mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol +-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol +-mips64 -mips64r2 @gol -mips16 -mno-mips16 -mflip-mips16 @gol -minterlink-mips16 -mno-interlink-mips16 @gol -mabi=@var{abi} -mabicalls -mno-abicalls @gol @@ -11963,7 +11964,7 @@ Generate code that will run on @var{arch}, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4}, -@samp{mips32}, @samp{mips32r2}, and @samp{mips64}. +@samp{mips32}, @samp{mips32r2}, @samp{mips64} and @samp{mips64r2}. The processor names are: @samp{4kc}, @samp{4km}, @samp{4kp}, @samp{4ksc}, @samp{4kec}, @samp{4kem}, @samp{4kep}, @samp{4ksd}, @@ -12065,6 +12066,10 @@ Equivalent to @samp{-march=mips32r2}. @opindex mips64 Equivalent to @samp{-march=mips64}. +@item -mips64r2 +@opindex mips64r2 +Equivalent to @samp{-march=mips64r2}. + @item -mips16 @itemx -mno-mips16 @opindex mips16 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6e460bc0283..6f9210d8336 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2008-07-31 Adam Nemet + + * gcc.target/mips/ext-1.c: New test. + 2008-07-31 Eric Botcazou * gnat.dg/discr10.ad[sb]: New test. diff --git a/gcc/testsuite/gcc.target/mips/ext-1.c b/gcc/testsuite/gcc.target/mips/ext-1.c new file mode 100644 index 00000000000..1cd111d5e33 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/ext-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O -mips64r2" } */ +/* { dg-final { scan-assembler "\tdext\t" } } */ +/* { dg-final { scan-assembler-not "and" } } */ + +struct +{ + unsigned long long a:9; + unsigned long long d:35; + unsigned long long e:10; + unsigned long long f:10; +} t; + +NOMIPS16 unsigned long long +f (void) +{ + return t.d; +} -- 2.11.4.GIT