From 48214222a2dcfca8e75b82b9e956dfdcf60bf2e0 Mon Sep 17 00:00:00 2001 From: clyon Date: Mon, 26 Jan 2015 15:45:00 +0000 Subject: [PATCH] [ARM/AArch64][testsuite] Add vmla_n and vmls_n tests. 2015-01-26 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220118 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/testsuite/ChangeLog | 6 ++ .../aarch64/advsimd-intrinsics/vmlX_n.inc | 87 ++++++++++++++++++++++ .../gcc.target/aarch64/advsimd-intrinsics/vmla_n.c | 23 ++++++ .../gcc.target/aarch64/advsimd-intrinsics/vmls_n.c | 25 +++++++ 4 files changed, 141 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6e099f6f063..4d5b5a665bc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-01-26 Christophe Lyon + * gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file. + * gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file. + * gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file. + +2015-01-26 Christophe Lyon + * gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc new file mode 100644 index 00000000000..375023a77cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc @@ -0,0 +1,87 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ +#define DECL_VMLX_N(VAR) \ + DECL_VARIABLE(VAR, int, 16, 4); \ + DECL_VARIABLE(VAR, int, 32, 2); \ + DECL_VARIABLE(VAR, uint, 16, 4); \ + DECL_VARIABLE(VAR, uint, 32, 2); \ + DECL_VARIABLE(VAR, float, 32, 2); \ + DECL_VARIABLE(VAR, int, 16, 8); \ + DECL_VARIABLE(VAR, int, 32, 4); \ + DECL_VARIABLE(VAR, uint, 16, 8); \ + DECL_VARIABLE(VAR, float, 32, 4); \ + DECL_VARIABLE(VAR, uint, 32, 4) + + /* vector_res = vmlx_n(vector, vector2, val), + then store the result. */ +#define TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W, N), \ + V); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)) + +#define TEST_VMLX_N(INSN, Q, T1, T2, W, N, V) \ + TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V) + + DECL_VMLX_N(vector); + DECL_VMLX_N(vector2); + DECL_VMLX_N(vector_res); + + clean_results (); + + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, , uint, u, 16, 4); + VLOAD(vector, buffer, , uint, u, 32, 2); + VLOAD(vector, buffer, , float, f, 32, 2); + VLOAD(vector, buffer, q, int, s, 16, 8); + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, uint, u, 16, 8); + VLOAD(vector, buffer, q, uint, u, 32, 4); + VLOAD(vector, buffer, q, float, f, 32, 4); + + VDUP(vector2, , int, s, 16, 4, 0x55); + VDUP(vector2, , int, s, 32, 2, 0x55); + VDUP(vector2, , uint, u, 16, 4, 0x55); + VDUP(vector2, , uint, u, 32, 2, 0x55); + VDUP(vector2, , float, f, 32, 2, 55.2f); + VDUP(vector2, q, int, s, 16, 8, 0x55); + VDUP(vector2, q, int, s, 32, 4, 0x55); + VDUP(vector2, q, uint, u, 16, 8, 0x55); + VDUP(vector2, q, uint, u, 32, 4, 0x55); + VDUP(vector2, q, float, f, 32, 4, 55.9f); + + /* Choose multiplier arbitrarily. */ + TEST_VMLX_N(INSN_NAME, , int, s, 16, 4, 0x11); + TEST_VMLX_N(INSN_NAME, , int, s, 32, 2, 0x22); + TEST_VMLX_N(INSN_NAME, , uint, u, 16, 4, 0x33); + TEST_VMLX_N(INSN_NAME, , uint, u, 32, 2, 0x44); + TEST_VMLX_N(INSN_NAME, , float, f, 32, 2, 22.3f); + TEST_VMLX_N(INSN_NAME, q, int, s, 16, 8, 0x55); + TEST_VMLX_N(INSN_NAME, q, int, s, 32, 4, 0x66); + TEST_VMLX_N(INSN_NAME, q, uint, u, 16, 8, 0x77); + TEST_VMLX_N(INSN_NAME, q, uint, u, 32, 4, 0x88); + TEST_VMLX_N(INSN_NAME, q, float, f, 32, 4, 66.7f); + + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c new file mode 100644 index 00000000000..8e88aad2464 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c @@ -0,0 +1,23 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmla +#define TEST_MSG "VMLA_N" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,4) [] = { 0x595, 0x596, 0x597, 0x598 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xb3a, 0xb3b }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1684, 0x1685 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4497deb8, 0x4497feb8 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c29, 0x1c2a, 0x1c2b, 0x1c2c, + 0x1c2d, 0x1c2e, 0x1c2f, 0x1c30 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x21ce, 0x21cf, 0x21d0, 0x21d1 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x2773, 0x2774, 0x2775, 0x2776, + 0x2777, 0x2778, 0x2779, 0x277a }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x2d18, 0x2d19, 0x2d1a, 0x2d1b }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x4568087b, 0x4568187b, + 0x4568287b, 0x4568387b }; + +#include "vmlX_n.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c new file mode 100644 index 00000000000..228673b4723 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c @@ -0,0 +1,25 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmls +#define TEST_MSG "VMLS_N" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfa4b, 0xfa4c, 0xfa4d, 0xfa4e }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff4a6, 0xfffff4a7 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xef01, 0xef02, 0xef03, 0xef04 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffe95c, 0xffffe95d }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc49bdeb8, 0xc49bbeb8 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0xe3b7, 0xe3b8, 0xe3b9, 0xe3ba, + 0xe3bb, 0xe3bc, 0xe3bd, 0xe3be }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffde12, 0xffffde13, + 0xffffde14, 0xffffde15 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd86d, 0xd86e, 0xd86f, 0xd870, + 0xd871, 0xd872, 0xd873, 0xd874 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffd2c8, 0xffffd2c9, + 0xffffd2ca, 0xffffd2cb }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc56a087b, 0xc569f87b, + 0xc569e87b, 0xc569d87b }; + +#include "vmlX_n.inc" -- 2.11.4.GIT