From 4321da7b93e4a5de7ca73a9933db8be6822a9ff1 Mon Sep 17 00:00:00 2001 From: Vladimir Makarov Date: Fri, 11 Jan 2019 19:25:31 +0000 Subject: [PATCH] re PR rtl-optimization/87305 (Segfault in end_hard_regno in setup_live_pseudos_and_spill_after_risky_transforms on aarch64 big-endian) 2019-01-11 Vladimir Makarov PR rtl-optimization/87305 * lra-assigns.c (setup_live_pseudos_and_spill_after_risky_transforms): Add code for little endian pseudos used as paradoxical subreg. From-SVN: r267854 --- gcc/ChangeLog | 7 +++++++ gcc/lra-assigns.c | 12 ++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bca96c04ac8..3185dd6e50c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-01-11 Vladimir Makarov + + PR rtl-optimization/87305 + * lra-assigns.c + (setup_live_pseudos_and_spill_after_risky_transforms): Add code + for little endian pseudos used as paradoxical subreg. + 2019-01-11 Jakub Jelinek PR tree-optimization/88693 diff --git a/gcc/lra-assigns.c b/gcc/lra-assigns.c index bcd81450c06..8b56b58fb2e 100644 --- a/gcc/lra-assigns.c +++ b/gcc/lra-assigns.c @@ -1174,10 +1174,14 @@ setup_live_pseudos_and_spill_after_risky_transforms (bitmap - hard_regno_nregs (hard_regno, PSEUDO_REGNO_MODE (i))); enum reg_class rclass = lra_get_allocno_class (i); - if (WORDS_BIG_ENDIAN - && (hard_regno - nregs_diff < 0 - || !TEST_HARD_REG_BIT (reg_class_contents[rclass], - hard_regno - nregs_diff))) + if ((WORDS_BIG_ENDIAN + && (hard_regno - nregs_diff < 0 + || !TEST_HARD_REG_BIT (reg_class_contents[rclass], + hard_regno - nregs_diff))) + || (!WORDS_BIG_ENDIAN + && (hard_regno + nregs_diff >= FIRST_PSEUDO_REGISTER + || !TEST_HARD_REG_BIT (reg_class_contents[rclass], + hard_regno + nregs_diff)))) { /* Hard registers of paradoxical sub-registers are out of range of pseudo register class. Spill the pseudo. */ -- 2.11.4.GIT