From 3ec5b5f015903512558b480752056ac9e41e8f3d Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Thu, 31 Aug 2017 16:03:09 +0000 Subject: [PATCH] [AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge The MLA by-element instructions have the same restriction as other by-element instructions whereby the forms operating on vectors of 16-bit integer data may only use registers v0-v15. We have an iterator for that, applied to the other patterns generating this instruction, so use that. gcc/ * config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge): Fix register constraint for by-element operand. (aarch64_mls_elt_merge): Likewise. From-SVN: r251568 --- gcc/ChangeLog | 6 ++++++ gcc/config/aarch64/aarch64-simd.md | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cf1e005c158..1d3794c07dc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-08-31 James Greenhalgh + + * config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge): Fix + register constraint for by-element operand. + (aarch64_mls_elt_merge): Likewise. + 2017-08-31 Claudiu Zissulescu * config/arc/arc.c (arc_can_follow_jump): Check for short diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a94c6fdabdc..8f045c21050 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1072,7 +1072,7 @@ [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS (mult:VDQHS (vec_duplicate:VDQHS - (match_operand: 1 "register_operand" "w")) + (match_operand: 1 "register_operand" "")) (match_operand:VDQHS 2 "register_operand" "w")) (match_operand:VDQHS 3 "register_operand" "0")))] "TARGET_SIMD" @@ -1132,7 +1132,7 @@ (minus:VDQHS (match_operand:VDQHS 1 "register_operand" "0") (mult:VDQHS (vec_duplicate:VDQHS - (match_operand: 2 "register_operand" "w")) + (match_operand: 2 "register_operand" "")) (match_operand:VDQHS 3 "register_operand" "w"))))] "TARGET_SIMD" "mls\t%0., %3., %2.[0]" -- 2.11.4.GIT