From 1ae6cf680aabd9ea97fa10556959e9854592e625 Mon Sep 17 00:00:00 2001 From: rsandifo Date: Tue, 8 May 2018 11:42:15 +0000 Subject: [PATCH] Move C++ SVE tests to g++.target/aarch64/sve 2018-05-08 Richard Sandiford gcc/testsuite/ * g++.dg/other/sve_const_pred_1.C: Rename to... * g++.target/aarch64/sve/const_pred_1.C: ...this. Remove aarch64 target selectors and explicit -march options. * g++.dg/other/sve_const_pred_2.C: Rename to... * g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise. * g++.dg/other/sve_const_pred_3.C: Rename to... * g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise. * g++.dg/other/sve_const_pred_4.C: Rename to... * g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise. * g++.dg/other/sve_tls_2.C: Rename to... * g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise. * g++.dg/other/sve_vcond_1.C: Rename to... * g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise. * g++.dg/other/sve_vcond_1_run.C: Rename to... * g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260038 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/testsuite/ChangeLog | 18 ++++++++++++++++++ .../aarch64/sve/const_pred_1.C} | 4 ++-- .../aarch64/sve/const_pred_2.C} | 4 ++-- .../aarch64/sve/const_pred_3.C} | 4 ++-- .../aarch64/sve/const_pred_4.C} | 4 ++-- .../sve_tls_2.C => g++.target/aarch64/sve/tls_2.C} | 4 ++-- .../sve_vcond_1.C => g++.target/aarch64/sve/vcond_1.C} | 2 +- .../aarch64/sve/vcond_1_run.C} | 4 ++-- 8 files changed, 31 insertions(+), 13 deletions(-) rename gcc/testsuite/{g++.dg/other/sve_const_pred_1.C => g++.target/aarch64/sve/const_pred_1.C} (78%) rename gcc/testsuite/{g++.dg/other/sve_const_pred_2.C => g++.target/aarch64/sve/const_pred_2.C} (75%) rename gcc/testsuite/{g++.dg/other/sve_const_pred_3.C => g++.target/aarch64/sve/const_pred_3.C} (73%) rename gcc/testsuite/{g++.dg/other/sve_const_pred_4.C => g++.target/aarch64/sve/const_pred_4.C} (72%) rename gcc/testsuite/{g++.dg/other/sve_tls_2.C => g++.target/aarch64/sve/tls_2.C} (85%) rename gcc/testsuite/{g++.dg/other/sve_vcond_1.C => g++.target/aarch64/sve/vcond_1.C} (99%) rename gcc/testsuite/{g++.dg/other/sve_vcond_1_run.C => g++.target/aarch64/sve/vcond_1_run.C} (88%) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5393aab0fe3..2628d55dc23 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,23 @@ 2018-05-08 Richard Sandiford + * g++.dg/other/sve_const_pred_1.C: Rename to... + * g++.target/aarch64/sve/const_pred_1.C: ...this. Remove aarch64 + target selectors and explicit -march options. + * g++.dg/other/sve_const_pred_2.C: Rename to... + * g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise. + * g++.dg/other/sve_const_pred_3.C: Rename to... + * g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise. + * g++.dg/other/sve_const_pred_4.C: Rename to... + * g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise. + * g++.dg/other/sve_tls_2.C: Rename to... + * g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise. + * g++.dg/other/sve_vcond_1.C: Rename to... + * g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise. + * g++.dg/other/sve_vcond_1_run.C: Rename to... + * g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise. + +2018-05-08 Richard Sandiford + PR testsuite/85586 * gcc.dg/vect/pr85586.c: Restrict LOOP VECTORIZED test to !vect_no_align. diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_1.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C similarity index 78% rename from gcc/testsuite/g++.dg/other/sve_const_pred_1.C rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C index cc124c06ee5..25b7663273f 100644 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_1.C +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C @@ -1,5 +1,5 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ #include diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_2.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C similarity index 75% rename from gcc/testsuite/g++.dg/other/sve_const_pred_2.C rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C index e3bce397cbf..4c781ca560c 100644 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_2.C +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C @@ -1,5 +1,5 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ #include diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_3.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C similarity index 73% rename from gcc/testsuite/g++.dg/other/sve_const_pred_3.C rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C index 9e75f399e4b..6196ee05be7 100644 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_3.C +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C @@ -1,5 +1,5 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ #include diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_4.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C similarity index 72% rename from gcc/testsuite/g++.dg/other/sve_const_pred_4.C rename to gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C index 04a13513380..2bdf67fd038 100644 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_4.C +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C @@ -1,5 +1,5 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ #include diff --git a/gcc/testsuite/g++.dg/other/sve_tls_2.C b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C similarity index 85% rename from gcc/testsuite/g++.dg/other/sve_tls_2.C rename to gcc/testsuite/g++.target/aarch64/sve/tls_2.C index ed4689353ae..9267f1e92d1 100644 --- a/gcc/testsuite/g++.dg/other/sve_tls_2.C +++ b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C @@ -1,6 +1,6 @@ -/* { dg-do compile { target aarch64*-*-* } } */ +/* { dg-do compile } */ /* { dg-require-effective-target tls } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -fPIC -msve-vector-bits=256" } */ +/* { dg-options "-O2 -fPIC -msve-vector-bits=256" } */ #include diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C similarity index 99% rename from gcc/testsuite/g++.dg/other/sve_vcond_1.C rename to gcc/testsuite/g++.target/aarch64/sve/vcond_1.C index c1ad0b91b0c..2a80d21abb9 100644 --- a/gcc/testsuite/g++.dg/other/sve_vcond_1.C +++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C @@ -1,5 +1,5 @@ /* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */ -/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */ +/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */ typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32))); typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32))); diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C similarity index 88% rename from gcc/testsuite/g++.dg/other/sve_vcond_1_run.C rename to gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C index b542356dbf8..d01745e6864 100644 --- a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C +++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C @@ -1,6 +1,6 @@ /* { dg-do run { target aarch64_sve_hw } } */ -/* { dg-options "-O -march=armv8.2-a+sve" } */ -/* { dg-options "-O -march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64_sve256_hw } } */ +/* { dg-options "-O" } */ +/* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */ #include "sve_vcond_1.c" -- 2.11.4.GIT