From 0e47d6c808fa5448f77850b4289fd612a37f53a3 Mon Sep 17 00:00:00 2001 From: Ilya Leoshkevich Date: Fri, 8 Jan 2021 14:01:20 +0100 Subject: [PATCH] IBM Z: Fix constraints in vpdi patterns The destination register is only partially overwritten, so + should be used instead of =. gcc/ChangeLog: 2021-01-08 Ilya Leoshkevich * config/s390/vector.md (*tf_to_fprx2_0): Rename from "*mov_tf_to_fprx2_0" for consistency, fix constraint. (*tf_to_fprx2_1): Rename from "*mov_tf_to_fprx2_1" for consistency, fix constraint. --- gcc/config/s390/vector.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 5b8d75f18f0..0e3c31f5d4f 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -737,16 +737,16 @@ "vperm\t%v0,%v1,%v2,%v3" [(set_attr "op_type" "VRR")]) -(define_insn "*mov_tf_to_fprx2_0" - [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0) +(define_insn "*tf_to_fprx2_0" + [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "+f") 0) (subreg:DF (match_operand:TF 1 "general_operand" "v") 0))] "TARGET_VXE" ; M4 == 1 corresponds to %v0[0] = %v1[0]; %v0[1] = %v0[1]; "vpdi\t%v0,%v1,%v0,1" [(set_attr "op_type" "VRR")]) -(define_insn "*mov_tf_to_fprx2_1" - [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 8) +(define_insn "*tf_to_fprx2_1" + [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "+f") 8) (subreg:DF (match_operand:TF 1 "general_operand" "v") 8))] "TARGET_VXE" ; M4 == 5 corresponds to %V0[0] = %v1[1]; %V0[1] = %V0[1]; -- 2.11.4.GIT