From 074a13b9bd1a194c0ff23d37b62c18e96bbc177e Mon Sep 17 00:00:00 2001 From: clyon Date: Tue, 10 Sep 2013 09:15:45 +0000 Subject: [PATCH] 2013-09-10 Venkataramanan Kumar gcc/ Backport from trunk r200197, 201411. 2013-06-19 Richard Earnshaw arm.md (split for eq(reg, 0)): Add variants for ARMv5 and Thumb2. (peepholes for eq(reg, not-0)): Ensure condition register is dead after pattern. Use more efficient sequences on ARMv5 and Thumb2. 2013-08-01 Kyrylo Tkachov * config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)): Generate canonical plus rtx with negated immediate instead of minus where appropriate. * config/arm/arm.c (thumb2_reorg): Handle ADCS , case. gcc/testsuite/ Backport from trunk r201411. 2013-08-01 Kyrylo Tkachov * gcc.target/arm/pr46972-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro@202430 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc-4_8-branch/gcc/ChangeLog.linaro | 16 ++++ gcc-4_8-branch/gcc/config/arm/arm.c | 10 +++ gcc-4_8-branch/gcc/config/arm/arm.md | 94 +++++++++++++++++++--- gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro | 7 ++ .../gcc/testsuite/gcc.target/arm/pr46975-2.c | 10 +++ 5 files changed, 127 insertions(+), 10 deletions(-) create mode 100644 gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr46975-2.c diff --git a/gcc-4_8-branch/gcc/ChangeLog.linaro b/gcc-4_8-branch/gcc/ChangeLog.linaro index 44ab523ffdb..d297f840f5c 100644 --- a/gcc-4_8-branch/gcc/ChangeLog.linaro +++ b/gcc-4_8-branch/gcc/ChangeLog.linaro @@ -1,3 +1,19 @@ +2013-09-10 Venkataramanan Kumar + + Backport from trunk r200197, 201411. + 2013-06-19 Richard Earnshaw + + arm.md (split for eq(reg, 0)): Add variants for ARMv5 and Thumb2. + (peepholes for eq(reg, not-0)): Ensure condition register is dead after + pattern. Use more efficient sequences on ARMv5 and Thumb2. + + 2013-08-01 Kyrylo Tkachov + + * config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)): + Generate canonical plus rtx with negated immediate instead of minus + where appropriate. + * config/arm/arm.c (thumb2_reorg): Handle ADCS , case. + 2013-09-10 Christophe Lyon Backport from trunk r200593,201024,201025,201122,201124,201126. diff --git a/gcc-4_8-branch/gcc/config/arm/arm.c b/gcc-4_8-branch/gcc/config/arm/arm.c index 312d1ddfac0..fde7d6fe6fe 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.c +++ b/gcc-4_8-branch/gcc/config/arm/arm.c @@ -14349,6 +14349,16 @@ thumb2_reorg (void) && IN_RANGE (INTVAL (op1), -7, 7)) action = CONV; } + /* ADCS , */ + else if (GET_CODE (XEXP (src, 0)) == PLUS + && rtx_equal_p (XEXP (XEXP (src, 0), 0), dst) + && low_register_operand (XEXP (XEXP (src, 0), 1), + SImode) + && COMPARISON_P (op1) + && cc_register (XEXP (op1, 0), VOIDmode) + && maybe_get_arm_condition_code (op1) == ARM_CS + && XEXP (op1, 1) == const0_rtx) + action = CONV; break; case MINUS: diff --git a/gcc-4_8-branch/gcc/config/arm/arm.md b/gcc-4_8-branch/gcc/config/arm/arm.md index 615c1ea3bb3..6c676c76a13 100644 --- a/gcc-4_8-branch/gcc/config/arm/arm.md +++ b/gcc-4_8-branch/gcc/config/arm/arm.md @@ -10291,6 +10291,16 @@ (eq:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0))) (clobber (reg:CC CC_REGNUM))] + "arm_arch5 && TARGET_32BIT" + [(set (match_dup 0) (clz:SI (match_dup 1))) + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] +) + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (eq:SI (match_operand:SI 1 "s_register_operand" "") + (const_int 0))) + (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && reload_completed" [(parallel [(set (reg:CC CC_REGNUM) @@ -10360,29 +10370,93 @@ ;; Attempt to improve the sequence generated by the compare_scc splitters ;; not to use conditional execution. + +;; Rd = (eq (reg1) (const_int0)) // ARMv5 +;; clz Rd, reg1 +;; lsr Rd, Rd, #5 (define_peephole2 [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" ""))) + (const_int 0))) + (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) + (set (match_operand:SI 0 "register_operand" "") (const_int 0))) + (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) (const_int 1)))] + "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" + [(set (match_dup 0) (clz:SI (match_dup 1))) + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] +) + +;; Rd = (eq (reg1) (const_int0)) // !ARMv5 +;; negs Rd, reg1 +;; adc Rd, Rd, reg1 +(define_peephole2 + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "register_operand" "") + (const_int 0))) (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) (set (match_operand:SI 0 "register_operand" "") (const_int 0))) (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 1))) - (match_scratch:SI 3 "r")] - "TARGET_32BIT" + (match_scratch:SI 2 "r")] + "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (match_dup 1) (match_dup 2))) - (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))]) + (compare:CC (const_int 0) (match_dup 1))) + (set (match_dup 2) (minus:SI (const_int 0) (match_dup 1)))]) + (set (match_dup 0) + (plus:SI (plus:SI (match_dup 1) (match_dup 2)) + (geu:SI (reg:CC CC_REGNUM) (const_int 0))))] +) + +;; Rd = (eq (reg1) (reg2/imm)) // ARMv5 and optimising for speed. +;; sub Rd, Reg1, reg2 +;; clz Rd, Rd +;; lsr Rd, Rd, #5 +(define_peephole2 + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "arm_rhs_operand" ""))) + (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) + (set (match_operand:SI 0 "register_operand" "") (const_int 0))) + (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) (const_int 1)))] + "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM) + && !(TARGET_THUMB2 && optimize_insn_for_size_p ())" + [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (clz:SI (match_dup 0))) + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] +) + + +;; Rd = (eq (reg1) (reg2)) // ! ARMv5 or optimising for size. +;; sub T1, Reg1, reg2 +;; negs Rd, T1 +;; adc Rd, Rd, T1 +(define_peephole2 + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "arm_rhs_operand" ""))) + (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) + (set (match_operand:SI 0 "register_operand" "") (const_int 0))) + (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) (const_int 1))) + (match_scratch:SI 3 "r")] + "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" + [(set (match_dup 3) (match_dup 4)) (parallel [(set (reg:CC CC_REGNUM) (compare:CC (const_int 0) (match_dup 3))) (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) - (parallel - [(set (match_dup 0) - (plus:SI (plus:SI (match_dup 0) (match_dup 3)) - (geu:SI (reg:CC CC_REGNUM) (const_int 0)))) - (clobber (reg:CC CC_REGNUM))])]) + (set (match_dup 0) + (plus:SI (plus:SI (match_dup 0) (match_dup 3)) + (geu:SI (reg:CC CC_REGNUM) (const_int 0))))] + " + if (CONST_INT_P (operands[2])) + operands[4] = plus_constant (SImode, operands[1], -INTVAL (operands[2])); + else + operands[4] = gen_rtx_MINUS (SImode, operands[1], operands[2]); + ") (define_insn "*cond_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") diff --git a/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro b/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro index 30043d78f10..342acc5dd4f 100644 --- a/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro +++ b/gcc-4_8-branch/gcc/testsuite/ChangeLog.linaro @@ -1,3 +1,10 @@ +2013-09-06 Venkataramanan Kumar + + Backport from trunk r201411. + 2013-08-01 Kyrylo Tkachov + + * gcc.target/arm/pr46972-2.c: New test. + 2013-09-05 Yvan Roux Backport from trunk r201267. diff --git a/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr46975-2.c b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr46975-2.c new file mode 100644 index 00000000000..f4017e3f78d --- /dev/null +++ b/gcc-4_8-branch/gcc/testsuite/gcc.target/arm/pr46975-2.c @@ -0,0 +1,10 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler "sub" } } */ +/* { dg-final { scan-assembler "clz" } } */ +/* { dg-final { scan-assembler "lsr.*#5" } } */ + +int foo (int s) +{ + return s == 1; +} -- 2.11.4.GIT