From 01fdb4cf5d52bd94ee85e8eef63279cdc1e46928 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 26 Sep 2007 16:45:39 +0000 Subject: [PATCH] re PR target/33479 (SyncTest Intermittent failing on MIPS) 2007-09-26 David Daney PR target/33479 * config/mips/mips.md (sync_compare_and_swap, sync_old_add, sync_new_add, sync_old_, sync_new_, sync_old_nand, sync_new_nand, sync_lock_test_and_set): Fix '&' constraint modifiers. Update length attributes. (sync_add, sync_sub, sync_old_sub, sync_new_sub, sync_, sync_nand): Update length attributes. * config/mips/mips.h (MIPS_COMPARE_AND_SWAP, MIPS_SYNC_OP, MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE): Add post-loop sync. From-SVN: r128821 --- gcc/ChangeLog | 16 ++++++++++++++++ gcc/config/mips/mips.h | 41 ++++++++++++++++++++--------------------- gcc/config/mips/mips.md | 44 ++++++++++++++++++++++---------------------- 3 files changed, 58 insertions(+), 43 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a85f8fcadc8..2147dedb02b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2007-09-26 David Daney + + PR target/33479 + * config/mips/mips.md (sync_compare_and_swap, sync_old_add, + sync_new_add, sync_old_, sync_new_, + sync_old_nand, sync_new_nand, + sync_lock_test_and_set): Fix '&' constraint modifiers. + Update length attributes. + (sync_add, sync_sub, sync_old_sub, + sync_new_sub, sync_, sync_nand): Update + length attributes. + * config/mips/mips.h (MIPS_COMPARE_AND_SWAP, MIPS_SYNC_OP, + MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, + MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE): Add + post-loop sync. + 2007-09-26 Richard Guenther PR tree-optimization/33563 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index d401d551a47..01d851d7f93 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2952,11 +2952,10 @@ while (0) "1:\tll" SUFFIX "\t%0,%1\n" \ "\tbne\t%0,%2,2f\n" \ "\t" OP "\t%@,%3\n" \ - "\tsc" SUFFIX "\t%@,%1" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq\t%@,%.,1b\n" \ "\tnop\n" \ - "2:%]%>%)" + "2:\tsync%-%]%>%)" /* Return an asm string that atomically: @@ -2968,10 +2967,10 @@ while (0) "%(%<%[%|sync\n" \ "1:\tll" SUFFIX "\t%@,%0\n" \ "\t" INSN "\t%@,%@,%1\n" \ - "\tsc" SUFFIX "\t%@,%0" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%0\n" \ "\tbeq\t%@,%.,1b\n" \ - "\tnop%]%>%)" + "\tnop\n" \ + "\tsync%-%]%>%)" /* Return an asm string that atomically: @@ -2985,10 +2984,10 @@ while (0) "%(%<%[%|sync\n" \ "1:\tll" SUFFIX "\t%0,%1\n" \ "\t" INSN "\t%@,%0,%2\n" \ - "\tsc" SUFFIX "\t%@,%1" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq\t%@,%.,1b\n" \ - "\tnop%]%>%)" + "\tnop\n" \ + "\tsync%-%]%>%)" /* Return an asm string that atomically: @@ -3002,10 +3001,10 @@ while (0) "%(%<%[%|sync\n" \ "1:\tll" SUFFIX "\t%0,%1\n" \ "\t" INSN "\t%@,%0,%2\n" \ - "\tsc" SUFFIX "\t%@,%1" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq\t%@,%.,1b\n" \ - "\t" INSN "\t%0,%0,%2%]%>%)" + "\t" INSN "\t%0,%0,%2\n" \ + "\tsync%-%]%>%)" /* Return an asm string that atomically: @@ -3019,10 +3018,10 @@ while (0) "1:\tll" SUFFIX "\t%@,%0\n" \ "\tnor\t%@,%@,%.\n" \ "\t" INSN "\t%@,%@,%1\n" \ - "\tsc" SUFFIX "\t%@,%0" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%0\n" \ "\tbeq\t%@,%.,1b\n" \ - "\tnop%]%>%)" + "\tnop\n" \ + "\tsync%-%]%>%)" /* Return an asm string that atomically: @@ -3038,10 +3037,10 @@ while (0) "1:\tll" SUFFIX "\t%0,%1\n" \ "\tnor\t%@,%0,%.\n" \ "\t" INSN "\t%@,%@,%2\n" \ - "\tsc" SUFFIX "\t%@,%1" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq\t%@,%.,1b\n" \ - "\tnop%]%>%)" + "\tnop\n" \ + "\tsync%-%]%>%)" /* Return an asm string that atomically: @@ -3057,10 +3056,10 @@ while (0) "1:\tll" SUFFIX "\t%0,%1\n" \ "\tnor\t%0,%0,%.\n" \ "\t" INSN "\t%@,%0,%2\n" \ - "\tsc" SUFFIX "\t%@,%1" \ - "%-\n" \ + "\tsc" SUFFIX "\t%@,%1\n" \ "\tbeq\t%@,%.,1b\n" \ - "\t" INSN "\t%0,%0,%2%]%>%)" + "\t" INSN "\t%0,%0,%2\n" \ + "\tsync%-%]%>%)" /* Return an asm string that atomically: diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 92d5ab269f3..d687223c382 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4328,7 +4328,7 @@ "%|sync%-") (define_insn "sync_compare_and_swap" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=&d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d") @@ -4341,7 +4341,7 @@ else return MIPS_COMPARE_AND_SWAP ("", "move"); } - [(set_attr "length" "28")]) + [(set_attr "length" "32")]) (define_insn "sync_add" [(set (match_operand:GPR 0 "memory_operand" "+R,R") @@ -4356,7 +4356,7 @@ else return MIPS_SYNC_OP ("", "addu"); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_sub" [(set (match_operand:GPR 0 "memory_operand" "+R") @@ -4366,12 +4366,12 @@ UNSPEC_SYNC_OLD_OP))] "GENERATE_LL_SC" { - return MIPS_SYNC_OP ("", "subu"); + return MIPS_SYNC_OP ("", "subu"); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_old_add" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR @@ -4385,7 +4385,7 @@ else return MIPS_SYNC_OLD_OP ("", "addu"); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_old_sub" [(set (match_operand:GPR 0 "register_operand" "=&d") @@ -4399,10 +4399,10 @@ { return MIPS_SYNC_OLD_OP ("", "subu"); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_new_add" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R") (match_operand:GPR 2 "arith_operand" "I,d"))) (set (match_dup 1) @@ -4416,7 +4416,7 @@ else return MIPS_SYNC_NEW_OP ("", "addu"); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_new_sub" [(set (match_operand:GPR 0 "register_operand" "=&d") @@ -4430,7 +4430,7 @@ { return MIPS_SYNC_NEW_OP ("", "subu"); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_" [(set (match_operand:GPR 0 "memory_operand" "+R,R") @@ -4445,10 +4445,10 @@ else return MIPS_SYNC_OP ("", ""); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_old_" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR @@ -4462,10 +4462,10 @@ else return MIPS_SYNC_OLD_OP ("", ""); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_new_" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR @@ -4479,7 +4479,7 @@ else return MIPS_SYNC_NEW_OP ("", ""); } - [(set_attr "length" "24")]) + [(set_attr "length" "28")]) (define_insn "sync_nand" [(set (match_operand:GPR 0 "memory_operand" "+R,R") @@ -4492,10 +4492,10 @@ else return MIPS_SYNC_NAND ("", "and"); } - [(set_attr "length" "28")]) + [(set_attr "length" "32")]) (define_insn "sync_old_nand" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] @@ -4507,10 +4507,10 @@ else return MIPS_SYNC_OLD_NAND ("", "and"); } - [(set_attr "length" "28")]) + [(set_attr "length" "32")]) (define_insn "sync_new_nand" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] @@ -4522,10 +4522,10 @@ else return MIPS_SYNC_NEW_NAND ("", "and"); } - [(set_attr "length" "28")]) + [(set_attr "length" "32")]) (define_insn "sync_lock_test_and_set" - [(set (match_operand:GPR 0 "register_operand" "=&d,d") + [(set (match_operand:GPR 0 "register_operand" "=d,&d") (match_operand:GPR 1 "memory_operand" "+R,R")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")] -- 2.11.4.GIT