| commit | e60593f3881c72a96a3fa4844d73e8a2cd14f670 | |
| author | Andrew Pinski <apinski@marvell.com> | |
| Mon, 5 Jun 2023 02:21:05 +0000 (4 19:21 -0700) | ||
| committer | Andrew Pinski <apinski@marvell.com> | |
| Wed, 7 Jun 2023 02:57:18 +0000 (6 19:57 -0700) | ||
| tree | 1d9dac2ee7b1bbe757d1e346bec3a7479d5ffeba | treesnapshot (tar.gz zip) |
| parent | cc155ff9c38848a8e6a7125dd0b66ac0aef47880 | commitdiff |
Improve do_store_flag for single bit when there is no non-zero bits
In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
turn off the bit tracking part of CCP so we would lose out
what TER was able to do before hand. This moves around the
TER code so that it is used instead of just the nonzerobits.
It also makes it easier to remove the TER part of the code
later on too.
OK? Bootstrapped and tested on x86_64-linux-gnu.
Note it reintroduces PR 110117 (which was accidently fixed after
r14-1534-g908e5ab5c11c). The next patch in series will fix that.
gcc/ChangeLog:
* expr.cc (do_store_flag): Rearrange the
TER code so that it overrides the nonzero bits
info if we had `a & POW2`.
In r14-1534-g908e5ab5c11c, I forgot you could turn off CCP or
turn off the bit tracking part of CCP so we would lose out
what TER was able to do before hand. This moves around the
TER code so that it is used instead of just the nonzerobits.
It also makes it easier to remove the TER part of the code
later on too.
OK? Bootstrapped and tested on x86_64-linux-gnu.
Note it reintroduces PR 110117 (which was accidently fixed after
r14-1534-g908e5ab5c11c). The next patch in series will fix that.
gcc/ChangeLog:
* expr.cc (do_store_flag): Rearrange the
TER code so that it overrides the nonzero bits
info if we had `a & POW2`.
| gcc/expr.cc | diffblobblamehistory |