| commit | fd586718406c518a8221a89ba6acc306f7ec566f | |
| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Fri, 21 Sep 2018 12:25:12 +0000 (21 12:25 +0000) | ||
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Fri, 21 Sep 2018 12:25:12 +0000 (21 12:25 +0000) | ||
| tree | a2920ca60e143c4c7d92dcc97d9a938e0f2377af | treesnapshot (tar.gz zip) |
| parent | dec77c83525963fd6ea50bddfa39ed5fd99ca34e | commitdiff |
[aarch64] Add HiSilicon tsv110 CPU support
This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A.
It has been tested on aarch64 and no regressions from this patch.
2018-09-21 Shaokun Zhang <zhangshaokun@hisilicon.com>
Bo Zhou <zbo.zhou@hisilicon.com>
* config/aarch64/aarch64-cores.def (tsv110): New CPU.
* config/aarch64/aarch64-tune.md: Regenerated.
* doc/invoke.texi (AArch64 Options/-mtune): Add "tsv110".
* config/aarch64/aarch64.c (tsv110_tunings): New tuning table.
* config/aarch64/aarch64-cost-tables.h: Add "tsv110" extra costs.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@264470 138bc75d-0d04-0410-961f-82ee72b054a4
This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A.
It has been tested on aarch64 and no regressions from this patch.
2018-09-21 Shaokun Zhang <zhangshaokun@hisilicon.com>
Bo Zhou <zbo.zhou@hisilicon.com>
* config/aarch64/aarch64-cores.def (tsv110): New CPU.
* config/aarch64/aarch64-tune.md: Regenerated.
* doc/invoke.texi (AArch64 Options/-mtune): Add "tsv110".
* config/aarch64/aarch64.c (tsv110_tunings): New tuning table.
* config/aarch64/aarch64-cost-tables.h: Add "tsv110" extra costs.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@264470 138bc75d-0d04-0410-961f-82ee72b054a4