RISC-V: Add initial pipeline description for an out-of-order core.

RISC-V: Add initial pipeline description for an out-of-order core.

This adds a pipeline description for a generic out-of-order core.
Latency and units are not based on any real processor but more or less
educated guesses what such a processor would look like.

In order to account for latency scaling by LMUL != 1, sched_adjust_cost
is implemented.  It will scale an instruction's latency by its LMUL
so an LMUL == 8 instruction will take 8 times the number of cycles
the same instruction with LMUL == 1 would take.
As this potentially causes very high latencies which, in turn, might
lead to scheduling anomalies and a higher number of vsetvls emitted
this feature is only enabled when specifying -madjust-lmul-cost.

Additionally, in order to easily recognize pre-RA vsetvls this patch
introduces an insn type vsetvl_pre which is used in sched_adjust_cost.

In the future we might also want a latency adjustment similar to lmul
for reductions, i.e. make the latency dependent on the type and its
number of units.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
	Add generic_ooo.
	* config/riscv/riscv.cc (riscv_sched_adjust_cost): Implement
	scheduler hook.
	(TARGET_SCHED_ADJUST_COST): Define.
	* config/riscv/riscv.md (no,yes"): Include generic-ooo.md
	* config/riscv/riscv.opt: Add -madjust-lmul-cost.
	* config/riscv/generic-ooo.md: New file.
	* config/riscv/vector.md: Add vsetvl_pre.