Backport from mainline

	Backport from mainline
	2016-08-23  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>

	* config/i386/i386.c (processor_alias_table): Enable PTA_PRFCHW
	for targets amdfam10 and barcelona.

	Backport from mainline
	2016-08-21  Uros Bizjak  <ubizjak@gmail.com>

	PR target/77270
	* config/i386/i386.md (prefetch): When TARGET_PRFCHW or
	TARGET_PREFETCHWT1 are disabled, emit 3dNOW! write prefetches for
	non-SSE2 athlons only, otherwise prefer SSE prefetches.

	Backport from mainline
	2016-08-19  Uros Bizjak  <ubizjak@gmail.com>

	PR target/77270
	* config/i386/i386.c (ix86_option_override_internal): Remove
	PTA_PRFCHW from entries that also have PTA_3DNOW flag.
	Enable SSE prefetch also for TARGET_PREFETCHWT1.
	Do not try to enable TARGET_PRFCHW ISA flag here.
	* config/i386/i386.md (prefetch): Enable also for TARGET_3DNOW.
	Rewrite expander function body.
	(*prefetch_3dnow): Enable for TARGET_3DNOW and TARGET_PREFETCHWT1.

testsuite/ChangeLog:

	Backport from mainline
	2016-08-24  Uros Bizjak  <ubizjak@gmail.com>

	PR target/77270
	* gcc.dg/tree-ssa/loop-28.c: Also compile on 32bit x86 targets.
	(dg-options): Use -march=amdfam10 instead of -march=athlon.
	* gcc.dg/tree-ssa/update-unroll-1.c: Ditto.
	* gcc.dg/tree-ssa/prefetch-3.c: Ditto.
	* gcc.dg/tree-ssa/prefetch-4.c: Ditto.
	* gcc.dg/tree-ssa/prefetch-5.c: Ditto.
	* gcc.dg/tree-ssa/prefetch-6.c: Ditto.  Do not require sse2
	effective target.  Remove scan-assembler-times directives.
	* gcc.dg/tree-ssa/prefetch-7.c: Ditto.
	* gcc.dg/tree-ssa/prefetch-8.c: Ditto.
	* gcc.dg/tree-ssa/prefetch-9.c: Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@239810 138bc75d-0d04-0410-961f-82ee72b054a4