xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads

xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads

When spilled DFmode registers are reloaded in, once loaded into a pair of
SImode regs and then copied from that regs.  Such unwanted reg-reg moves
seems not to be eliminated at the "cprop_hardreg" stage, despite no problem
in output reloads.

Luckily it is easy to resolve such inefficiencies, with the use of peephole2
pattern.

gcc/ChangeLog:

	* config/xtensa/predicates.md (reload_operand):
	New predicate.
	* config/xtensa/xtensa.md: New peephole2 pattern.