* rs6000.md (arithmetic, logical, and shift Rc combiner patterns):
commitcf74dbaea327e04574822bf7483129f4dc9ed5f1
authordje <dje@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 19 Jul 1999 19:11:29 +0000 (19 19:11 +0000)
committerdje <dje@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 19 Jul 1999 19:11:29 +0000 (19 19:11 +0000)
tree59a3f7cca13239eabf0e1bae23d9ccc82f92201a
parent752fb7ee979d28864cba62a5ea7d4249917823a7
* rs6000.md (arithmetic, logical, and shift Rc combiner patterns):
Disable patterns performing SImode comparisons with SImode values
if TARGET_POWERPC64 and instruction does not sign-extend or does
not mask to narrower than SImode, i.e. where bit 31 and bit 63 may
differ for signed quantities.
(indirect_jump): Add expander to choose RTL based on TARGET_64BIT.
(tablejump): Patterns contingent on TARGET_64BIT not TARGET_POWERPC64.
(decrement_and_branch_on_count): Add 64-bit variant.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@28172 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/rs6000/rs6000.md