* rs6000.md (arithmetic, logical, and shift Rc combiner patterns):
Disable patterns performing SImode comparisons with SImode values
if TARGET_POWERPC64 and instruction does not sign-extend or does
not mask to narrower than SImode, i.e. where bit 31 and bit 63 may
differ for signed quantities.
(indirect_jump): Add expander to choose RTL based on TARGET_64BIT.
(tablejump): Patterns contingent on TARGET_64BIT not TARGET_POWERPC64.
(decrement_and_branch_on_count): Add 64-bit variant.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@28172 138bc75d-0d04-0410-961f-82ee72b054a4