| commit | ce1e682ca21400d9b59f08f0416d96e0bac369d8 | |
| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | |
| Wed, 5 Apr 2023 13:46:36 +0000 (5 07:46 -0600) | ||
| committer | Jeff Law <jlaw@ventanamicro> | |
| Wed, 5 Apr 2023 13:47:39 +0000 (5 07:47 -0600) | ||
| tree | 836878328879802d9ce4e9e73b756f60ec697fb3 | treesnapshot (tar.gz zip) |
| parent | 44e17b8d8999a658af9f86681504d74a119a5f6f | commitdiff |
[PATCH] RISC-V: Fix SEW64 of vrsub.vx runtime fail in RV32 system
It's quite obvious that the order of vrsub SEW64 is wrong.
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect operand order.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/bug-23.C: New test.
It's quite obvious that the order of vrsub SEW64 is wrong.
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect operand order.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/bug-23.C: New test.
| gcc/config/riscv/vector.md | diffblobblamehistory | |
| gcc/testsuite/g++.target/riscv/rvv/base/bug-23.C | [new file with mode: 0644] | blob |