RISC-V: Support cond vmulh.vv and vmulu.vv autovec patterns

RISC-V: Support cond vmulh.vv and vmulu.vv autovec patterns

This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
currently. We will send another patch to take this issue.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*cond_<mulh_table><mode>3_highpart):
	New combine pattern.
	* config/riscv/autovec.md (smul<mode>3_highpart): Mrege smul and umul.
	(<mulh_table><mode>3_highpart): Merged pattern.
	(umul<mode>3_highpart): Mrege smul and umul.
	* config/riscv/vector-iterators.md (umul): New iterators.
	(UNSPEC_VMULHU): New iterators.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: New test.